JP2011034622A - Built-in memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a built-in memory which is comparatively inexpensive and also secures the quality to some extent. <P>SOLUTION: The built-in memory includes: a plurality of memories for storing data; a first voltage means to apply a voltage to the memories, for recording the data to the memories or reading out the data being stored in the memories; a second voltage means to apply a voltage to the memories, which is higher than the voltage to be applied to the memories by the first voltage means; and a control means for controlling the second voltage means so that the voltage is applied to all or some among the memories other than a part of memories, in accordance with the first voltage means applying the voltage to some memories among the plurality of memories, until predetermined requirement is satisfied after a use of a self-device is started. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a built-in memory, and more particularly to a built-in memory built in an electronic apparatus such as an imaging apparatus.

  Patent Document 1 discloses a test method for a semiconductor integrated circuit that performs a burn-in test. By performing a burn-in test before shipment of the semiconductor integrated circuit, a defective area in the semiconductor integrated circuit can be made an area that cannot be accessed in advance.

JP 2001-167600 A

  However, if a burn-in test is performed on a semiconductor integrated circuit such as a built-in memory before shipping, it will take time until shipping. As a result, the cost of a semiconductor integrated circuit such as a built-in memory also increases.

  An object of the present invention is to provide a built-in memory that is relatively inexpensive and has a certain level of quality.

  In order to solve the above-mentioned problems, the built-in memory according to the present invention includes a plurality of memories for storing data and a memory for recording data in the memory or reading data stored in the memory. A first voltage means for applying a voltage; a second voltage means for applying a voltage higher than the voltage applied to the memory by the first voltage means; The second voltage means applies a voltage to all or some of the memories other than some of the memories in response to the first voltage means applying a voltage to some of the plurality of memories. Control means for controlling the voltage means.

  According to the present invention, it is possible to provide a built-in memory that is relatively inexpensive and has a certain level of quality.

The block diagram which shows the structure of the digital video camera 100 Schematic diagram for explaining the configuration of the internal memory 240 Flow chart for explaining the selection operation of the chip to be accessed Schematic diagram for explaining the access operation to the chip Schematic diagram for explaining the access operation to the chip

[1. Embodiment 1]
[1-1. Constitution〕
[1-2-1. Electrical configuration)
An electrical configuration of the digital video camera 100 according to the present embodiment will be described with reference to FIG. FIG. 1 is a block diagram showing a configuration of the digital video camera 100. The digital video camera 100 captures an object image formed by the optical system 110 including one or a plurality of lenses with the image sensor 140. The video data generated by the image sensor 140 is subjected to various processes by the image processing unit 160 and stored in the built-in memory 240. Hereinafter, the configuration of the digital video camera 100 will be described in detail.

  The optical system 110 includes a zoom lens and a focus lens. The subject image can be enlarged or reduced by moving the zoom lens along the optical axis. Further, the focus of the subject image can be adjusted by moving the focus lens along the optical axis.

  The lens driving unit 120 drives various lenses included in the optical system 110. For example, a zoom motor that drives a zoom lens, and a focus motor that drives a focus lens correspond to this.

  The diaphragm 300 adjusts the amount of transmitted light by adjusting the size of the opening in accordance with the setting of the user or automatically.

  The image sensor 140 captures the subject image formed by the optical system 110 and generates video data. The image sensor 140 performs various operations such as exposure, transfer, and electronic shutter.

  The A / D converter 150 converts the analog video data generated by the image sensor 140 into digital video data.

  The image processing unit 160 performs various processes on the video data generated by the image sensor 140. The image processing unit 160 processes the video data generated by the image sensor 140 to generate video data to be displayed on the display monitor 220 or to generate video data to be stored in the built-in memory 240. Or For example, the image processing unit 160 performs various processes such as gamma correction, white balance correction, and flaw correction on the video data generated by the image sensor 140. In addition, the image processing unit 160 compresses the video data with respect to the video data generated by the image sensor 140 in a compression format that conforms to an international standard such as the AVCHD standard. The image processing unit 160 can also be realized by a DSP or a microcomputer.

  The controller 180 is a control means for controlling the whole. The controller 180 can be realized by a semiconductor element or the like. The controller 180 may be configured only by hardware, or may be realized by combining hardware and software. The controller 180 can be realized by a microcomputer or the like.

  The card slot 190 is detachable from the memory card 200. The card slot 190 can be mechanically and electrically connected to the memory card 200. The memory card 200 includes a flash memory, a ferroelectric memory, and the like, and can store data such as video data generated by the image processing unit 160.

  The built-in memory 240 is composed of a flash memory or a ferroelectric low memory. The built-in memory 240 can store data such as video data generated by the image processing unit 160.

  The operation member 210 is a generic name for a user interface that receives an operation from a user. For example, a cross key, an enter button, a mode dial, a recording start button, and the like that accept an operation from the user correspond to this.

  The display monitor 220 can display a video (through video) indicated by the video data generated by the image sensor 140 and a video indicated by the video data read from the memory card 200. The display monitor 220 can also display various menu screens for performing various settings of the digital video camera 100.

[1-2-2. Internal memory configuration)
The configuration of the built-in memory 240 will be described in detail with reference to FIG. FIG. 2 is a schematic diagram for explaining the configuration of the built-in memory 240.

  NAND-0 to NAND-7 are semiconductor nonvolatile memories represented by flash memories, respectively. In order to construct a large-capacity built-in memory, the built-in memory is composed of a multi-chip flash memory. In the present embodiment, the built-in memory 240 is composed of an 8-chip flash memory.

  For example, if 8 chips of 4 GB flash memory are used, a built-in memory with a total capacity of 32 GB can be realized. The NAND controller 258 is configured by a microcomputer or a dedicated LSI. Usually, the microcomputer or the like constituting the controller 180 does not have a function of directly controlling writing and reading with respect to the flash memory of a plurality of chips, and the NAND controller 258 is based on an instruction from the controller 180. Controls writing / reading of data to / from (NAND-0 to NAND-7).

[1-3. Operation)
[1-3-1. (Selection operation of chip to access)
An operation for selecting a chip to be accessed among a plurality of chips in the built-in memory 240 will be described with reference to FIG. FIG. 3 is a flowchart for explaining a selection operation of a chip to be accessed.

  The digital video camera 100 supplies power to the internal memory 240 when recording the captured video in the internal memory (S100). When the supply of power to the internal memory 240 is started, the NAND controller 258 starts counting the number of commands given from the controller 180 to the internal memory 240 in order to measure the accumulated time that the flash memory has been used ( S101). Examples of the command include an initialization command, a WRITE command, and a READ command. By counting any or all of these commands, the accumulated time used for the flash memory can be measured. The digital video camera 100 can record the count number in any of the flash memory chips.

  When the internal memory 240 is first used and the count number has not reached the predetermined number, the digital video camera 100 writes / reads data using only the NAND-0 chip 250 (S102). Here, writing / reading of data is performed by controlling the NAND controller 258 to apply a voltage of 5 (V) to the chip.

  In response to a command issued from the controller 180, the NAND controller 258 writes / reads data to / from the NAND-0 chip and executes an erase process on the NAND-1 to 7 chips (S103). ). Here, in the erase process of the NAND memory, it is generally necessary to supply a voltage considerably higher than that of the read process to the memory cell, and the read process is controlled in units of blocks, whereas the erase process is performed in a larger access block. Can be controlled. In these two points, the Erase process is suitable for the burn-in process described above. The erase process is performed by controlling the NAND controller 258 to apply a voltage of 20 (V) to the booster circuit 259 on the chip. A defective area in the chip does not accept data writing by accepting the erase process a plurality of times. In this way, a process for improving the quality of a chip by accessing the chip before actually using the chip so as not to accept data writing for a defective area is called a burn-in process.

  When the number of commands executed reaches a predetermined number (S104), the NAND controller 258 increases the number of flash memory chips to be written / read (S105). For example, the predetermined number when increasing the number of chips used from 1 to 2 is set to 100 times, the predetermined number when increasing the number of chips used from 2 to 4 is set to 1000 times, and the number of chips used is increased from 4 to 8 The predetermined number when increasing the number is 10000 times.

  In this case, when the number of executed commands reaches 100 times, the NAND controller 258 increases the flash memory chips to be used to two chips of NAND-0 and NAND-1. At this time, the NAND controller 258 has executed 100 times of erase processing on the NAND-1 to 7 chips.

  When the command count is further continued and 1000 commands are executed, the NAND controller 258 further increases the number of flash memory chips to be used to four chips. At this point, the NAND controller 258 has executed 1100 times of erase processing on the flash memory chips of NAND-2 to NAND-7.

  Further, when the number of commands reaches 10,000 times, the NAND controller 258 increases the number of chips to be used to use all eight chips. At this point, the NAND controller 258 has executed 11100 times of erase processing on the flash memory chips of NAND-4 to NAND-7.

  After all 8 chips are used, the digital video camera 100 uses the built-in memory 240 in a state where all 8 chips are always used.

  As described above, the digital camera 100 according to the present embodiment repeats the erase process for a part of the chips included in the built-in memory for a certain period after the user starts use. As a result, the digital video camera 100 can perform burn-in processing on a part of the chips in the built-in memory even when the burn-in processing for the built-in memory is not performed in advance, and the characteristics of the built-in memory can be stabilized. Can be made.

[1-3-2. (Chip access operation)
The access operation to the chip in the built-in memory 240 will be described with reference to FIGS. 4 and 5 are schematic diagrams for explaining the access operation to the chip, respectively.

  The initial mode (1) is a mode in which one chip of flash memory is used. In the initial mode (1), the digital video camera 100 writes and reads video data using the NAND-0 chip 4GB. During this period, the NAND controller 258 executes an erase process on the seven chips NAND-1 to NAND-7 each time a command is issued from the controller 180.

  The initial mode (2) is a mode that uses two chips of flash memory. In the initial mode (2), the digital video camera 100 performs video data writing / reading using a total of 8 GB of NAND-0 and NAND-1 chips. The erase process is performed on the remaining six chips that are not written in the same manner as in the above-described mode. At this time, 4 GB of each of NAND-0 and NAND-1 is divided into small-capacity blocks of, for example, 2 MB, and alternately arranged to perform writing and reading. This is to prevent concentration of writing to either the flash memory NAND-0 or NAND-1. Thereby, the degree of quality degradation of NAND-0 and NAND-1 can be reduced.

  The initial mode (4) is a mode that uses four chips of flash memory. In the initial mode (4), the digital video camera 100 writes and reads video data using the 4-chip 16 GB. The erase process is performed on the remaining four chips that are not written in the same manner as in the above-described mode. Similarly to the above-described mode, the four chips NAND-0 to 3 are divided into, for example, small blocks of 2 MB and arranged alternately to reduce the degree of quality deterioration of the built-in memory 240.

  The normal mode is a mode after the initial modes (1) to (4) are completed, and video data is written and read as a 32 GB built-in memory using all 8 chips of the flash memory.

  The present invention can be applied to an imaging device such as a digital still camera and a digital video camera, and a built-in memory that can be built in an electronic device such as a mobile phone with a camera function.

DESCRIPTION OF SYMBOLS 100 Digital camera 110 Optical system 120 Lens drive part 140 Image sensor 150 A / D converter 160 Image processing part 180 Controller 190 Card slot 200 Memory card 210 Operation member 220 Display monitor 240 Built-in memory

Claims (1)

A plurality of memories for storing data;
First voltage means for applying a voltage to the memory in order to record data in the memory or to read data stored in the memory;
Second voltage means for applying a voltage to the memory that is higher than a voltage applied to the memory by the first voltage means;
The first voltage means applies a voltage to a part of the plurality of memories until the predetermined requirement is satisfied after the use of the own device is started. Control means for controlling the second voltage means to apply a voltage to all or a part of the memories of
Built-in memory.

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