JP2011029510A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device including an electrostatic protection element for protecting an internal circuit from electrostatic discharge damage. <P>SOLUTION: The semiconductor device includes a first circuit (internal circuit 1) driven by a first power source system, a second circuit (internal circuit 2) driven by a second power source system different from the first power source system, and a third circuit (internal circuit 3) driven by a third power source system generated by a step-down circuit (step-down circuit 4) included in the first circuit. A first electrostatic protection element (diode D3) is provided between the power supply wiring VDD2 of the second circuit and the power supply wiring VDD3 of the third circuit. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device including an electrostatic protection element for protecting an internal circuit from electrostatic breakdown.

  In order to protect a semiconductor device from electrostatic discharge (ESD), a diode, a transistor, or the like is used as an ESD protection element.

  In the ESD protection element, the breakdown voltage at which the protection element starts to operate needs to be lower than the gate breakdown voltage of the transistor constituting the semiconductor device.

JP 2004-228138 A

  FIG. 1 is a diagram showing the dependence of the gate oxide thickness on the breakdown voltage and gate oxide breakdown voltage of the MOS transistor. FIG. 1 shows that the breakdown voltage and the gate oxide breakdown voltage of the MOS transistor are reversed when the gate oxide film thickness becomes a certain value or less. The gate oxide film thickness at the time of reversal is influenced by the structure of the MOS transistor and the film quality of the oxide film.

As semiconductors become finer in the future, the gate oxide film becomes thinner, so it is necessary to lower the operation start voltage of the protection element as a technique for protecting the internal circuit from electrostatic breakdown. For example, Patent Document 1 discloses a technique for adding a trigger element in order to lower the operation start voltage of a protection element.
However, this method requires a plurality of elements for triggering, and also requires a signal line for triggering and a circuit for driving the signal line, complicating the structure of the protection element. For this reason, there is a problem that the ratio of the protective element to the semiconductor chip is increased.

  The present invention relates to a first circuit driven by a first power supply system, a second circuit driven by a second power supply system different from the first power supply system, and a step-down included in the first circuit. A third circuit driven by a third power supply system generated by the circuit, wherein the power supply voltage level of the second circuit is higher than the power supply voltage level of the third circuit, A semiconductor device comprising a first electrostatic protection element between the power supply wiring of the second circuit and the power supply wiring of the third circuit.

  According to the semiconductor device of the present invention, the third circuit is connected only by providing the first electrostatic protection element between the power supply wiring of the second circuit and the power supply wiring of the third circuit. The electrostatic stress transmitted to the power supply wiring VDD3 can be quickly released to the power supply wiring VDD2, and the third circuit can be protected from electrostatic breakdown. In addition, when the electrostatic protection element is originally provided in the first electrostatic protection element or the third circuit, the signal line is used to control these protection elements including the electrostatic protection element. And a configuration that does not require a circuit. Therefore, the effect of reducing the ratio of the protective element to the semiconductor chip can be achieved without complicating the structure of the protective element.

It is a characteristic view of a MOS transistor. It is a circuit diagram of the electrostatic protection element with which the semiconductor device of the related technology of this invention is provided. It is a circuit diagram of the electrostatic protection element with which the semiconductor device of the present invention is provided. FIG. 4 is a layout diagram of a diode D3 in FIG. 3. It is sectional drawing of the diode D3 in FIG. It is a circuit diagram of the electrostatic protection element with which the semiconductor device of the present invention is provided. It is a circuit diagram of the electrostatic protection element with which the semiconductor device of the present invention is provided. It is a layout figure which shows the other structural example of the diode in the semiconductor device of this invention. It is sectional drawing of the diode in FIG.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
First, prior to describing the present invention, related techniques of the present invention will be described.
FIG. 2 shows a configuration before the present invention is applied. The semiconductor device 100 in FIG. 2 includes an internal circuit 1 (first circuit) driven by a first power supply system (a power supply system that supplies power through the power supply wiring VDD1 and the ground wiring VSS1), and a second power supply system ( An internal circuit 2 (second circuit) driven by a power supply line VDD2 and a power supply system that supplies power through the ground wiring VSS2, and a third power supply system (power supply system that supplies power through the power supply wiring VDD3 and ground wiring VSS1). ) Is driven by an internal circuit 3 (third circuit). Here, a power supply voltage level obtained by stepping down the voltage level of the power supply wiring VDD1 is supplied to the power supply wiring VDD3 by the step-down circuit 4 driven by the first power supply system.

  Further, between the power supply wiring and the ground wiring of each power supply system, a protection element a (transistor Qn1), a protection element as a protection element for protecting each of the internal circuit 1, the internal circuit 2, and the internal circuit 3 from electrostatic breakdown An element b (transistor Qn2) and a protection element c (transistor Qn3) are provided.

  The transistors constituting the internal circuit 1 and the transistor Qn1 are composed of MOS transistors having thick gate oxide films. The transistors constituting the internal circuit 3 and the transistor Qn3 are composed of MOS transistors having a thinner gate oxide film than the transistors constituting the internal circuit 1 and the like. Further, the internal circuit 2 and the transistor Qn2 connected to the second power supply system are composed of MOS transistors having a thicker gate oxide film than the transistors and the like constituting the internal circuit 3. For example, when the voltage level of the second power supply wiring VDD2 is the same as the voltage level of the power supply wiring VDD1, the gate oxide film thickness of the internal circuit 2 and the transistor Qn2 is the same as that of the internal circuit 1 and the transistor Qn1.

  When the semiconductor device 100 is a semiconductor memory, for example, the first power supply system is a power supply system that drives a normal circuit to which external power is applied as it is, and the second power supply system drives an output transistor. The third power supply system is a power supply system for peripheral circuits that operate at a step-down voltage.

Here, when a positive electrostatic stress is applied between the power supply wiring VDD1 and the ground wiring VSS1 of the semiconductor device shown in FIG. 2, the MOS transistor Qn1 is conducted to discharge the stress to the ground wiring VSS1, thereby causing an internal circuit. Prevent 1 from electrostatic breakdown. However, some of the applied electrostatic stress may be transmitted to the power supply wiring VDD3 through the step-down circuit 4. In such a case, the protection element c (MOS transistor Qn3) may be connected to the step-down circuit 4 for the purpose of protecting the internal circuit 3 connected to the power supply wiring VDD3.
However, as the semiconductor device becomes finer, the breakdown voltage of the transistor Qn3 becomes higher than the breakdown voltage of the gate oxide film.

(First embodiment)
FIG. 3 is a circuit diagram showing connection of protection elements in the semiconductor device of the present invention. In FIG. 3, the same parts as those in FIG.
The semiconductor device 200 in FIG. 3 includes an internal circuit 1 (first circuit) driven by a first power supply system (a power supply system that supplies power by the power supply wiring VDD1 and the ground wiring VSS1), and a second power supply system ( An internal circuit 2 (second circuit) driven by a power supply line VDD2 and a power supply system that supplies power through the ground wiring VSS2 and a third power supply system (power supply system that supplies power through the power supply wiring VDD3 and the ground wiring VSS1) ) Is driven by an internal circuit 3 (third circuit).

Here, a power supply voltage level obtained by stepping down the voltage level of the power supply wiring VDD1 is supplied to the power supply wiring VDD3 by the step-down circuit 4 driven by the first power supply system. Further, a power supply voltage level higher than the voltage level of the power supply wiring VDD3 is supplied to the power supply wiring VDD2 from a second power supply system different from the first power supply system. That is, the voltage level of the power supply wiring VDD3 is the lowest among the voltage levels of the power supply wiring VDD1, the power supply wiring VDD2, and the power supply wiring VDD3.
In addition, between the power supply wiring and the ground wiring of each power supply system, a protection element a (transistor Qn1) and a protection element b (protection element b) are respectively provided as protection elements for protecting the internal circuit 1 and the internal circuit 2 from electrostatic breakdown. Transistor Qn2) is provided. Note that the protection element c (transistor Qn3) provided in the internal circuit 3 in FIG. 2 is not necessarily shown in the semiconductor device 200 in the present embodiment, and is not shown.

  Further, as a countermeasure against electrostatic breakdown generally performed in a semiconductor device having a plurality of power supply systems, an electrostatic protection element (diode D1, diode D1) is provided between the first ground wiring VSS1 and the second ground wiring VSS2. D2) is connected, but these diodes are not necessarily connected.

  The transistors constituting the internal circuit 1 and the transistor Qn1 are composed of MOS transistors having thick gate oxide films. The transistors constituting the internal circuit 3 and the transistor Qn3 are composed of MOS transistors having a thinner gate oxide film than the transistors constituting the internal circuit 1 and the like. Further, the internal circuit 2 and the transistor Qn2 connected to the second power supply system are composed of MOS transistors having a thicker gate oxide film than the transistors and the like constituting the internal circuit 3. For example, when the voltage level of the second power supply wiring VDD2 is the same as the voltage level of the power supply wiring VDD1, the gate oxide film thickness of the internal circuit 2 and the transistor Qn2 is the same as that of the internal circuit 1 and the transistor Qn1.

  When the semiconductor device 200 is a semiconductor memory, for example, the first power supply system is a power supply system that drives a normal circuit to which external power is applied as it is, and the second power supply system drives an output transistor. The third power supply system is a power supply system for peripheral circuits that operate at a step-down voltage.

In the semiconductor device 200, unlike the semiconductor device 100 in FIG. 2, a protective element that releases electrostatic stress applied to the third power supply system between the power supply wiring VDD3 and the power supply wiring VDD2 to the second power supply system. (Diode D3) is connected.
The diode D3 is a protective element that discharges electrostatic stress applied to the power supply wiring VDD3 from the power supply wiring VDD1 through the step-down circuit 4 to the power supply wiring VDD2.
Here, the electrostatic stress applied to the power supply wiring VDD3 is electrostatic stress that could not be discharged by the first protection element (transistor Qn1) connected to the power supply wiring VDD1, and was transmitted through the step-down circuit 4. Since it is an electrostatic stress, its strength is weak compared to the electrostatic stress applied from the outside.

For this reason, after electrostatic stress is discharged to the power supply wiring VDD2 that is the discharge destination, even if the discharge destination of the electrostatic stress is not sufficiently formed, the load capacitance of the power supply wiring itself connected to the power supply wiring VDD2, for example, semiconductor to power supply wiring If the parasitic capacitance to the substrate is large, electrostatic stress can be absorbed. Further, the discharge capability of the diode D3 is not necessarily increased because the electrostatic stress to be discharged is also weak. Therefore, the layout dimension of the diode D3 may be determined in consideration of the relationship between the electrostatic stress discharge capability of the protection element a (transistor Qn1) and the electrostatic stress applied to the power supply wiring VDD2.
Further, in a normal operation state, the power supply voltage level of the second circuit is higher than the power supply voltage level of the third circuit, so that no forward current flows through the diode D3.

4 and 5 are a plan view and a cross-sectional view of the diode D3.
As shown in FIG. 4, the diode D3 is formed in an N well layer NW formed on a P-type semiconductor substrate Psub (not shown). An element isolation region is provided on the surface of the semiconductor substrate so as to surround a rectangular P-type diffusion layer PD provided in the center of the N-well layer NW, and an N-type diffusion layer ND is provided therearound.

FIG. 5 is a cross-sectional view corresponding to AA ′ in FIG. An N well layer NW is formed on the P type semiconductor substrate Psub, and an N type diffusion layer ND and a P type diffusion layer PD are formed inside the N well layer NW. The N-type diffusion layer ND is connected to the power supply wiring VDD2 through a contact hole (not shown) and a metal wiring indicated by a solid line. The N-type diffusion layer ND is connected to the power supply wiring VDD3 via a contact hole (not shown) and a metal wiring indicated by a solid line.
The diode D3 configured as described above is a diode having the anode electrode as the power supply wiring VDD3 and the cathode electrode as the power supply wiring VDD2, and the discharge capability thereof can be adjusted by changing the area of the P-type diffusion layer PD.

  As described above, the semiconductor device according to the present embodiment is driven by the first circuit (internal circuit 1) driven by the first power supply system and the second power supply system different from the first power supply system. 2 circuit (internal circuit 2), and a third circuit (internal circuit 3) driven by a third power supply system generated by a step-down circuit (step-down circuit 4) included in the first circuit. In the semiconductor device (semiconductor device 200), the power supply voltage level of the second circuit is higher than the power supply voltage level of the third circuit, the power supply wiring (power supply wiring VDD2) of the second circuit, and the third circuit The first electrostatic protection element (diode D3) is provided between the power supply wiring (power supply wiring VDD3) and the semiconductor device.

  According to the semiconductor device of the present invention, between the power supply wiring (power supply wiring VDD2) of the second circuit (internal circuit 2) and the power supply wiring (power supply wiring VDD3) of the third circuit (internal circuit 3), By providing only the first electrostatic protection element (diode D3), the static stress transmitted to the power supply wiring VDD3 to which the third circuit (internal circuit 3) is connected can be quickly released to the power supply wiring VDD2. The third circuit (internal circuit 3) can be protected from electrostatic breakdown.

  In addition, when the electrostatic protection element is originally provided in the first electrostatic protection element (diode D3) or the third circuit, the protection element including the electrostatic protection element is controlled. In addition, no signal line or circuit is required. Therefore, the effect of reducing the ratio of the protective element to the semiconductor chip can be achieved without complicating the structure of the protective element.

(Second Embodiment)
Next, another embodiment of the present invention will be described with reference to the attached drawing (FIG. 6).
FIG. 6 is a circuit diagram showing connection of protection elements in the semiconductor device of the present invention. 6, the same parts as those in FIGS. 2 and 3 are denoted by the same reference numerals, and the description thereof is omitted.
In the semiconductor device 300 in FIG. 3, the protective element c (transistor Qn3) provided in the internal circuit 3 shown in FIG. 2 is connected.
In the semiconductor device 300 according to the present embodiment, electrostatic stress that enters the power supply wiring VDD3 is released to the power supply wiring VDD2 by the discharge of the diode D3 until the protection element c (transistor Qn3) operates.

  That is, as described in the problem to be solved by the invention, as the semiconductor becomes finer in the future, the breakdown voltage of the transistor Qn3 is likely to be higher than the breakdown voltage of the gate oxide film thickness. Therefore, as a technique for protecting the internal circuit 3 from electrostatic breakdown, it is not applied to the breakdown voltage of the protection element c (transistor Qn3), but is applied to the internal circuit 3 during a period until the breakdown voltage is reached. The electrostatic stress is quickly released to the power supply wiring VDD2 by the diode D3.

(Third embodiment)
Next, another embodiment of the present invention will be described with reference to the attached drawing (FIG. 7).
FIG. 7 is a circuit diagram showing connection of protection elements in the semiconductor device of the present invention. 7, the same parts as those in FIGS. 3 and 6 are denoted by the same reference numerals, and the description thereof is omitted.
In the semiconductor device 400 in FIG. 7, the connection position of the diode D3 with the power supply wiring VDD3 is shown in the vicinity of the step-down circuit 4. A capacitor C1 is connected to the power supply wiring VDD3 for the purpose of preventing a voltage drop when the connected circuit operates.

  When the electrostatic stress applied to the internal circuit 3 is small, the electrostatic stress may be absorbed even with the capacitor C1 alone, but depending on the position of the connected capacitor C1, the internal stress may be reduced before the electrostatic stress is absorbed by the capacitor C1. The circuit 3 may be destroyed. In order to prevent this, it is desirable to dispose the diode D3 near the step-down circuit 4.

At this time, by connecting the diode D3 between the power supply wiring VDD3 and the power supply wiring VDD2, electrostatic stress applied to the power supply wiring VDD2 breaks down the diode D3 in the reverse direction and enters the power supply wiring VDD3. There is a problem of coming.
For this, the breakdown voltage of the protection element b (transistor Qn2) connected to the power supply wiring VDD2 may be set to be lower than the breakdown voltage of the diode D3.

  Specifically, the gate oxide film thickness of the transistor Qn2 is adjusted, for example, the gate oxide film thickness is reduced so that the breakdown voltage of the transistor Qn2 is lower than the breakdown voltage of the diode D3. Alternatively, there is a method of increasing the breakdown voltage by adjusting the impurity concentration of the diode D3, for example, by reducing the impurity concentration for forming the P-type diffusion layer PD.

Alternatively, there is a method of changing the structure of the diode D3 in order to increase the breakdown voltage of the diode D3. 8 and 9 are a plan view and a cross-sectional view showing the structure of a diode D3a that can be used in place of the diode D3 commonly used in the semiconductor devices 200, 300, and 400, respectively.
As shown in FIG. 8, the diode D3a is formed in an N well layer NW formed on a P-type semiconductor substrate Psub (not shown). An element isolation region is provided on the surface of the semiconductor substrate so as to surround a rectangular P-type diffusion layer PD provided in the center of the N-well layer NW, and an N-type diffusion layer ND is provided therearound. The diode D3a is different from the diode D3 shown in FIG. 4 as follows.

  The P-type diffusion layer PD is provided in a rectangular P well layer PW (not shown). Unlike the diode D3, the N well layer NW is provided in contact with the P well layer PW and surrounding the P well layer PW. Further, a rectangular deep N well layer (hereinafter referred to as DN well layer DNW) is newly provided inside the outer periphery of the N well layer NW while surrounding the P well layer PW.

  FIG. 9 is a cross-sectional view corresponding to A-A ′ in FIG. 8. As described above, the P type diffusion layer PD is provided in the P well layer PW, and the P well layer PW is electrically separated from the P type semiconductor substrate Psub by the DN well layer DNW. DN well layer DNW is electrically connected to N well layer NW. The N-type diffusion layer ND and the P-type diffusion layer PD are respectively connected to the power supply wiring VDD2 and the power supply wiring VDD3 through a contact hole (not shown) and a metal wiring indicated by a solid line.

  The diode D3a configured as described above is a diode in which the anode electrode is the power supply wiring VDD3 and the cathode electrode is the power supply wiring VDD2, and the discharge capability can be adjusted by changing the area of the P-type diffusion layer PD. Also, by providing the DN well layer DNW, the breakdown voltage of the diode D3a can be increased to the breakdown voltage of the N well layer NW or the DN well layer DNW with respect to the P well layer PW.

  As described above, the semiconductor device according to the present embodiment is driven by the first circuit (internal circuit 1) driven by the first power supply system and the second power supply system different from the first power supply system. 2 circuit (internal circuit 2), and a third circuit (internal circuit 3) driven by a third power supply system generated by a step-down circuit (step-down circuit 4) included in the first circuit. In the semiconductor device (semiconductor device 200, 300, 400), the power supply voltage level of the second circuit is higher than the power supply voltage level of the third circuit, and the power supply wiring (power supply wiring VDD2) of the second circuit; The semiconductor device includes a first electrostatic protection element (diode D3a) between the power supply wiring (power supply wiring VDD3) of the third circuit.

  Further, in the semiconductor device, a second electrostatic protection element (transistor Qn2) is provided between the power supply wiring (power supply wiring VDD2) and the ground wiring of the second circuit (internal circuit 2), and the first electrostatic protection element (transistor Qn2) is provided. The electric protection element (diode D3a) has a breakdown voltage higher than that of the second electrostatic protection element (transistor Qn2).

  As a result, while maintaining the effect of the first embodiment, the breakdown voltage of the diode D3a can be made higher than the breakdown voltage of the protection element b (transistor Qn2) connected to the power supply wiring VDD2. The problem that electrostatic stress applied to the power supply wiring VDD2 breaks down the diode D3a and enters the power supply wiring VDD3 can be solved.

  As mentioned above, although the invention made | formed by this inventor was demonstrated based on embodiment, it cannot be overemphasized that this invention is not limited to embodiment demonstrated, and can be variously changed in the range which does not deviate from the summary. . In this embodiment, a semiconductor device using a MOS transistor as a protection element has been described. However, a metal-insulator-silicon (MIS) transistor can be applied as the protection element. The present invention can also be applied to a semiconductor device using a bipolar transistor as a protective element. In that case, in the case of an NPN bipolar transistor, the base may be an anode and a collector may be a cathode, or a base may be an anode and an emitter may be a cathode.

DESCRIPTION OF SYMBOLS 100, 200, 300, 400 ... Semiconductor device, 1, 2, 3 ... Internal circuit, a, b, c ... Protection element, VDD1, VDD2, VDD3 ... Power supply wiring, VSS1, VSS2 ... Ground wiring, 4 ... Step-down circuit, Qn1, Qn2, Qn3 ... transistor, D1, D2, D3, D3a ... diode, C1 ... capacitance, ND ... N type diffusion layer, PD ... P type diffusion layer, NW ... N well layer, PW ... P well layer, DNW ... DN well layer, Psub ... P-type semiconductor substrate

Claims (7)

A first circuit driven by a first power supply system; a second circuit driven by a second power supply system different from the first power supply system; and a step-down circuit included in the first circuit. A third circuit driven by a generated third power supply system, and a semiconductor device comprising:
The power supply voltage level of the second circuit is higher than the power supply voltage level of the third circuit,
A semiconductor device comprising a first electrostatic protection element between a power supply wiring of the second circuit and a power supply wiring of the third circuit.   2. The semiconductor device according to claim 1, wherein the gate oxide film of the transistor constituting the third circuit is thinner than the gate oxide film of the transistor constituting the first circuit.   The semiconductor device according to claim 1, wherein the first electrostatic protection element is a diode.   4. The semiconductor device according to claim 1, wherein the first electrostatic protection element is disposed adjacent to the step-down circuit. 5.   A second electrostatic protection element is provided between the power supply wiring and the ground wiring of the second circuit, and the first electrostatic protection element has a breakdown voltage higher than that of the second electrostatic protection element. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device.   6. The semiconductor device according to claim 1, wherein a capacitor element is provided between a power supply wiring and a ground wiring of the second circuit.   7. The third electrostatic protection element is provided between the ground wiring of the first power supply system and the ground wiring of the second power supply system. 7. A semiconductor device according to 1.

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