JP2011029509A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device that achieves an increase of a driving current by expanding a channel region, and to provide a method of manufacturing the same. <P>SOLUTION: A semiconductor device comprises an active region 5 insulated and separated by an embedded insulating film 3 embedded in a semiconductor substrate 2, a gate electrode 7 formed over the active region 5 via a gate insulating film 6 formed on the active region 5, a source region 8 and a drain region 9 formed by implementing ions into the active region 5 at both sides with the gate electrode 7 therebetween. In the active region 5, a groove 10 is provided. A trench-type channel structure is included by embedding part of the gate electrode 7 inside the groove 10 via the gate insulating film 6. Recesses 11 are provided in counter to both side surfaces of the active region 5 and by forming a narrow part 12 between these recesses 11, a channel region 13 wider than the narrow part 12 is formed at least between a bottom of the groove 10 and the narrow part 12. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

  In recent years, with the miniaturization of semiconductor elements, the size of transistors tends to be reduced, and due to this size reduction, the short channel effect of transistors has become more prominent. For example, in DRAM (Dynamic Random Access Memory) and the like, the transistor channel length is reduced by reducing the memory cell size, so that the performance of the transistor is lowered, and the retention and write characteristics of the memory cell are deteriorated. It has become a problem.

  Therefore, in order to solve such problems, a recess (trench) FET (Field Effect Transistor) having a three-dimensional channel by forming a groove (trench) in a semiconductor substrate and a silicon fin are formed. Fin type FETs having a three-dimensional channel structure have been developed (see, for example, Patent Documents 1 to 3).

  Specifically, the trench FET has a three-dimensional channel structure by forming a groove in a semiconductor substrate and forming a gate electrode in the groove via a gate insulating film. On the other hand, the fin-type FET has a three-dimensional channel structure by forming a silicon fin on a semiconductor substrate and forming a gate electrode across the fin. In any case, since the gate length can be increased, the short channel effect can be suppressed.

Japanese Patent Laying-Open No. 2005-064500 JP 2007-027753 A JP 2007-305827 A

  By the way, in the conventional trench FET described above, the fin-shaped side walls formed in pairs on both side surfaces of the groove portion of the active region function as a channel region, but the threshold voltage is lower than the channel region of the side wall at the bottom portion of the groove portion. Since it becomes high, it was difficult to function as a channel region.

  A semiconductor device according to the present invention includes an active region insulated and isolated by a buried insulating film embedded in a semiconductor substrate, and a gate formed so as to straddle the active region via a gate insulating film formed on the active region A source region and a drain region formed by ion implantation into the active region on both sides of the electrode and the gate electrode, and a groove portion is provided in the active region, and a gate insulating film is interposed inside the groove portion It has a trench type channel structure in which a part of the gate electrode is embedded, and concave portions are provided opposite to both side surfaces of the active region, and a narrow portion is formed between these concave portions, so that at least A channel region that is wider than the narrow portion is formed between the bottom surface of the groove portion and the narrow portion.

  Also, the method of manufacturing a semiconductor device according to the present invention straddles the active region via the active region isolated by the embedded insulating film embedded in the semiconductor substrate and the gate insulating film formed on the active region. A buried insulating film is embedded in a semiconductor substrate when manufacturing a semiconductor device having a gate electrode formed on the gate electrode and a drain region and a source region formed by ion implantation into active regions on both sides of the gate electrode. Forming a narrow portion between the opposing concave portions on both side surfaces of the active region by forming a concave portion that is wider than the groove portion by isotropic etching after the groove portion is formed. And forming a groove on the upper surface of the active region at a depth reaching the front of the recess, so that at least the width between the bottom surface of the groove and the narrow portion is wider than the narrow portion. Characterized in that it comprises a step of forming a channel region becomes.

  As described above, in the present invention, a channel region that is wider than the narrow portion is formed at least between the bottom surface of the groove portion and the narrow portion, thereby expanding the channel region and increasing the drive current. It is possible to plan. In addition, since the on / off controllability of the transistor by the gate electrode is improved, a semiconductor device having excellent switching characteristics can be provided.

FIG. 1 is a plan view showing the structure of a trench gate transistor shown as the first embodiment. FIG. 2 is a cross-sectional view showing the structure of the trench gate transistor shown as the first embodiment. FIG. 3 is a cross-sectional view showing the operation of the trench gate transistor shown as the first embodiment. FIG. 4 is a diagram sequentially illustrating the manufacturing process of the trench gate transistor shown as the first embodiment. FIG. 5 is a diagram sequentially illustrating the manufacturing process of the trench gate transistor shown as the first embodiment. FIG. 6 is a diagram sequentially illustrating the manufacturing process of the trench gate transistor shown as the first embodiment. FIG. 7 is a diagram sequentially illustrating the manufacturing process of the trench gate transistor shown as the first embodiment. FIG. 8 is a diagram sequentially illustrating the manufacturing process of the trench gate transistor shown as the first embodiment. FIG. 9 is a diagram sequentially illustrating the manufacturing process of the trench gate transistor shown as the first embodiment. FIG. 10 is a diagram sequentially illustrating the manufacturing process of the trench gate transistor shown as the first embodiment. FIG. 11 is a diagram sequentially illustrating the manufacturing process of the trench gate transistor shown as the first embodiment. FIG. 12 is a diagram sequentially illustrating the manufacturing process of the trench gate transistor shown as the first embodiment. FIG. 13 is a diagram sequentially illustrating the manufacturing process of the trench gate transistor shown as the first embodiment. FIG. 14 is a diagram sequentially illustrating the manufacturing process of the trench gate transistor shown as the first embodiment. FIG. 15 is a diagram sequentially illustrating the manufacturing process of the trench gate transistor shown as the first embodiment. FIG. 16 is a diagram sequentially illustrating the manufacturing process of the trench gate transistor shown as the first embodiment. FIG. 17 is a cross-sectional view showing the structure of the trench gate transistor shown as the second embodiment. FIG. 18 is a diagram sequentially illustrating the manufacturing process of the trench gate transistor shown as the second embodiment. FIG. 19 is a diagram sequentially illustrating the manufacturing process of the trench gate transistor shown as the second embodiment. FIG. 20 is a diagram sequentially illustrating the manufacturing process of the trench gate transistor shown as the second embodiment. FIG. 21 is a diagram sequentially showing the manufacturing process of the trench gate transistor shown as the second embodiment. FIG. 22 is a plan view showing the structure of a trench gate transistor shown as the third embodiment. FIG. 23 is a diagram sequentially illustrating the manufacturing process of the trench gate transistor shown as the third embodiment. FIG. 24 is a diagram sequentially illustrating the manufacturing process of the trench gate transistor shown as the third embodiment. FIG. 25 is a diagram sequentially illustrating the manufacturing process of the trench gate transistor shown as the third embodiment. FIG. 26 is a diagram sequentially illustrating the manufacturing process of the trench gate transistor shown as the third embodiment. FIG. 27 is a cross-sectional view showing the structure of the trench gate transistor shown as the third embodiment. FIG. 28 is a diagram sequentially illustrating the manufacturing process of the trench gate transistor shown as the third embodiment. FIG. 29 is a diagram sequentially illustrating the manufacturing process of the trench gate transistor shown as the third embodiment.

Hereinafter, a semiconductor device to which the present invention is applied and a manufacturing method thereof will be described in detail with reference to the drawings.
In addition, in the drawings used in the following description, in order to make the features easy to understand, there are cases where the portions that become the features are enlarged for the sake of convenience, and the dimensional ratios of the respective components are not always the same as the actual ones. Absent.

(First embodiment)
First, a semiconductor device including a trench gate transistor 1 shown in FIGS. 1 and 2A to 2C will be described as a first embodiment of the present invention. 2A is a cross-sectional view taken along line AA ′ shown in FIG. 1, FIG. 2B is a cross-sectional view taken along line BB ′ shown in FIG. 1, and FIG. ) Shows a cross-sectional view taken along the line CC ′ shown in FIG.

  The trench gate transistor 1 is formed by embedding a buried insulating film 3 in a semiconductor substrate 2 and a groove portion 2a formed in the semiconductor substrate 2 as shown in FIGS. 1 and 2A to 2C. The element isolation region 4, the active region 5 isolated by the element isolation region 4, the gate insulating film 6 formed on the active region 5, and the active region 5 through the gate insulating film 6 A gate electrode 7 formed so as to straddle and a source region 8 and a drain region 9 formed by implanting impurity ions into the active regions 5 on both sides of the gate electrode 7, and a groove portion in the active region 5 10 has a trench-type channel structure in which a part of the gate electrode 7 is buried inside the groove 10 via the gate insulating film 6.

  In the trench gate transistor 1, by adopting such a trench type channel structure, the channel length of the trench gate transistor 1 can be increased without increasing the horizontal area of the gate electrode 7, and as a result, It is possible to suppress the short channel effect.

  The semiconductor substrate 2 is formed of a substrate containing a predetermined concentration of impurities, for example, a silicon substrate. Further, the semiconductor substrate 2 may be any substrate as long as the surface layer is made of silicon. As such a substrate, an SOI in which a silicon thin film is formed on a buried oxide (BOX) film in addition to a silicon substrate. A (Silicon on Insulator) substrate may be used. When such an SOI substrate is used, since the junction capacitance between the source and the drain can be reduced, it is possible to cope with further miniaturization.

  The element isolation region 4 is called STI (Shallow Trench Isolation), and a plurality of active regions 5 are defined by embedding a buried insulating film 3 in a groove 2 a formed in the surface layer of the semiconductor substrate 2. .

  The active region 5 is a part of the semiconductor substrate 2 that is insulated and isolated by the buried insulating film 3 (element isolation region 4), and its shape in plan view is, for example, a shape in which both ends of a rectangle are rounded. In addition, a plurality of active regions 5 are provided in the horizontal direction X and the vertical direction Y at predetermined intervals in the plane of the semiconductor substrate 2.

  The gate insulating film 6 is made of, for example, a silicon oxide film obtained by oxidizing the surface (upper surface) of the active region 5 by a thermal oxidation method. The gate electrode 7 is made of, for example, a silicon film 29 doped with impurities, or a barrier metal film such as titanium nitride. 30 and at least one conductive film in which a tungsten film 31 is laminated. Further, a silicon nitride film 32 is provided on the tungsten film 31.

  In the source region 8 and the drain region 9, an impurity diffusion layer is formed by ion implantation at the central portion and both ends of each active region 5 across the gate electrode 7. Of these impurity diffusion layers, the central portion is The drain region 9 and both ends form a source region 8.

  The trench gate transistor 1 is used, for example, as a memory cell selection transistor arranged in a cell array region of a DRAM (Dynamic Random Access Memory). The cell array region is a 2-bit memory cell in one active region. Are arranged. For this reason, as shown in FIG. 1, a plurality of the gate electrodes 7 are provided side by side in a direction intersecting with the active region 5 at a predetermined interval. Of these, two gate electrodes 7 straddling the active region 5 are provided in the DRAM. It functions as the word line 7a, and the rest functions as the dummy word line 7b.

  Although not shown, the trench gate transistor 1 further includes a sidewall spacer covering both side surfaces of the gate electrode 7, a hard mask laminated on the gate electrode 7, the gate electrode 7, and the source region 8. A cell transistor in the DRAM is configured by including an interlayer insulating film that covers the surface on which the drain region 9 is formed and a contact plug embedded in a contact hole formed in the interlayer insulating film. In the DRAM, peripheral transistors, gate lines, bit lines, word lines (gate electrodes 7), capacitive contact plugs, capacitors, wirings, and the like are provided.

  By the way, in the trench gate transistor 1 to which the present invention is applied, the recesses 11 are provided opposite to both sides of the active region 5, and the narrow portion 12 is formed between these recesses 11, so that at least the trench 10. A channel region 13 that is wider than the narrow portion 12 is formed between the bottom surface of the thin film and the narrow portion 12. In the first embodiment, the channel region 13 is formed from the bottom surface of the groove portion 10 to both side surfaces of the groove portion 10.

  Specifically, in the cross section in the direction perpendicular to the longitudinal direction of the active region 5, the concave portions 11 are formed inwardly from the mutually opposing side surfaces of the active region 5, thereby being confined between the concave portions 11. A narrow portion 12 having a shape is formed. Further, the buried insulating film 3 is buried in the recesses 11. Note that the recess 11 may be a gap without embedding the buried insulating film 3. Further, since the narrow portion 12 is a part of the semiconductor substrate 2, it is possible to apply a bias to the semiconductor substrate 2.

  The channel region 13 is wider than the narrow portion 12 between the bottom surface of the groove portion 10 and the narrow portion 12 by forming the groove portion 10 on the upper surface of the active region 5 at a depth reaching the front of the concave portion 11. Bottom channel region 13a and a pair of side channel regions 13b rising upward from both ends of the bottom channel region 13a.

  In addition, a first sidewall 14 that covers the side surface of the gate electrode 7 embedded in the trench 10 is provided on the upper portion of the side channel region 13b. Further, the first sidewall and the side channel region 13b A second sidewall 15 covering the side surface is provided.

  In the trench gate transistor 1 having the above-described structure, as shown in FIG. 3, by applying a threshold voltage to the gate electrode 7, the side portion from the bottom channel region 13a is formed on the surface of the channel region 13 on the gate electrode side. An inversion layer region T is formed over the channel region 13b. Thereby, a high conductance can be achieved between the source region 8 and the drain region 9.

  On the other hand, in the trench gate transistor 1, a fully depleted region S is formed from the bottom channel region 13a to the side channel region 13b on the semiconductor substrate 2 side of the channel region 13 during operation. As a result, the active region 5 has an SOI structure, and good subthreshold characteristics can be obtained. That is, it has characteristics of a small threshold voltage and a high driving capability.

  As described above, in the present invention, by forming the channel region 13 wider than the narrow portion 12 at least between the bottom surface of the groove portion 10 and the narrow portion 12, the channel region 13 is enlarged, It is possible to increase the drive current. In addition, since the on / off controllability of the transistor by the gate electrode 7 is improved, a semiconductor device having excellent switching characteristics can be provided.

Next, as a method for manufacturing a semiconductor device to which the present invention is applied, a case where the trench gate transistor 1 is manufactured will be described with reference to FIGS.
Note that the materials, dimensions, and the like exemplified in the following description are merely examples, and the present invention is not necessarily limited thereto, and can be implemented with appropriate modifications within a range that does not change the gist thereof. .

  When the trench gate transistor 1 is manufactured, first, as shown in FIG. 4, a silicon substrate is prepared as the semiconductor substrate 2 before processing, and the surface of the semiconductor substrate 2 is oxidized by, for example, thermal oxidation to form silicon oxide. After the film (first oxide film) 21 is formed, a silicon nitride film (first nitride film) 22 is formed thereon, for example, by LP-CVD.

  Then, after applying a resist on the silicon nitride film 22, a resist pattern (not shown) having a shape corresponding to the active region 5 is formed while patterning the resist by a lithography technique. Then, using this resist pattern as a mask, the silicon nitride film 22 and the silicon oxide film 21 are patterned by anisotropic dry etching, and then the resist pattern is removed. As a result, the silicon oxide film 21 and the silicon nitride film 22 patterned into a shape corresponding to the active region 5 remain on the semiconductor substrate 2. In this example, a silicon oxide film 21 having a thickness of about 10 nm and a silicon nitride film 22 having a thickness of about 100 nm are formed.

  Next, as shown in FIGS. 5A and 5B, the surface layer of the semiconductor substrate 2 is patterned by anisotropic dry etching using the patterned silicon nitride film 22 as a mask. As a result, the first groove 23 is formed in the surface layer of the semiconductor substrate 2. In this example, the first groove 23 having a depth of about 100 nm is formed. As a result, silicon pillars having a shape corresponding to the active region 5 were formed between the first groove portions 23 with a width W of about 80 nm. 5A is a plan view showing the surface of the semiconductor substrate 2, and FIG. 5B is a cross-sectional view taken along line A-A 'in FIG. 5A.

  Next, as shown in FIG. 6, a silicon oxide film (second oxide film) 24 is formed on the semiconductor substrate 2 by, for example, a CVD method, and then etched back by anisotropic dry etching. A first sidewall 14 in which the silicon oxide film 24 remains is formed on the side surface of the groove 23. In this example, a silicon oxide film 24 having a thickness of about 10 nm is formed. FIG. 6 is a cross-sectional view taken along line A-A ′ in FIG.

  Next, as shown in FIG. 7, the second groove 25 is formed in the semiconductor substrate 2 while patterning the semiconductor substrate 2 by anisotropic dry etching. In this example, the second groove portion 25 having a depth of about 50 nm is formed. FIG. 7 is a cross-sectional view taken along line A-A ′ in FIG.

  Next, as shown in FIG. 8, a silicon oxide film (third oxide film) 26 is formed on the semiconductor substrate 2 by, for example, a CVD method, and then etched back by anisotropic dry etching. A second sidewall 15 in which the silicon oxide film 26 remains is formed on the side surface of the groove portion 25. In this example, a silicon oxide film 26 having a thickness of about 10 nm is formed. FIG. 8 is a cross-sectional view taken along line A-A ′ in FIG.

  Next, as shown in FIG. 9, while patterning the semiconductor substrate 2 by isotropic etching, a recess 11 having a width wider than that of the second groove 25 is formed below the second groove 25. Specifically, the isotropic etching can be performed, for example, by wet etching using an ammonia perwater solution that is a mixed solution of ammonia water, hydrogen peroxide solution, and pure water. FIG. 9 is a cross-sectional view taken along line A-A ′ in FIG.

  In this example, wet etching was performed for 25 minutes using an ammonia perwater solution with a reaction rate of 2 nm / min. As a result, a recess 11 having a thickness of about 50 nm was formed below the second groove 25 in the depth direction and the width direction. In addition, the recesses 11 are formed inwardly from the mutually opposing side surfaces of the silicon pillar, whereby a narrow portion 12 having a shape confined between the recesses 11 is formed with a width of about 40 nm.

  In addition to the wet etching, isotropic etching can be performed by dry etching. Specifically, when performing dry etching, for example, chlorine gas and sulfur hexafluoride gas are used. A mixed gas containing chlorine gas, a mixed gas containing chlorine gas and hydrogen bromide, or the like can be used.

  Next, as shown in FIG. 10, the buried insulating film 3 is buried in the first and second groove portions 23 and 25 and the recess 11 while the buried insulating film 3 is formed on the semiconductor substrate 2. . In this example, an SOD (Spin On Dielectric) film is used as the buried insulating film 3, but a silicon oxide film formed by a CVD method may be used. The distance from the upper surface of the buried insulating film 3 to the upper surface of the silicon pillar is about 30 nm. FIG. 10 is a cross-sectional view taken along line A-A ′ in FIG.

  Next, as shown in FIG. 11, the surface on which the buried insulating film 3 is formed is polished by chemical mechanical polishing (CMP), and planarized until the surface of the silicon nitride film 22 is exposed. Do. As a result, the element isolation region 4 in which the buried insulating film 3 is embedded in the recess 2a and the plurality of active regions 5 insulated and isolated by the element isolation region 4 are formed. FIG. 11 is a cross-sectional view taken along line A-A ′ in FIG.

  Next, as shown in FIG. 12, the silicon nitride film 22 on the active region 5 is removed with hot phosphoric acid solution, and the silicon oxide film 21 is removed with hydrofluoric acid solution, and then the surface (upper surface) of the exposed active region 5 is removed. ) Is oxidized to form a silicon oxide film (fourth oxide film) 27. In this example, the silicon oxide film 27 having a thickness of 10 nm is formed by thermal oxidation. FIG. 12 is a cross-sectional view taken along line A-A ′ in FIG.

  Next, as shown in FIGS. 13A to 13D, after a resist is applied thereon, an opening 28a is formed in a portion corresponding to the groove 10 while patterning the resist by a lithography technique. A resist pattern 28 is formed. In this example, a resist pattern 28 having a thickness of about 350 nm was formed. The width of the opening 28a of the resist pattern 28 is 50 nm. FIG. 13A is a plan view showing the surface of the semiconductor substrate 2 in this step, and FIG. 13B is a cross-sectional view taken along line AA ′ in FIG. 13 (c) is a cross-sectional view taken along line BB ′ in FIG. 13 (a), and FIG. 13 (d) is a cross-sectional view taken along line DD ′ in FIG. 13 (a).

  Next, as shown in FIGS. 14A to 14C, using this resist pattern 28 as a mask, the active region 5 exposed from the opening 28a is patterned by anisotropic dry etching, before the recess 11 is formed. The groove portion 10 having a depth up to is formed. As a result, the active region 5 includes a bottom channel region 13a that is wider than the narrow portion 12 between the bottom surface of the groove portion 10 and the narrow portion 12, and upward from both ends of the bottom channel region 13a. A channel region 13 having a pair of rising side channel regions 13b is formed.

  In this example, etching is performed at a depth of 120 ± 10 nm from the upper surface of the active region 5, the thickness th of the thinnest portion of the bottom channel region 13a is 30 nm ± 10 nm, and the thickness tw of the side channel region 13b is Etching was performed to 20 nm. 14A is a cross-sectional view taken along line AA ′ in FIG. 13A in this step, and FIG. 14B is line BB ′ in FIG. 13A. FIG. 14C shows a cross-sectional view taken along line CC ′ in FIG.

  Next, as shown in FIG. 15, after removing the resist pattern 28, the silicon oxide film 27 is removed with a hydrofluoric acid solution, and then the exposed surface (upper surface) of the active region 5 is oxidized to form a gate insulating film ( A silicon oxide film 6 is formed. The gate insulating film 6 is not limited to a silicon oxide film formed by thermal oxidation, and may be a high temperature silicon oxide film (HTO) formed by a CVD method, a high dielectric constant film, or the like. In this example, the gate insulating film 6 having a thickness of 5 nm was formed by thermal oxidation.

  Then, a silicon film 29 to be the gate electrode 7 is sequentially laminated thereon by, for example, an LP-CVD method, a barrier metal film 30 and a tungsten film 31 by, for example, a plasma sputtering method, and a part of the silicon film 29 is formed in the groove 10. Embedded. Further, a silicon nitride film (second nitride film) 32 is formed thereon by, for example, LP-CVD. In this example, a silicon film 29 having a thickness of 80 nm, a barrier metal film 30 having a thickness of 10 nm, a tungsten film 31 having a thickness of 50 nm are formed, and a silicon nitride film 32 having a thickness of 200 nm is formed. FIG. 15 is a cross-sectional view taken along line A-A ′ in FIG.

  Next, as shown in FIGS. 16A to 16C, a resist pattern having a shape corresponding to the gate electrode 7 is formed on the silicon nitride film 32, and the silicon nitride film 32, After the tungsten film 31, the barrier metal film 30, and the silicon film 29 are patterned by anisotropic dry etching, the resist pattern is removed. Thereby, the gate electrode 7 is formed.

  Thereafter, impurity ions are implanted into the active regions 5 on both sides of the gate electrode 7 to form the source region 8 and the drain region 9. In this example, a drain region 9 is formed by implanting P or As ions or both ions in the center of the active region 5 across the gate electrode 7, and the gate electrode 7 in the active region 5 is sandwiched. The source region 8 was formed by implanting P or As ions or both ions at both ends. 16A is a cross-sectional view taken along line AA ′ in FIG. 13A at the time of this step, and FIG. 16B is a line segment in FIG. 13A at the time of this step. FIG. 16C is a cross-sectional view taken along the line BB ′ and FIG. 16C is a cross-sectional view taken along the line CC ′ in FIG.

  Through the above-described steps, the trench gate transistor 1 can be manufactured.

  As described above, in the present invention, after forming the trench 2a (first and second trenches 23 and 25) in which the buried insulating film 3 is buried in the semiconductor substrate 2, the isotropic etching is performed below the trench 2a. The step of forming the narrow portion 12 between the opposing concave portions 11 on both side surfaces of the active region 5 by forming the concave portion 11 wider than the groove portion 2a, and the groove portion 10 on the upper surface of the active region 5 By forming the channel region 13 wider than the narrow portion 12 at least between the bottom surface of the groove portion 10 and the narrow portion 12, It is possible to manufacture the trench gate transistor 1 in which the active region 5 has an SOI structure and good subthreshold characteristics can be obtained.

(Second Embodiment)
Next, a trench gate transistor 50 shown in FIGS. 17A to 17C will be described as a second embodiment.
17A is a cross-sectional view taken along line AA ′ shown in FIG. 1, FIG. 17B is a cross-sectional view taken along line BB ′ shown in FIG. 1, and FIG. ) Corresponds to the cross-sectional view taken along line CC ′ shown in FIG.
Moreover, in the following description, about the site | part equivalent to the said trench gate transistor 1, description is abbreviate | omitted and the same code | symbol shall be attached | subjected in drawing.

  In this trench gate transistor 50, the first sidewall 14 covering the side surface of the gate electrode 7 embedded in the trench 10 is shortened, and a pair of side channel regions 13b rising upward from both ends of the bottom channel region 13a is formed. The structure is substantially the same as that of the trench gate transistor 1 except that it is formed long.

  In the trench gate transistor 50 having the above-described structure, a threshold voltage is applied to the gate electrode 7 in the same manner as the trench gate transistor 1 shown in FIG. An inversion layer region T is formed from the channel region 13a to the side channel region 13b. Thereby, a high conductance can be achieved between the source region 8 and the drain region 9.

  On the other hand, in this trench gate transistor 50, a fully depleted region S is formed from the bottom channel region 13a to the side channel region 13b on the semiconductor substrate 2 side of the channel region 13 during operation. As a result, the active region 5 has an SOI structure, and good subthreshold characteristics can be obtained. That is, it has characteristics of a small threshold voltage and a high driving capability.

  When the trench gate transistor 50 is manufactured, after the steps shown in FIGS. 4A and 4B, the surface layer of the semiconductor substrate 2 is formed using the patterned silicon nitride film 22 as a mask as shown in FIG. Is patterned by anisotropic dry etching. At this time, the depth of the first groove 23 formed in the surface layer of the semiconductor substrate 2 is made smaller than in the case of the step shown in FIG. In this example, the first groove 23 having a depth of about 30 nm was formed. As a result, the bottom surface of the first groove 23 is positioned slightly below the silicon oxide film 21. FIG. 18 corresponds to a cross-sectional view taken along line A-A ′ in FIG.

  Next, as shown in FIG. 19, a silicon oxide film (second oxide film) 24 is formed on the semiconductor substrate 2 by, for example, a CVD method, and then etched back by anisotropic dry etching. A first sidewall 14 in which the silicon oxide film 24 remains is formed on the side surface of the groove 23. In this example, a silicon oxide film 24 having a thickness of about 10 nm is formed. FIG. 19 corresponds to a cross-sectional view taken along line A-A ′ in FIG.

  Next, as shown in FIG. 20, the second groove 25 is formed in the semiconductor substrate 2 while patterning the semiconductor substrate 2 by anisotropic dry etching. Note that FIG. 20 corresponds to a cross-sectional view taken along line A-A ′ in FIG.

  Next, as shown in FIG. 21, a silicon oxide film (third oxide film) 26 is formed on the semiconductor substrate 2 by, for example, the CVD method, and then etched back by anisotropic dry etching to form the second A second sidewall 15 in which the silicon oxide film 26 remains is formed on the side surface of the groove portion 25. In this example, a silicon oxide film 26 having a thickness of about 10 nm is formed. FIG. 21 corresponds to a cross-sectional view taken along line A-A ′ in FIG.

  As for the subsequent steps, the trench gate transistor 50 can be manufactured by performing the same steps as those for manufacturing the trench gate transistor 1, that is, the steps shown in FIGS. .

  In the trench gate transistor 50 manufactured through the above processes, the side channel region 13b of the trench gate transistor 1 has a height of about 50 nm, while the side portion has a height of about 120 nm. The channel region 13b can be formed, and as a result, the driving capability can be further improved.

(Third embodiment)
Next, a trench gate transistor 60 shown in FIG. 22 and FIGS. 23A to 23C will be described as a third embodiment.
23A is a cross-sectional view taken along line AA ′ shown in FIG. 22, FIG. 23B is a cross-sectional view taken along line BB ′ shown in FIG. 22, and FIG. ) Corresponds to a cross-sectional view taken along line CC ′ shown in FIG.
Moreover, in the following description, about the site | part equivalent to the said trench gate transistor 1, description is abbreviate | omitted and the same code | symbol shall be attached | subjected in drawing.

  The trench gate transistor 60 is the same as the trench gate transistor except that the first side wall 14 covering the side surface of the gate electrode 7 embedded in the trench 10 is omitted, and the side channel region 13b is omitted and only the bottom channel region 13a is used. The configuration is almost the same as that of the gate transistor 1.

  In the trench gate transistor 60 having the structure as described above, the gate electrode of the channel region 13 (bottom channel region 13a) is applied by applying a threshold voltage to the gate electrode 7, similarly to the trench gate transistor 1 shown in FIG. The inversion layer region T is formed on the surface on the side. Thereby, a high conductance can be achieved between the source region 8 and the drain region 9.

  On the other hand, in the trench gate transistor 60, a fully depleted region S is formed on the semiconductor substrate 2 side of the channel region 13 (bottom channel region 13a) during operation. As a result, the active region 5 has an SOI structure, and good subthreshold characteristics can be obtained. That is, it has characteristics of a small threshold voltage and a high driving capability.

  When manufacturing the trench gate transistor 60, after the steps shown in FIGS. 4A and 4B, as shown in FIG. 24, the surface layer of the semiconductor substrate 2 is formed using the patterned silicon nitride film 22 as a mask. Is patterned by anisotropic dry etching. At this time, the depth of the first groove 23 formed in the surface layer of the semiconductor substrate 2 is made deeper than in the case of the step shown in FIG. In this example, the first groove 23 having a depth of about 150 nm is formed. As a result, the bottom surface of the first groove portion 23 is substantially at the same position as the bottom surface of the second groove portion 25. FIG. 24 corresponds to a cross-sectional view taken along line A-A ′ in FIG.

  Next, as shown in FIG. 25, a silicon oxide film (third oxide film) 26 is formed on the semiconductor substrate 2 by, for example, a CVD method, and then etched back by anisotropic dry etching. A second sidewall 15 in which the silicon oxide film 26 remains is formed on the side surface of the groove 23. In this example, a silicon oxide film 26 having a thickness of about 10 nm is formed. Note that FIG. 25 corresponds to a cross-sectional view taken along line A-A ′ in FIG.

  Next, as shown in FIG. 26, while patterning the semiconductor substrate 2 by isotropic etching, a recess 11 having a width wider than that of the first groove 23 is formed below the first groove 23. Specifically, the isotropic etching can be performed, for example, by wet etching using an ammonia perwater solution that is a mixed solution of ammonia water, hydrogen peroxide solution, and pure water. FIG. 26 corresponds to a cross-sectional view taken along line A-A ′ in FIG.

  In this example, wet etching was performed for 17 minutes using an ammonia perwater solution with a reaction rate of 2 nm / min. As a result, a recess 11 having a thickness of about 35 nm was formed below the first groove 23 in the depth direction and the width direction. In addition, the recesses 11 are formed inwardly from the mutually opposing side surfaces of the silicon pillar, whereby the narrow portion 12 having a shape confined between the recesses 11 is formed with a width of about 30 nm.

  Next, as shown in FIG. 27, the buried insulating film 3 is buried in the first groove 23 and the recess 11 while the buried insulating film 3 is formed on the semiconductor substrate 2. FIG. 27 corresponds to a cross-sectional view taken along line A-A ′ in FIG.

  Next, as shown in FIG. 28, the surface on which the buried insulating film 3 is formed is polished by chemical mechanical polishing (CMP) and planarized until the surface of the silicon nitride film 22 is exposed. Do. Then, the silicon nitride film 22 on the active region 5 is removed with a hot phosphoric acid solution, and the silicon oxide film 21 is removed with a hydrofluoric acid solution, and then the exposed surface (upper surface) of the active region 5 is oxidized to form silicon oxide. A film (fourth oxide film) 27 is formed. FIG. 28 corresponds to a cross-sectional view taken along line A-A ′ in FIG.

  Next, as shown in FIGS. 29A to 29C, after a resist is applied thereon, an opening 28a is formed in a portion corresponding to the groove 10 while patterning the resist by a lithography technique. A resist pattern 28 is formed. Then, using the resist pattern 28 as a mask, the active region 5 exposed from the opening 28a is patterned by anisotropic dry etching, and the groove 10 having a depth reaching the front of the recess 11 is formed. As a result, a bottom channel region 13 a (channel region 13) that is wider than the narrow portion 12 is formed in the active region 5 between the bottom surface of the groove 10 and the narrow portion 12.

  In this example, the etching is performed at a depth of about 125 nm, which is about 5 nm deeper than that of the trench gate transistor 1 from the upper surface of the active region 5, reflecting that the etching amount when forming the recess 11 is small. Etching was performed so that the thickness th of the thinnest portion of the bottom channel region 13a was 30 nm ± 10 nm. FIG. 29A is a cross-sectional view taken along line AA ′ in FIG. 13A at the time of this step, and FIG. 29B is line BB ′ in FIG. 13A. FIG. 29C corresponds to the cross-sectional view taken along line CC ′ in FIG.

  As for the subsequent steps, the trench gate transistor 60 can be manufactured through the same steps as those for manufacturing the trench gate transistor 1, that is, the steps shown in FIGS. .

  Since the trench gate transistor 60 manufactured through the above steps has a structure in which only the bottom channel region 13a is formed, a high driving capability can be obtained in the bottom channel region 13a.

  The present invention is not limited to the case where the trench gate transistors 1, 50, 60 are applied to DRAM memory cells, but can be widely applied to semiconductor devices including trench gate transistors. The present invention can also be applied to general semiconductor devices such as logic products that do not have the.

  DESCRIPTION OF SYMBOLS 1 ... Trench gate transistor (1st Embodiment) 2 ... Semiconductor substrate 2a ... Groove part 3 ... Embedded insulating film 4 ... Element isolation region 5 ... Active region 6 ... Gate insulating film 7 ... Gate electrode 7a ... Word line 7b ... Dummy word Line 8 ... Source region 9 ... Drain region 10 ... Groove 11 ... Recess 12 ... Narrow 13 ... Channel region 13a ... Bottom channel region 13b ... Side channel region 14 ... First sidewall 15 ... Second sidewall 21 ... Silicon oxide film (first oxide film) 22 ... Silicon nitride film 23 ... First groove 24 ... Silicon oxide film (second oxide film) 25 ... Second groove 26 ... Silicon oxide film (third oxide film) 27) Silicon oxide film (fourth oxide film) 28 ... Resist pattern 28a ... Opening 29 ... Silicon film 30 ... Barrier metal 31 ... tungsten film 32 ... silicon nitride film (the second nitride film) 50 ... trench gate transistor (second embodiment) 60 ... trench gate transistor (Third Embodiment)

Claims (4)

An active region isolated by a buried insulating film buried in a semiconductor substrate;
A gate electrode formed so as to straddle the active region through a gate insulating film formed on the active region;
A source region and a drain region formed by ion implantation into active regions on both sides of the gate electrode;
A trench-type channel structure in which a groove is provided in the active region, and a part of the gate electrode is embedded inside the groove via the gate insulating film;
Recesses are provided on both side surfaces of the active region so as to face each other, and a narrow part is formed between the recesses, so that at least the bottom part of the groove part and the narrow part are more than the narrow part. A semiconductor device characterized in that a wide channel region is formed.   The semiconductor device according to claim 1, wherein the channel region is formed from a bottom surface of the groove portion to both side surfaces of the groove portion. An active region isolated by a buried insulating film buried in a semiconductor substrate;
A gate electrode formed so as to straddle the active region through a gate insulating film formed on the active region;
A method of manufacturing a semiconductor device comprising a source region and a drain region formed by ion implantation into active regions on both sides sandwiching the gate electrode,
After forming a groove portion in which the embedded insulating film is embedded in the semiconductor substrate, a recess having a width wider than the groove portion is formed below the groove portion by isotropic etching, thereby opposing both sides of the active region. Forming a narrow portion between the recesses;
By forming a groove on the upper surface of the active region at a depth reaching the front of the recess, a channel region that is wider than the narrow portion is formed at least between the bottom surface of the groove and the narrow portion. A method for manufacturing a semiconductor device, comprising: a step.   4. The method of manufacturing a semiconductor device according to claim 3, wherein the channel region is formed from the bottom surface of the groove portion to both side surfaces of the groove portion.

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