JP2011029358A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve a MOS transistor with higher withstand voltage, lower on-resistance, improved HCI resistance, and reduced design rule. <P>SOLUTION: The MOS transistor has a drain including: an N-type low-concentration drain 7, one end of which is disposed, in a channel length direction, in a P-type low-concentration well 3 and the other end of which is disposed in a P-type well 5; and an N-type high-concentration drain 9 which is disposed in the low-concentration drain 7 above the low-concentration well 3 so as to be apart from the ends of the low-concentration drain 7. A source includes: an N-type high-concentration source 11, one end of which is disposed, in the channel length direction, in the low-concentration well 3 so as to be apart from the low-concentration drain 7 and the other end of which is disposed in the well 5; and an N-type low-concentration source 13 which is adjacent to the high-concentration source 11 in the low-concentration well 3 and is disposed apart from the low-concentration drain 7. A gate electrode 19 is disposed above the low-concentration well 3 and the low-concentration drain 7 and between the high-concentration drain 9 and the low-concentration source 13 so as to be apart from the high-concentration drain 9. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device including a high voltage MOS transistor.

  2. Description of the Related Art In recent years, semiconductor devices have been increasingly miniaturized and lowered in voltage for gate electrodes of MOS transistors in order to improve digital calculation speed. On the other hand, as represented by power supply products, there is a trend toward higher breakdown voltage of MOS transistors.

  In order to increase the breakdown voltage of the drain structure of a MOS transistor, a structure in which a low-concentration impurity diffusion layer is disposed around a high-concentration drain is disclosed (for example, see Patent Document 1). A conventional high voltage MOS transistor is formed in one well having a uniform concentration.

  In a conventional high voltage MOS transistor in which a low-concentration impurity diffusion layer is arranged around a high-concentration drain in order to increase the breakdown voltage of the drain structure, it is formed in one well having a uniform concentration. There was a problem of HCI (Hot Carrier Injection) due to the large electric field strength near the drain under the electrode. Moreover, since the junction breakdown voltage near the bottom of the drain is lowered, there is a problem in that it is disadvantageous for increasing the breakdown voltage.

  In order to solve such a problem, it is conceivable to reduce the impurity concentration of the well in which the high voltage MOS transistor is formed. However, if the impurity concentration of the well is lowered, when a plurality of high breakdown voltage MOS transistors are arranged side by side, it is necessary to make a large space between the MOS transistors and the MOS transistors in order to maintain the breakdown voltage between the wells between the adjacent MOS transistors. There was a problem that it was disadvantageous in terms of design rules. Further, when a well having a low impurity concentration is used, the substrate resistance increases in the MOS transistor. For example, in the case of a large driver transistor or the like, if impact ionization occurs, the substrate potential tends to float, snapping back immediately, and the on-breakdown voltage deteriorates.

  Accordingly, an object of the present invention is to provide a semiconductor device capable of realizing a high breakdown voltage of a MOS transistor, a reduction in on-resistance, an improvement in HCI resistance, and a reduction in design rule.

A semiconductor device according to the present invention includes a P-type low-concentration well formed on the surface of a semiconductor substrate with a relatively low concentration of P-type impurity, and the P-type low-concentration well adjacent to the P-type low-concentration well. A P-type well surrounding the periphery and formed on the surface of the semiconductor substrate with a P-type impurity concentration higher than that of the P-type low-concentration well. The high voltage MOS transistor is formed across the P-type low concentration well and the P-type well.
Here, the semiconductor substrate may be either P-type or N-type. The term “semiconductor substrate” includes an epitaxially grown layer.

  The high breakdown voltage MOS transistor is formed on the surface of the semiconductor substrate shallower than the P-type low concentration well and the P-type well, and has one end disposed in the P-type low concentration well in the channel length direction and the other end An N-type low-concentration drain having a relatively low concentration of N-type impurity disposed in the P-type well, and an N-type impurity concentration higher than the N-type low-concentration drain and shallower than the N-type low-concentration drain An N-type high-concentration drain formed on the surface of the semiconductor substrate and spaced from an end of the N-type low-concentration drain in the N-type low-concentration drain on the P-type low-concentration well; An end opposite to the P-type low-concentration well end formed on the surface of the semiconductor substrate shallower than the concentration well and the P-type well and in which the N-type low-concentration drain is arranged in the channel length direction Further, an N-type source having one end disposed in the P-type low-concentration well with an interval from the N-type low-concentration drain and the other end disposed in the P-type well, The N-type source is formed on the semiconductor substrate between the N-type sources via the gate insulating film, and the end of the drain side in the channel length direction as viewed from above is spaced from the N-type high-concentration drain. And a gate electrode disposed on the low concentration drain.

  In the semiconductor device of the present invention, an example in which the N-type source has a single source structure can be given. That is, an example in which the N-type source is formed only by the N-type high-concentration source formed simultaneously with the N-type high-concentration drain can be given.

  The N-type source may have an LDD (Lightly Doped Drain) structure. That is, the N-type source is an N-type high-concentration source formed at the same time as the N-type high-concentration drain, and is shallower than the N-type high-concentration source with an N-type impurity concentration lower than that of the N-type low-concentration source. It is formed on the surface of the semiconductor substrate, and is formed by an N-type low-concentration source disposed between the source-side end of the gate electrode and the N-type high-concentration source in the channel length direction when viewed from above. It may be.

In the semiconductor device of the present invention, the source may have the same structure as the drain.
That is, the N-type source is formed on the surface of the semiconductor substrate shallower than the P-type low-concentration well and the P-type well, one end is disposed in the P-type low-concentration well in the channel length direction, and the other end is An N-type low concentration source having a relatively low concentration of N-type impurity disposed in the P-type well, and an N-type impurity concentration higher than that of the N-type low concentration source and shallower than the N-type low concentration source. An N-type high-concentration source formed on the surface of the semiconductor substrate and disposed in the N-type low-concentration source on the P-type low-concentration well and spaced from an end of the N-type low-concentration source; The end of the gate electrode on the source side may be disposed on the N-type low concentration source with an interval from the N-type high concentration source as viewed from above.

  In the semiconductor device of the present invention, the P type and the N type may be opposite conductivity types. That is, the high voltage MOS transistor may be a P-channel MOS transistor in which the P-type and N-type are opposite conductivity types. Further, the P channel MOS transistor and the N channel MOS transistor may be mixedly mounted on the same semiconductor substrate.

In the semiconductor device of the present invention, a P-type low concentration well and a P-type well adjacent to the P-type low concentration well and surrounding the periphery of the P-type low concentration well and having a higher P-type impurity concentration than the P-type low concentration well. A high voltage MOS transistor was formed across the gate.
In the high voltage MOS transistor, the N type high concentration drain is covered with the N type low concentration drain in order to give the drain a high junction breakdown voltage. Furthermore, the breakdown voltage of the drain can be improved by disposing the N-type high-concentration drain on the P-type low-concentration well.

  Also, in a region generally called drift from the channel to the N-type high-concentration drain, a certain distance is arranged to ensure a withstand voltage, but on the contrary, it becomes a parasitic high-resistance part, so that the resistance value should be lowered as much as possible. . To solve this problem, since the drift region is arranged on the P-type low concentration well in the semiconductor device according to the present invention, the N-type low concentration drain is formed and returned to the P-type low concentration well having a low P-type impurity concentration. Therefore, the drift portion can be reduced in resistance and the on-resistance can be reduced as compared with the case where the drift portion is formed in a high-concentration P-type well.

Furthermore, the concentration gradient in the vicinity of the drain immediately below the gate electrode can be lowered by forming the channel with a P-type low concentration well and disposing the end of the N-type low concentration drain under the gate electrode. Thereby, improvement of HCI tolerance can be aimed at.
Further, since the periphery of the MOS transistor is surrounded by a P-type well, when a plurality of high voltage MOS transistors are arranged side by side, the MOS transistor is formed only in one P-type low concentration well having a uniform concentration. In comparison, the space between wells can be reduced between adjacent MOS transistors, and the design rule can be reduced.

In the semiconductor device of the present invention, if the N-type source has a single source structure or an LDD structure, the source resistance can be reduced, so that the on-resistance can be reduced.
Further, if the source has the same structure as the drain, it can cope with a case where the source requires a high breakdown voltage.

It is a schematic sectional view for explaining an example. It is a schematic plan view of the same embodiment. It is a figure showing the measurement result which verified drive capability with the drain voltage-drain current of the MOS transistor of the Example. It is a figure showing the measurement result which verified the drive capability with the drain voltage-drain current of the MOS transistor of the comparative example. It is process sectional drawing for demonstrating the first process of an example of the manufacturing process of the MOS transistor of the Example. It is process sectional drawing for demonstrating the continuation of the manufacturing process. It is process sectional drawing for demonstrating the further continuation of the manufacturing process. It is process sectional drawing for demonstrating the further continuation of the manufacturing process. It is process sectional drawing for demonstrating the further continuation of the manufacturing process. It is process sectional drawing for demonstrating the further continuation of the manufacturing process. It is process sectional drawing for demonstrating the further continuation of the manufacturing process. It is a schematic sectional drawing for demonstrating another Example. It is a schematic plan view of the same embodiment. Furthermore, it is a schematic sectional drawing for demonstrating another Example. It is a schematic plan view of the same embodiment.

  FIG. 1 is a schematic sectional view for explaining one embodiment. FIG. 2 is a schematic plan view of the embodiment. FIG. 1 corresponds to a cross section taken along line AA in FIG.

  On the surface of the P-type semiconductor substrate 1 (Psub), a P-type low-concentration well 3 (LPW), a P-type well 5 (PW), an N-type low-concentration drain 7 (NLDD), an N-type high-concentration drain 9 (N +), An N-type high concentration source 11 (N +) and an N-type low concentration source 13 are formed.

The P-type low concentration well 3 forms a channel of an N-channel high voltage MOS transistor.
The P-type well 5 is formed adjacent to the P-type low-concentration well 3 formed with a relatively low P-type impurity concentration and surrounding the P-type low-concentration well. The P-type well 5 has a higher P-type impurity concentration than the P-type low concentration well 3.

  The N-type low concentration drain 7 is formed with a relatively low N-type impurity concentration. The N-type low concentration drain 7 is formed shallower than the P-type low concentration well 3 and the P-type well 5. One end of the N-type low concentration drain 7 is disposed in the P-type low concentration well 3 in the channel length direction of the N-channel high voltage MOS transistor. The other end of the N-type low concentration drain 7 is disposed in the P-type well 3.

The N-type high-concentration drain 9 is disposed in the N-type low-concentration drain 7 on the P-type low-concentration well 3 with a distance from the end of the N-type low-concentration drain 7. The N-type high-concentration drain 9 is formed with a higher N-type impurity concentration than the N-type low-concentration drain 7 and shallower than the N-type low-concentration drain 7.
The N-type low-concentration drain 7 and the N-type high-concentration drain 9 form a double diffusion structure drain of an N-channel high breakdown voltage MOS transistor.

  The N-type high-concentration source 11 has a P-type low-concentration well 3 and a P-type on the end opposite to the end of the P-type low-concentration well 3 where the N-type low-concentration drain 7 is arranged in the channel length direction. It is formed shallower than the well 5. One end of the N-type high-concentration source 11 is disposed in the P-type low-concentration well 3 at a distance from the N-type low-concentration drain 7 in the channel length direction. The other end of the N-type high concentration source 11 is disposed in the P-type well 3.

The N type low concentration source 13 is formed on the surface of the P type low concentration well 3 between the N type low concentration drain 7 and the N type high concentration source 11. The N-type low concentration source 13 is formed shallower than the N-type low concentration drain 7. In the channel length direction, one end of the N-type low-concentration source 13 is spaced from the N-type low-concentration drain 7, and the other end is adjacent to the N-type high-concentration source 11.
The N-type high-concentration source 11 and the N-type low-concentration source 13 constitute an LDD structure source of an N-channel high voltage MOS transistor.

A LOCOS (local oxidation of silicon) oxide film 15 is also formed on the surface of the semiconductor substrate 1.
In the channel length direction, one end of the opening of the LOCOS oxide film 15 is located at the end of the N-type high concentration source 11 and the other end is disposed on the N-type low concentration drain 7. The N-type high-concentration drain 9 is disposed at a distance from the LOCOS oxide film 15.

In the channel width direction of the MOS transistor, the opening of the LOCOS oxide film 15 is arranged inside the layout of the P-type low concentration well 3 and the N-type low concentration drain 7.
In the channel width direction, the end portion of the N-type low concentration drain 7 is disposed outside the end portion of the P-type low concentration well 3. However, the end portion of the N-type low concentration drain 7 in the channel width direction may be disposed at the same position as the end portion of the P-type low concentration well 3 or more than the end portion of the P-type low concentration well 3. You may arrange | position inside.

  A gate electrode 19 is formed on the semiconductor substrate 1 via a gate oxide film (gate insulating film) 17 inside the opening of the LOCOS oxide film 15. The gate electrode 19 is disposed on the P-type low concentration well 3 and the N-type low concentration drain 7 between the N-type high concentration drain 9 and the N-type high concentration source 11. When viewed from above, the end of the gate electrode 19 on the drain side in the channel length direction is spaced from the N-type high concentration drain 9. The N-type low-concentration source 13 is formed using the end portion on the source side of the gate electrode 19 as a mask. The gate electrode 19 is formed extending on the LOCOS oxide film 15 in the channel width direction. Sidewalls 21 are formed on the side surfaces of the gate electrode 19.

Inside the opening of the LOCOS oxide film 15, the surface side of the P-type low concentration well 3 located under the gate electrode 13 becomes a channel of the MOS transistor.
Contact plugs 23 are respectively formed on the N-type high concentration drain 7 and the N-type high concentration source 11.

  In this embodiment, in the N-channel high breakdown voltage MOS transistor, the P-type low concentration well 3 having a relatively low concentration is disposed in the vicinity of the channel and the source and drain channels. Improvement of HCI tolerance and reduction of design rules can be realized.

Specifically, since the drain structure in which the N-type high-concentration drain 9 is covered with the N-type low-concentration drain 7 is provided, the drain can have a high junction breakdown voltage.
Furthermore, the breakdown voltage of the drain can be improved by disposing the N-type high concentration drain 9 on the P-type low concentration well 3. Regarding the bottom breakdown voltage of the N-type high-concentration drain 9, when the N-type high-concentration drain 9 is disposed on the P-type well 3 via the N-type low-concentration drain 7, it is only 25V. By arranging the drain 9 on the P-type low-concentration well 3, the breakdown voltage can be improved to around 36V. Here, in order to arrange the N-type high-concentration drain 9 on the P-type low-concentration well 3, the boundary between the P-type low-concentration well 3 and the P-type well 5 below the drain in the channel length direction is the gate electrode. What is necessary is just to arrange | position between the edge part of the N type high concentration drain 9 and the edge part of the N type low concentration drain 7 on the opposite side to 19. FIG.

  Further, in this embodiment, the N-type low concentration drain 7 portion (drift region) between the channel and the N-type high concentration drain 9 is disposed on the P-type low concentration well 3. Since the N-type low concentration drain 7 is formed by striking the P-type low concentration well 3 having a low P-type impurity concentration, the drift region has a lower resistance than the case where the drift region is formed by striking the high-concentration P-type well 3. The on-resistance can be lowered.

FIG. 3 and FIG. 4 are diagrams showing the results of comparing the drive capability with drain voltage-drain current for the MOS transistor of this example (Example) and the MOS transistor formed only in the P-type well (Comparative Example). is there. FIG. 3 shows the measurement results of the example, and FIG. 4 shows the measurement results of the comparative example. The vertical axis represents drain current (unit: A (ampere)), and the horizontal axis represents drain voltage (unit: V (volt)).
3 and 4 clearly show that it is more advantageous to arrange the P-type low concentration well 3.

  Further, in this embodiment, the channel is formed by the P-type low concentration well 3 and the end portion of the N-type low concentration drain 7 is disposed under the gate electrode 19, so that the concentration gradient in the vicinity of the drain immediately below the gate electrode 19 is obtained. Can be lowered. Thereby, improvement of HCI tolerance can be aimed at.

  Further, since the periphery of the MOS transistor is surrounded by the P-type well 3, when a plurality of N-channel high breakdown voltage MOS transistors are arranged side by side, the MOS transistor is formed only in one P-type low-concentration well having a uniform concentration. Compared to the case, the space between the wells can be reduced between adjacent MOS transistors, and the design rule can be reduced.

  Furthermore, since the source has an LDD structure including the N-type high-concentration source 11 and the N-type low-concentration source 13, the source resistance can be reduced, so that the on-resistance can be reduced.

  5 to 11 are process cross-sectional views for explaining an example of a manufacturing process of the MOS transistor shown in FIGS. 5 to 11, in addition to the N-channel high voltage MOS transistor (HVNch), a P-channel high voltage MOS transistor (HVPch), a normal N-channel MOS transistor (LVNch), and a normal P-channel MOS formed on the same semiconductor substrate. The manufacturing process of the transistor (LVPch) and the high resistance polysilicon resistance element (HRPoly) is also shown. LVNch and LVPch have LDD structures at the source and drain. The steps described below correspond to the parenthesized numerals in FIGS.

(1) A silicon oxide film 25 having a film thickness of about 250 Å is formed on the surface of a P-type semiconductor substrate 1 having a resistivity of about 20 ohms. A silicon nitride film 27 having a thickness of about 1000 mm is formed on the silicon oxide film 25.

(2) A photoresist 29 for defining the formation position of the N-type well is formed on the silicon nitride film 27 by photolithography. The silicon nitride film 27 is patterned by the ion implantation technique using the photoresist 29 as a mask. Using the photoresist 29 as a mask, phosphorus ions are implanted into the semiconductor substrate 1 under the conditions of an implantation energy of 160 keV and a dose of about 7.7 × 10 ¹² .

(3) The photoresist 29 is removed. Heat treatment is performed at 1000 ° C. for about 80 minutes to form the N-type well 31 at the HVPch formation position and the N-type well 33 at the LVPch formation position. The silicon oxide film 25 is thickened on the surfaces of the N-type well 31 and the N-type well 33 to form a silicon oxide film 35 having a thickness of about 3000 mm.

(4) A photoresist 37 for defining the formation position of the P-type well is formed on the silicon oxide film 25 by photolithography. Boron ions are implanted into the semiconductor substrate 1 by ion implantation under the conditions of an implantation energy of 30 keV and a dose of about 8.4 × 10 ¹² using the silicon oxide film 35 and the photoresist 37 as a mask.

(5) The photoresist 37 is removed. Boron ions are implanted into the semiconductor substrate 1 by ion implantation under the conditions of implantation energy of 30 keV and dose of about 3.6 × 10 ^{12 using the} silicon oxide film 35 as a mask.

(6) Heat treatment is performed at about 1150 ° C. for about 65 minutes to form the P-type low concentration well 3 and the P-type well 5 at the HVNch formation position and the P-type well 39 at the LVNch formation position. The silicon oxide films 25 and 35 on the surface of the semiconductor substrate 1 are removed. Heat treatment is performed at about 920 ° C. to form a silicon oxide film 41 having a thickness of about 300 mm on the surface of the semiconductor substrate 1.

(7) A photoresist 43 for defining the formation position of the HVNch N-type low concentration drain is formed on the silicon oxide film 41 by photolithography. By the ion implantation technique, using the photoresist 43 as a mask, phosphorus ions are implanted into the semiconductor substrate 1 under the conditions of an implantation energy of 60 keV and a dose of about 1.2 × 10 ¹³ .

(8) The photoresist 43 is removed. A silicon nitride film 45 having a thickness of about 1000 mm is formed on the silicon oxide film 41.

(9) A photoresist 47 for defining the formation position of the LOCOS oxide film is formed on the silicon nitride film 45 by photolithography. The silicon nitride film 45 is patterned by the etching technique using the photoresist 37 as a mask.

(10) The photoresist 47 is removed. A photoresist 49 having openings on the P-type wells 5 and 39 is formed on the silicon oxide film 41 and the silicon nitride film 45 by photolithography. By ion implantation, boron ions for field doping are implanted into the semiconductor substrate 1 under conditions of an implantation energy of 15 keV and a dose of about 3.0 × 10 ¹³ using the silicon nitride film 45 and the photoresist 49 as a mask.

(11) The photoresist 49 is removed. A heat treatment is performed at 1000 ° C. for about 150 minutes to thicken the silicon oxide film 41 at a position not covered by the silicon nitride film 45 to form a LOCOS oxide film 15 having a thickness of about 4500 mm. At this time, the phosphorus ions implanted into the HVNch formation planned position in the step (7) are activated, and the N-type low concentration drain 7 is formed.

(12) The silicon nitride film 45 and the silicon oxide film 41 are removed. A pre-gate oxide film 51 having a thickness of about 100 mm is formed by performing heat treatment at 920 ° C. for about 9.5 minutes. A silicon nitride film 53 having a thickness of about 200 mm is formed on the LOCOS oxide film 15 and the pre-gate oxide film 51. On the silicon nitride film 53, an HTO (High Temperature Oxide) film 55 having a thickness of about 1250 mm is formed.

(13) A photoresist 57 having an opening at a position where an HVPch is to be formed is formed on the HTO film 55 by photolithography. Etching technique is used to remove the HTO film 55 at the position where the HVPch is to be formed, using the photoresist 57 as a mask. By ion implantation technique, boron ions for channel doping of HVPch are implanted into the semiconductor substrate 1 under conditions of an implantation energy of 40 keV and a dose of about 2.5 × 10 ¹² using the photoresist 57 as a mask.

(14) The photoresist 57 is removed. A photoresist 59 having an opening at a position where HVNch is to be formed is formed on the silicon nitride film 53 and the HTO film 55 by photolithography. The HTO film 55 at the position where the HVNch is to be formed is removed by etching using the photoresist 59 as a mask. Boron ions for channel doping of HVNch are implanted into the semiconductor substrate 1 by ion implantation under the conditions of an implantation energy of 40 keV and a dose of about 4.0 × 10 ¹¹ using the photoresist 59 as a mask.

(15) The photoresist 59 is removed. Etching technique is used to remove the silicon nitride film 53 at the position where the HVNch and HVPch are to be formed, using the HTO film 55 as a mask. The remaining HTO film 55 and the pre-gate oxide film 51 at the positions where HVNch and HVPch are to be formed are removed. A heat treatment is performed at 850 ° C. for about 55 minutes to form a gate oxide film 17 having a thickness of about 440 mm at a position where HVNch and HVPch are to be formed. The remaining silicon nitride film 53 is removed.

(16) Photoresist 61 for defining the formation position of the P type low concentration drain of HVPch is formed by photolithography. Boron ions are implanted into the semiconductor substrate 1 by an ion implantation technique using the photoresist 61 and the LOCOS oxide film 15 as a mask under conditions of an implantation energy of 35 keV and a dose of about 1.0 × 10 ¹³ .

(17) The photoresist 61 is removed. Photoresist 63 having an opening at the position where the LVPch is to be formed is formed by photolithography. By ion implantation technique, boron ions for channel doping of LVPch are implanted into the semiconductor substrate 1 under conditions of an implantation energy of 15 keV and a dose of about 5.4 × 10 ¹² using the photoresist 63 and the LOCOS oxide film 15 as a mask. To do.

(18) The photoresist 63 is removed. Photoresist 65 having an opening at the position where LVNch is to be formed is formed by photolithography. By ion implantation technique, boron ions for channel doping of LVNch are implanted into the semiconductor substrate 1 under conditions of an implantation energy of 15 keV and a dose of about 3.1 × 10 ¹² using the photoresist 65 and the LOCOS oxide film 15 as a mask. To do.

(19) The photoresist 65 is removed. Photoresist 67 is formed to cover the positions where HVNch and HVPch are to be formed by photolithography. Using the photoresist 67 as a mask, the pre-gate oxide film 51 at the position where the LVNch and LVPch are to be formed is removed.

(20) The photoresist 67 is removed. A heat treatment is performed at 850 ° C. for about 13.5 minutes to form a gate oxide film 69 having a thickness of about 135 mm at a position where LVNch and LVPch are to be formed. At this time, the gate oxide film 17 is thickened. Further, the boron ions implanted in the HVPch formation planned position in the step (16) are activated, and the P-type low concentration drain 71 is formed.

(21) A polysilicon film 73 having a thickness of about 3400 mm is formed on the LOCOS oxide film 15 and the gate oxide films 17 and 69.

(22) Boron ions are implanted into the polysilicon film 73 by an ion implantation technique under conditions of an implantation energy of 15 keV and a dose of about 2.6 × 10 ¹⁴ .

(23) An HTO film 75 having a thickness of about 1500 mm is formed on the polysilicon film 73.

(24) A photoresist 77 is formed on the HTO film 75 by a photolithography technique so as to cover a position where a high resistance polysilicon resistance element (HRPoly) is to be formed. The HTO film 75 is patterned by the etching technique using the photoresist 77 as a mask.

(25) The photoresist 77 is removed. A phosphorus glass is formed on the polysilicon film 73 and the HTO film 75, and phosphorus ions are diffused from the phosphor glass into the polysilicon film 73 to form a low resistance polysilicon film 79. A high-resistance polysilicon film 73 remains under the HTO film 75 disposed at the position where HRPoly is to be formed. The phosphorus glass and the HTO film 75 are removed.

(26) A photoresist 81 for patterning the gate electrode and HRPoly is formed on the polysilicon films 73 and 79 by photolithography. The polysilicon films 73 and 79 are patterned by the etching technique using the photoresist 81 as a mask. As a result, the gate electrode 19 is formed from the low-resistance polysilicon film 79 at the position where HVNch, HVPch, LVNch and HVPch are to be formed, and the resistance element 83 is formed from the high-resistance polysilicon film 73 at the position where HRPoly is to be formed. The

(27) The photoresist 81 is removed. A photoresist 85 having an opening at a position where HVPch and LVPch are to be formed is formed by photolithography. At the position where the HVPch is to be formed, the photoresist 85 covers the peripheral edge of the P-type low-concentration drain 71, the end of the gate electrode 19 and the end of the LOCOS oxide film 15 adjacent thereto. With the ion implantation technique, the photoresist 85, the gate electrode 19 and the LOCOS oxide film 15 are used as a mask, and boron ions for the low concentration drain of the LDD structure are implanted at an energy of 15 keV and a dose of about 2.0 × 10 ^13. Is injected into the semiconductor substrate 1.

(28) The photoresist 85 is removed. Photoresist 87 having an opening at a position where HVNch and LVNch are to be formed is formed by photolithography. At the position where HVNch is to be formed, the photoresist 87 covers the peripheral edge of the N-type low-concentration drain 7, the end of the gate electrode 19 and the end of the LOCOS oxide film 15 adjacent thereto. With the ion implantation technique, using the photoresist 87, the gate electrode 19 and the LOCOS oxide film 15 as a mask, phosphorus ions for lightly doped drains of the LDD structure are implanted at an energy of 30 keV and a dose of about 3.0 × 10 ^13. Implanted into the semiconductor substrate 1.

(29) The photoresist 87 is removed. An HTO film having a thickness of about 1500 mm is formed on the semiconductor substrate 1. The HTO film covers the LOCOS oxide film 15, the gate electrode 19, and the resistance element 83. The ions implanted in the steps (27) and (28) are activated when the HTO film is formed. An N-type low concentration source 13 is formed at a planned HVNch source formation position, and an N-type low concentration diffusion layer 89 is formed at a planned drain formation position. A P-type low-concentration source 91 is formed at the planned source formation position of HVPch, and a P-type low-concentration diffusion layer 93 is formed at the planned drain formation position. An N-type low-concentration source and drain 95 are formed at positions where the LVNch source and drain are to be formed. A P-type low-concentration source and drain 97 is formed at a position where the LVPch source and drain are to be formed.
The HTO film is etched back to form sidewalls 21 on the side surfaces of the gate electrode 19 and sidewalls (not shown) on the side surfaces of the resistance element 83.

(30) A photoresist 99 having an opening at a position where HVNch and LVNch are to be formed is formed by photolithography. The photoresist 99 has the same pattern as the photoresist 87 formed in the step (28). With the ion implantation technique, the photoresist 99, the LOCOS oxide film 15, the gate electrode 19 and the sidewalls 21 are used as a mask, and arsenic ions for high concentration drain and high concentration source are implanted with an energy of 50 keV and a dose of 6.0 ×. Injecting into the semiconductor substrate 1 under the condition of about 10 ¹⁵ .

(31) The photoresist 99 is removed. A heat treatment is performed at 900 degrees for about 85 minutes to activate the arsenic ions implanted in the step (30). An N-type high concentration source 11 is formed at a planned HVNch source formation position, and an N-type high concentration drain 9 is formed at a planned drain formation position. An N-type high-concentration source and drain 101 is formed at a position where the source and drain of LVNch are to be formed.

(32) A photoresist 103 having an opening at a position where HVPch and LVPch are to be formed is formed by photolithography. The photoresist 103 has the same pattern as the photoresist 85 formed in the step (27). With the ion implantation technique, the photoresist 103, the LOCOS oxide film 15, the gate electrode 19 and the sidewall 21 are used as a mask, and BF ₂ ions for high concentration drain and high concentration source are implanted with an energy of 50 keV and a dose of 3.0. Implanted into the semiconductor substrate 1 under conditions of about × 10 ¹⁵ .

(33) The photoresist 103 is removed. A BPSG (Boro-Phospho Silicate Glass) film 105 having a thickness of about 8000 mm is formed. Heat treatment is performed at 850 degrees for about 30 minutes. An SOG (Spin On Glass) film is formed on the BPSG film 105 to fill the step on the surface of the BPSG film 105. The illustration of the SOG film is omitted. Heat treatment is performed at 800 degrees for about 30 minutes. By these heat treatments, the BF ₂ ions implanted in the step (32) are activated. A P-type high concentration source 107 is formed at a planned source formation position of the HVPch, and a P-type high concentration drain 109 is formed at a drain formation planned position. A P-type high-concentration source / drain 111 is formed at a position where an LVPch source / drain is to be formed.

(34) A photoresist 113 having an opening at a position where a contact hole is to be formed is formed on the BPSG film 105 by photolithography. The contact hole 115 is formed by etching the BPSG film 105 using the photoresist 113 as a mask by an etching technique.

(35) The photoresist 113 is removed. A contact plug 23 is formed by filling the contact hole 115 with a metal material.
Thereafter, formation of metal wiring, formation of an interlayer insulating film, formation of a final protective film, and the like are performed.

  FIG. 12 is a schematic cross-sectional view for explaining another embodiment. FIG. 13 is a schematic plan view of the embodiment. FIG. 12 corresponds to the cross section at the position BB in FIG. The same parts as those in FIGS. 1 and 2 are denoted by the same reference numerals, and detailed description thereof will be omitted.

  In this embodiment, the source has the same structure as the drain, and the N-type high-concentration source 11 and the N-type low-concentration source 13 are not provided as compared with the MOS transistor shown in FIGS. A low concentration source 117 and an N-type high concentration source 119 are provided.

  The N-type low concentration source 117 is formed with a relatively low N-type impurity concentration, for example, the same N-type impurity concentration as the N-type low concentration drain 7. The N-type low concentration source 117 is formed shallower than the P-type low concentration well 3 and the P-type well 5. One end of the N-type low concentration source 117 is disposed in the P-type low concentration well 3 with a gap from the N-type low concentration drain 7 in the channel length direction. The other end of the N-type low concentration source 117 is disposed in the P-type well 3.

The N-type high-concentration source 119 is disposed in the N-type low-concentration source 117 on the P-type low-concentration well 3 with a distance from the end of the N-type low-concentration source 117. The N-type high-concentration source 119 is formed shallower than the N-type low-concentration source 117 at an N-type impurity concentration higher than that of the N-type low-concentration source 117, for example, the same concentration as the N-type high-concentration drain 9.
The N-type low-concentration source 117 and the N-type high-concentration source 119 form a double-diffused source of an N-channel high voltage MOS transistor.

The end of the gate electrode 19 on the source side is disposed on the N-type low concentration source 117 with a space from the N-type high concentration source 119 when viewed from above.
This embodiment can be formed in the same manner by changing the photolithography mask in the manufacturing process described with reference to FIGS.
In this embodiment, since the source has the same structure as the drain, it can cope with a case where a high breakdown voltage is required for the source.

  In this embodiment, as shown in FIG. 13, the end of the N-type low concentration drain 7 is disposed inside the end of the P-type low concentration well 3 in the channel width direction. However, the end portion of the N-type low concentration drain 7 in the channel width direction may be disposed at the same position as the end portion of the P-type low concentration well 3 or more than the end portion of the P-type low concentration well 3. It may be arranged outside.

  Similarly, in this embodiment, the end of the N-type low-concentration source 117 is arranged inside the end of the P-type low-concentration well 3 in the channel width direction. The end of the concentration source 117 may be arranged at the same position as the end of the P-type low concentration well 3 or may be arranged outside the end of the P-type low concentration well 3.

  In this embodiment, the side wall 21 is formed on the side surface of the gate electrode 19, but the side wall 21 may not be formed.

  FIG. 14 is a schematic sectional view for explaining still another embodiment. FIG. 15 is a schematic plan view of the embodiment. FIG. 14 corresponds to a cross section taken along the line CC in FIG. The same parts as those in FIGS. 1 and 2 are denoted by the same reference numerals, and detailed description thereof will be omitted.

This embodiment has a single source structure as a source, and does not include the N-type low concentration source 13 and the side wall 21 as compared with the MOS transistor shown in FIGS.
The end of the N-type high-concentration source 11 on the gate electrode side is overlapped with the position of the end of the gate electrode 19 on the source side as viewed from above.

  The N-type low concentration source 117 is formed with a relatively low N-type impurity concentration, for example, the same N-type impurity concentration as the N-type low concentration drain 7. The N-type low concentration source 117 is formed shallower than the P-type low concentration well 3 and the P-type well 5. One end of the N-type low concentration source 117 is disposed in the P-type low concentration well 3 with a gap from the N-type low concentration drain 7 in the channel length direction. The other end of the N-type low concentration source 117 is disposed in the P-type well 3.

This embodiment is formed by not performing the process for forming the N-type low concentration source 13 and the process for forming the sidewalls 21 in the manufacturing process described with reference to FIGS. be able to. The N-type low concentration source 117 is formed by implanting P-type impurity ions using the gate electrode 19 and the LOCOS oxide film 15 as a mask.
In this embodiment, since the source has a single source structure, the source resistance can be reduced, so that the on-resistance can be reduced.

  In this embodiment, as shown in FIG. 15, the end of the N-type low concentration drain 7 is arranged outside the end of the P-type low concentration well 3 in the channel width direction. However, the end portion of the N-type low concentration drain 7 in the channel width direction may be disposed at the same position as the end portion of the P-type low concentration well 3 or more than the end portion of the P-type low concentration well 3. You may arrange | position inside.

  Similarly, in this embodiment, the end of the N-type low-concentration source 117 is arranged inside the end of the P-type low-concentration well 3 in the channel width direction. The end of the concentration source 117 may be arranged at the same position as the end of the P-type low concentration well 3 or may be arranged outside the end of the P-type low concentration well 3.

  In the embodiment shown in FIGS. 1 and 2, the embodiment shown in FIGS. 12 and 13, and the embodiment shown in FIGS. 14 and 15, the present invention is applied to an N-channel high voltage MOS transistor. If the conductivity type of these MOS transistors is changed to the opposite conductivity type, a P-channel high voltage MOS transistor having the same operation and effect as the N-channel high voltage MOS transistor of the embodiment can be formed.

Although the embodiments of the present invention have been described above, the numerical values, materials, dimensions, arrangements, and the like are examples, and the present invention is not limited to these, and is within the scope of the present invention described in the claims. Various changes can be made.
For example, in the above embodiment, a high breakdown voltage MOS transistor is formed on the P-type semiconductor substrate 1, but in the present invention, a high breakdown voltage is applied to an N-type semiconductor substrate or a P-type or N-type epitaxial growth layer formed on the substrate. A MOS transistor can also be formed.

  Further, the LOCOS oxide film 15 may not be formed. Further, instead of the LOCOS oxide film 15, the element may be isolated by a buried oxide film or a thick oxide film formed by a method other than the LOCOS method.

  The present invention can be applied to a semiconductor device provided with a high voltage MOS transistor.

DESCRIPTION OF SYMBOLS 1 P type semiconductor substrate 3 P type low concentration well 5 P type well 7 N type low concentration drain 9 N type high concentration drain 11 N type high concentration source 13 N type low concentration source 17 Gate oxide film 19 Gate electrode 117 N type low Concentration source 119 N-type high concentration source

JP 11-31802 A

Claims (5)

A P-type low-concentration well formed on the surface of the semiconductor substrate with a relatively low P-type impurity concentration;
A P-type well adjacent to the P-type low-concentration well and surrounding the periphery of the P-type low-concentration well and having a P-type impurity concentration higher than that of the P-type low-concentration well; Prepared,
A high voltage MOS transistor is formed across the P-type low concentration well and the P-type well,
The high voltage MOS transistor is
The P-type low-concentration well and the semiconductor substrate surface shallower than the P-type well, one end is disposed in the P-type low-concentration well in the channel length direction, and the other end is disposed in the P-type well. An N-type low-concentration drain having a relatively low N-type impurity concentration;
N-type impurity concentration higher than that of the N-type low-concentration drain and shallower than the N-type low-concentration drain is formed on the surface of the semiconductor substrate, and the N-type is disposed in the N-type low-concentration drain on the P-type low-concentration well. An N-type high-concentration drain spaced from the end of the low-concentration drain; and
The P-type low-concentration well and the side opposite to the P-type low-concentration well end formed on the surface of the semiconductor substrate shallower than the P-type well and in which the N-type low-concentration drain is arranged in the channel length direction An N-type source having one end disposed in the P-type low-concentration well and spaced apart from the N-type low-concentration drain, and the other end disposed in the P-type well;
Formed on the semiconductor substrate between the N-type high-concentration drain and the N-type source via the gate insulating film, and the end on the drain side in the channel length direction as viewed from above is the N-type high-concentration drain And a gate electrode disposed on the N-type low-concentration drain at an interval.   2. The semiconductor device according to claim 1, wherein the N-type source is formed only by an N-type high-concentration source formed simultaneously with the N-type high-concentration drain.   The N-type source includes an N-type high-concentration source formed simultaneously with the N-type high-concentration drain, and an N-type impurity concentration lower than that of the N-type low-concentration source and shallower than the N-type high-concentration source. 2. The N-type low-concentration source formed on the surface and disposed between the source-side end of the gate electrode and the N-type high-concentration source in the channel length direction when viewed from above. A semiconductor device according to 1. The N-type source is
The P-type low-concentration well and the semiconductor substrate surface shallower than the P-type well, one end is disposed in the P-type low-concentration well in the channel length direction, and the other end is disposed in the P-type well. An N-type low concentration source having a relatively low N-type impurity concentration;
The semiconductor substrate is formed on the surface of the semiconductor substrate with an N-type impurity concentration higher than that of the N-type low-concentration source and shallower than the N-type low-concentration source, and in the N-type low-concentration source on the P-type low-concentration well. An N-type high-concentration source arranged at an interval from the end of the low-concentration source,
2. The semiconductor device according to claim 1, wherein an end portion of the gate electrode on the source side is disposed on the N-type low concentration source with an interval from the N-type high concentration source as viewed from above.   The semiconductor device according to claim 1, wherein the P-type and the N-type are opposite conductivity types.

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