JP2011028445A - Transmission and reception control device, electronic apparatus, data transmission method, and control program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a master device for preventing circuit destruction in a device without causing any bus fight even when a timing when a reply signal from a slave device is returned does not satisfy tolerance. <P>SOLUTION: A master 10 includes: a clock generation part 12 for generating a clock, and for transmitting the clock to each slave 20; a frame generation part 13 for generating a pseudo frame with a frame excluding the least significant bit in the first byte of serial data to be transmitted first to each slave 20, and for transmitting the pseudo frame to each slave 20; and a response time calculation part 14b for calculating a response time since the transmission of the pseudo frame to a data signal line 31 ends until ACK from the salve 20 with respect to the pseudo frame is detected. The frame generation part 13 adjusts a timing when the transmission of the frame to the data signal line is completed in the frame of each byte of serial data based on the response time. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a transmission / reception control apparatus for controlling transmission / reception of a clock and data for operating one or a plurality of devices, and a control program therefor.

  In recent years, various manufacturers have provided electronic devices having a serial bus serving as an interface between a master device and a slave device, and it has become essential to realize an interface that covers the standards of individual devices.

  This master device (hereinafter referred to as a master) is a device that generates a clock that enables data transfer, starts data transfer on the serial bus, and ends data transfer. A slave device (hereinafter referred to as a slave) is a device whose address is designated by the master, and receives data with a length of 8 bits from each master and performs an operation according to the data. It is.

  In addition, each time an end of each byte in the address and data transmitted from the master is completed, the slave transmits an acknowledge (acknowledge: hereinafter referred to as ACK) for notifying that the reception of the transmitted address and data has been completed. Generate and reply to master. Similarly, the master generates an ACK and returns it to the slave that is the data transmission source whenever each byte in the data input from the slave is completed.

  As shown in FIG. 9A, the timing for returning this ACK is usually the timing at which each byte (BIT7 to BIT0) in the data transmitted from the master to the slave does not overlap with the ACK transmitted from the slave to the master. Reply with.

  However, electronic devices equipped with masters and slaves do not necessarily design and manufacture all the built-in masters and slaves by a single manufacturer, but the current situation is that there is an allowable range in the timing of returning ACKs by slaves. It is.

  For this reason, when the slave does not satisfy this allowable range, as shown in FIG. 9B, each byte (particularly, the least significant bit) in the data to be transmitted from the master to the slave and the slave to the master are transmitted. ACK to be superimposed. This phenomenon is called bus fight, and as shown in FIG. 9C, the data at the high potential (power supply voltage: VCC) level and the ACK at the low potential (ground: GND) level are short-circuited. May destroy the circuitry in the master and / or slave.

  In contrast, the conventional bus contention detection method captures and temporarily stores the measurement result of the voltage level of the bus, reads the stored contents to the outside while updating each system clock cycle, and uses the read result to A race condition is detected (see, for example, Patent Document 1).

  The conventional bus fight prevention circuit includes an output buffer for transmitting data on the bus line, and a floating detection circuit for detecting whether or not the bus line is in a floating state. This floating detection circuit disables the corresponding output buffer so that data is not transmitted when it is detected that the bus line is not in a floating state and the data level to be transmitted is different (for example, patents). Reference 2).

  Further, the conventional output circuit is controlled to switch the output state of the output means from the enable state to the disable state by the delay signal output from the first delay circuit that delays the enable control signal by the first specified time. To do. Further, the conventional output circuit has means for performing step-by-step control for switching the output state of the output means from the enabled state to the disabled state in the second specified time (see, for example, Patent Document 3).

JP-A-63-208964 JP-A 1-1117541 Japanese Patent Laid-Open No. 10-320089

  However, the conventional bus contention detection method is a technique for detecting a bus fight by detecting the intermediate level between logic 0 and 1 or high impedance as the voltage level of the bus line. Detecting an intermediate value between logic 0 and 1 as the voltage level of the bus line means that a bus fight has already occurred, and the circuits in the master and slave may be destroyed.

  Further, the conventional bus fight prevention circuit detects that bus fight occurs by simultaneously asserting two output control signals, and disables the output buffer. On the other hand, when the timing of the bus signal itself is shifted with respect to the output control signal, a bus fight may occur and the circuits in the master and slave may be destroyed.

The conventional output circuit avoids bus fight by adjusting the timing of the enable control signal. On the other hand, as with the conventional bus fight prevention circuit, when the timing of the bus signal itself is shifted with respect to the enable control signal, a bus fight occurs and the circuits in the master and slave are destroyed. There is.
Therefore, the present invention provides a master device, an electronic apparatus, a bus control method, and a control program that can prevent a circuit in the device from being destroyed.

  The transmission / reception control device includes: a detection unit that detects a response signal from the device; a frame generation unit that adjusts the timing of completing transmission of the frame to the bus in each byte frame of serial data based on a detection result by the detection unit; .

  According to the disclosed transmission / reception control apparatus, it is possible to prevent the circuit in the device from being destroyed.

It is a block diagram which shows one Example of schematic structure of the electronic device which concerns on 1st Embodiment. It is explanatory drawing which shows one Example of the data transfer format in an I2C bus, (a) shows the data transfer format at the time of write access, (b) shows the data transfer format at the time of read access. It is explanatory drawing for demonstrating one Example of the pseudo frame which concerns on 1st Embodiment, (a) shows a normal frame, (b) shows a pseudo frame, (c) is a start bit. The following pseudo frame is shown. 2 is a timing chart for explaining an example of a bus fight avoidance method according to the first embodiment, wherein (a) shows a timing chart for explaining a method for calculating a response time, and (b) shows both. 4 is a timing chart for explaining a control method of the direction buffer unit. 3 is a flowchart illustrating an example of a setup processing procedure in the electronic device illustrated in FIG. 1. 3 is a flowchart illustrating an example of a processing procedure at the time of write access in the electronic device illustrated in FIG. 1. It is a block diagram which shows one Example of schematic structure of the electronic device which concerns on 2nd Embodiment. 8 is a flowchart illustrating an example of a processing procedure in the electronic device illustrated in FIG. 7. It is a timing chart for explaining bus fight, (a) shows the state where bus fight has not occurred, (b) shows the state where bus fight has occurred, and (c) shows the occurrence of bus fight. Shows a state where the signal is short-circuited.

  Here, the present invention can be implemented in many different forms. Therefore, it should not be interpreted only by the description of the following embodiment. Also, the same reference numerals are given to the same elements throughout the embodiment.

In the embodiment, the apparatus will be mainly described. However, as will be apparent to those skilled in the art, the present invention can also be implemented as a program and method usable on a computer. In addition, the present invention can be implemented in hardware, software, or software and hardware embodiments.
The program can be recorded on any computer-readable medium such as a hard disk, a CD-ROM (Compact Disc Read Only Memory), a DVD-ROM (Digital Versatile Disc Read Only Memory), an optical storage device, or a magnetic storage device. Furthermore, the program can be recorded on another computer via a network.

(First embodiment)
In the following description, the master 10 and the slave 20 will be described as an example of the information processing unit. It may be an information processing means that is not present.

  In FIG. 1, an electronic device 100 includes a master 10 and one or more (first, second,..., K-th (k is a natural number)) slaves 20 that are devices whose addresses are designated by the master 10. And a serial bus 30 for connecting between the master 10 and each slave 20.

  The electronic device 100 according to the present embodiment includes, for example, a communication device, and an FPGA (Field Programmable Gate Array) used as the master 10 and an optical module used as the slave 20 are connected to the serial bus 30. The However, electronic device 100 is not limited to a communication device as long as serial communication is performed between master 10 and slave 20 via serial bus 30. For example, an electronic device having a CPU (Central Processing Unit) as a master 10 and an EEPROM (Erasable Programmable ROM) as a slave 20 or a peripheral device such as a communication I / O (Input / Output) device and a camera as the slave 20 A mobile phone or the like can be considered.

  The serial bus 30 includes a data signal line 31 that is a signal line for transmitting data, an address, and the like, and a clock signal line 32 that is a signal line for transmitting a clock from the master 10 to the slave 20. Data, addresses, and the like are transmitted through the data signal line 31 in synchronization with the clock transmitted through the clock signal line 32.

  When a plurality of devices including the master 10 and the slave 20 transmit data simultaneously via the data signal line 31, an abnormal current flows between the plurality of devices, leading to destruction of the devices. For this reason, the data signal line 31 makes the transmission of data by a device other than the device that needs to transmit data electrically insulated (High-impedance: Hi-Z).

  Further, when all output terminals in other devices connected to any input terminal in the master 10 or the slave 20 simultaneously become high impedance, the input terminal is the same as that nothing is electrically connected. Yes, there is a possibility of destroying the device. For this reason, when the data signal line 31 is connected to a positive power supply voltage via a pull-up resistor 33 of about 100 kΩ and the data signal line 31 is opened, the H (Hight) state (hereinafter referred to as the H level) It is set so as to become.

  Examples of the serial bus 30 include an I2C (Inter-Integrated Circuit) bus manufactured by Philips. In this I2C bus, the data signal line 31 and the clock signal line 32 have bidirectionality, and are connected to a positive power supply voltage via a parallel resistance by a pull-up resistor 33 connected to each signal line. Therefore, the data signal line 31 and the clock signal line 32 are both at the H level when the bus is open.

The master 10 is a device having a function of starting data transfer on the serial bus 30, a function of generating a clock that takes data transfer timing, and a function of ending data transfer.
The master 10 roughly includes a serial timing generation unit 11, a clock generation unit 12, a frame generation unit 13, and a response signal reception unit 14.

  The serial timing generator 11 generates a clock (serial data clock) used for generating serial data including the address of the slave 20 and outputs the clock to the serial data generator 13a. In addition, the serial timing generation unit 11 generates a timing signal for synchronizing processing by each component in the master 10, and generates a clock generation unit 12, a serial data generation unit 13 a, a bidirectional buffer control unit 13 c, and a response signal reception unit 14. Output to.

  The clock generation unit 12 generates a clock serving as a reference for transmission timing of ACK that is a response signal from each slave 20, and transmits the clock to the serial timing generation unit in each slave 20 via the clock signal line 32. . The serial timing generation unit of each slave 20 generates a serial data clock based on the clock from the master 10 and outputs the serial data clock to the serial data generation unit in each slave 20.

The frame generation unit 13 generates a pseudo frame excluding at least the least significant bit in the frame of the first byte of serial data transmitted first to each slave 20. In addition, the frame generation unit 13 transmits the generated pseudo frame to each slave 20 via the data signal line 31.
Here, in describing the pseudo frame, an I2C bus is taken as an example of the serial bus 30, and data transfer between the master 10 and the slave 20 will be described with reference to FIG.

  The I2C bus data transfer is performed when the master 10 writes data to the slave 20, for example, when the transfer format shown in FIG. 2A is specified, and when the master 10 reads data from the slave 20, for example, FIG. The transfer format shown in (b) is defined. The master 10 completes transmission / reception with each slave 20 by using these transfer formats, whereby the operation of each slave 20 is started normally, and the entire electronic device 100 is operated.

  As shown in FIGS. 2A and 2B, the length of each byte sent to the data signal line 31 is 8 bits (BIT7, BIT6,..., BIT0), and data of one time There is no limit to the number of bytes that can be transferred. Each byte is followed by an acknowledge bit (ACK).

  Further, as shown in FIG. 2C, one clock (for one clock) is generated by the clock generator 12 of the master 10 for each data bit transferred through the data signal line 31, and the clock signal line It is transmitted to each slave 20 via 32.

  The slave 20 or the master 10 recognizes the rising edge (or falling edge) of the clock corresponding to the least significant bit (BIT0) of each byte of the serial data, and returns an ACK. While the clock is at the H level, the state of the data signal line 31 must be constant, and the data signal line 31 can change the state between the H level and the L (Low) level. Only when the clock of line 32 is at L level. That is, as shown in the timing chart of the uppermost stage and the second stage in FIG. 2C, from 0 (corresponding to the rising edge of each bit) to a quarter cycle (T / 4) in one clock. The clock is at L level. The clock is at H level from the quarter cycle (T / 4) to the three-quarter cycle (3T / 4), and from the three-quarter cycle (3T / 4) to one cycle (the rise of each bit). The clock is at L level (corresponding to the falling edge).

  In FIG. 2C, the uppermost row indicates a clock generated by the clock generation unit 12 of the master 10 and transmitted from the master 10 to each slave 20 via the clock signal line 32. The second row shows serial data sent from the master 10 to the data signal line 31. The serial signal occupies the data signal line 31 for each byte (BIT7 to BIT0). The data signal line 31 is opened (Hi-Z) to receive ACK. The third row shows serial data sent from the slave 20 to the data signal line 31. The data signal line 31 is occupied every time an ACK is transmitted, and data is received from the master 10 between each ACK. Therefore, the data signal line 31 is opened (Hi-Z). The bottom row shows the state of data transfer on the data signal line 31 by the serial data shown in the second and third rows.

  In the communication procedure of the I2C bus, unique states such as a start (START) condition and a stop (STOP) condition occur. This start condition occurs when the master 10 changes the data signal line 31 from H level to L level (start bit) when the clock signal line 32 is at H level. The stop condition is generated when the master 10 changes the data signal line 31 from the L level to the H level (stop bit) when the clock signal line 32 is at the H level. After the start condition is generated, the serial bus 30 is in a busy state, and after the stop condition is generated, the serial bus 30 is released and the serial bus 30 is in a free state.

  As shown in FIGS. 2 (a) and 2 (b), the transfer format includes a 7-bit slave address (DEVICE ADDRESS) and a 1-bit as the first byte following the start bit (START). Data direction bit (READ / WRITE) is specified. If the data direction bit is “0”, it indicates data transmission (write), and if it is “1”, it indicates a data request (read). That is, each slave 20 determines which slave 20 the master 10 selects from the 7-bit address, and determines data transmission or request from the master 10 based on the data direction bit.

  The master 10 transmits various setting data necessary for operation in the slave 20 to the slave 20 by receiving an ACK from the slave 20 for the first byte. 2A and 2B, a word address (WORD ADDRESS) is address data for designating an address in the slave 20.

Next, a pseudo frame according to the present embodiment will be described with reference to FIG.
As shown in FIG. 3A, a normal frame using each byte of serial data is a frame having a byte length of 8 bits. On the other hand, the pseudo frame according to the present embodiment is a frame having a byte length (for example, 7 bits shown in FIG. 3B) excluding at least the least significant bit (BIT0) from a normal frame.

  In particular, in the I2C bus, the first byte following the start bit corresponds to a 7-bit address indicating the address of the slave 20 and a data direction bit indicating data transmission or request to the slave 20. For this reason, as shown in FIG. 3C, the pseudo frame is a frame including a 7-bit address excluding the data direction bit, so that the address of the slave 20 is designated and the desired slave 20 A pseudo frame can be transmitted.

  The ACK for the first byte of serial data is returned based on the rising edge (or falling edge) of the eighth clock following the clock corresponding to the start bit. For this reason, in the extreme case, the pseudo frame may exclude all the bits of the first byte of the serial data (the first byte may be in the reception state).

  However, on the I2C bus, the first byte following the start bit is a 7-bit address indicating the address of the slave 20. For this reason, in order to identify the slave 20, it is preferable to use a pseudo frame that excludes only the data direction bit without deleting the 7-bit address.

  In particular, when ACK is superimposed on the bits (BIT7 to BIT1) higher than the least significant bit in each byte of serial data, the rising edge (or falling edge) of the clock corresponding to the least significant bit of each byte is recognized. ACK is returned. That is, it is an obvious violation of the standard at the interface of the serial bus 30 that the ACK is superimposed on the bits higher than the least significant bit in each byte of serial data. Normally, when a bus fight occurs, the ACK is the least significant bit. To be superimposed on.

  Note that the pseudo frame is generated by the frame generation unit 13, but more specifically, the serial data generation unit 13a, the bidirectional buffer unit 13b, and the bidirectional buffer control unit 13c included in the frame generation unit 13. Is generated by

  Further, the frame generation unit 13 adjusts the timing for completing the transmission of the frame to the data signal line 31 in each byte frame of the serial data based on the detection result by the response signal reception unit 14.

  The response signal reception unit 14 corresponds to a detection unit that detects a response signal from the slave 20, and is a block that receives an ACK that is a response signal from the slave 20, and includes a sampling clock generation unit 14a and a response time calculation unit 14b. And.

  The sampling clock generation unit 14a generates a sampling clock having a clock frequency higher than the clock frequency of the clock generated by the clock generation unit 12, and outputs the sampling clock to the response time calculation unit 14b. Note that the higher the sampling clock is, the higher the speed of the clock generated by the clock generation unit 12, the higher the resolution, and the higher the accuracy of detecting a potential level change point due to ACK described later. For example, when the serial bus 30 is an I2C bus, a sufficient resolution can be obtained by setting the clock frequency of the sampling clock to about 50 MHz with respect to the standard in which the clock frequency of the clock generated by the master 10 is 100 kHz to 400 kHz. Obtainable.

  The response time calculation unit 14b calculates a response time from the time when the pseudo frame is transmitted to the data signal line 31 to the time when the response signal from the slave 20 to the pseudo frame is detected based on the sampling clock, and is bidirectional. The data is output to the buffer control unit 13c.

  In the present embodiment, the time point when the pseudo frame has been sent to the data signal line 31 (hereinafter referred to as the response time start point) is the least significant bit of the pseudo frame (see FIG. 3B). For example, it is the time when the falling edge of BIT1) is sent to the data signal line 31. However, as long as it is managed by the master 10, the present invention is not limited to the time point when the falling edge of the least significant bit is sent to the data signal line 31. For example, the rising or falling edge of the sampling clock generated immediately after sending the falling edge of the least significant bit to the data signal line 31 may be used. Further, the time point when the response signal from the slave 20 to the pseudo frame is detected (hereinafter referred to as the end point of the response time) is the time point when the change point due to ACK described later is detected.

  Here, a method for calculating the response time will be described with reference to FIG. 4A shows the serial data transmitted from the master 10 to the data signal line 31, and the data after the least significant bit (BIT1) of the pseudo frame (BIT7 to BIT1) is transmitted. The signal line 31 is opened (Hi-Z) and is in a receiving state. The second stage shows the received data in the slave 20 by the serial data shown in the uppermost stage, and the high impedance in the uppermost stage is received by the slave 20 as H level by the pull-up resistor 33. Since the serial data sent from the master 10 to the data signal line 31 does not include BIT0, the received data in the slave 20 does not receive BIT0. However, for convenience of explanation, in the second stage, BIT0 is shown at a location that becomes H level by the pull-up resistor 33. The third row shows the sampling clock generated by the sampling clock generation unit 14a and output to the response time calculation unit 14b. Further, the fourth row shows the serial data sent from the slave 20 to the data signal line 31, and the rising edge (or the eighth clock following the clock corresponding to the start bit) corresponding to BIT0 (or ACK is transmitted by recognizing falling edge). The bottom row shows the reception data in the master 10 by the serial data shown in the fourth row, and the high impedance is received by the master 10 as H level by the pull-up resistor 33.

  As shown in FIG. 4A, the response time calculation unit 14b makes the rising edge of one clock in the sampling clock coincide with the start point of the response time, and accumulates the number of sampling clocks from this one clock. start. Then, the response time calculation unit 14b detects the change point of the potential level from H level to ACK (L level) (the rising edge of the eighth sampling clock in FIG. 4A). Then, the response time calculation unit 14b calculates an integrated value (eight in FIG. 4A) of the number of sampling clocks at the time when the change point is detected as the response time.

  Although it is ideal to detect the falling edge of ACK as the end point of the response time, as shown in FIG. 4A, the falling edge of ACK does not always match the rising edge of the sampling clock. . Therefore, as described above, the higher the sampling clock is, the shorter the interval between the ACK falling edge and the rising edge of the sampling clock at which the change point is detected. be able to. That is, the error between the falling edge of ACK and the rising edge of the sampling clock can be reduced, and an accurate value of the response time can be calculated.

  The serial data generation unit 13a is a block that generates serial data. For example, the serial data generation unit 13a is a parallel / serial conversion register that outputs data written as parallel data bit by bit as serial data to the bidirectional buffer unit 13b.

  The bidirectional buffer unit 13b is a bidirectional buffer that switches the data transfer direction (transmission direction and reception direction) with respect to the data signal line 31 of the serial bus 30 based on a control signal from the bidirectional buffer control unit 13c. The bidirectional buffer unit 13 b is connected to the bidirectional buffer unit in each slave 20 via the data signal line 31.

  The bidirectional buffer control unit 13c controls the bidirectional buffer unit 13b at least with the least significant bit in the first byte of serial data to be transmitted first to each slave 20, and sets the direction of data transfer to the reception direction (= High impedance state). That is, the bidirectional buffer control unit 13c controls the bidirectional buffer unit 13b in order to send the normal frame generated by the serial data generation unit 13a to the data signal line 31 as a pseudo frame.

  Further, the bidirectional buffer control unit 13c adjusts the timing for completing the transmission of the frame to the data signal line 31 in each byte frame of the serial data based on the response time calculated by the response time calculation unit 14b. That is, based on the response time, the bidirectional buffer control unit 13c sets the data transfer direction in the least significant bit of each byte of the serial data as the reception direction with respect to the serial data transmitted from the bidirectional buffer unit 13b. Adjust timing.

  In addition, since the response time calculated by the response time calculation unit 14b may be different for each slave 20, the bidirectional buffer control unit 13c uses the response time calculated for each slave 20 as identification information of each slave. A response time storage unit 13d that stores the data in association with each other is provided.

  Here, adjustment of the timing at which the data transfer direction is set to the reception direction in the least significant bit of each byte of the serial data will be described with reference to FIG. 4B shows the sampling clock generated by the sampling clock generation unit 14a and output to the response time calculation unit 14b. The third stage in FIG. 4A described above. It is the same as the clock frequency of the sampling clock. The lower row shows the state of data transfer on the data signal line 31 in which the data transfer direction in the least significant bit of each byte of serial data is adjusted to avoid the occurrence of bus fights. ing.

  As shown in FIG. 4B, the bidirectional buffer control unit 13c matches the rising edge of one clock in the sampling clock with the rising edge of the least significant bit in each byte of serial data. Then, the bidirectional buffer control unit 13c sets the least significant bit to the data signal line 31 so that the falling edge of the least significant bit in each byte does not exceed the integrated value of the number of sampling clocks that is the calculated response time. Adjust the time to continue sending. For example, when the calculated number of sampling clocks is 8, the bidirectional buffer control unit 13c, as shown in FIG. 4B, the data signal line 31 at the rising edge of the seventh clock of the sampling clock. The direction of data transfer with respect to is the receiving direction.

  As described above, the frame generation unit 13 can change the data transfer direction with respect to the normal frame generated by the serial data generation unit 13a only by switching the data transfer direction by the bidirectional buffer unit 13b and the bidirectional buffer control unit 13c. This frame can be easily generated.

  Next, a bus control method in the electronic device 100 according to the present embodiment will be described. In the following description, the case where an I2C bus is used as the serial bus 30 will be described as an example.

First, a setup for calculating a response time (integrated value of the number of sampling clocks) corresponding to each slave 20 performed before starting normal operation in the electronic device 100 will be described with reference to FIG.
The user of the electronic device 100 turns on the electronic device 100 and activates the master 10 and the slave 20 (step S1).

  The serial timing generation unit 11 of the master 10 generates a serial data clock and outputs it to the serial data generation unit 13a. The serial timing generator 11 generates a timing signal and outputs it to the clock generator 12, serial data generator 13a, bidirectional buffer controller 13c, and response signal receiver 14 (step S2).

The clock generator 12 generates a clock based on the timing signal, and transmits a common clock to all the slaves 20 connected via the clock signal line 32 (step S3).
Further, the sampling clock generation unit 14a generates a sampling clock based on the timing signal and outputs it to the response time calculation unit 14b (step S4).

  The serial data generation unit 13a generates a first byte including a 7-bit address of the designated slave 20 and a data direction bit indicating data transmission (writing), and outputs the first byte to the bidirectional buffer unit 13b (step S5). . That is, the serial data generation unit 13a generates a normal frame based on the first byte of serial data based on the serial data clock, and outputs it to the bidirectional buffer unit 13b.

The bidirectional buffer control unit 13c controls the bidirectional buffer unit 13b to change the data signal line 31 from H level to L level (start bit) when the clock signal line 32 is at H level, The direction of data transfer is set to the transmission direction (step S6).
Following the start bit, the bidirectional buffer unit 13b sends the 7-bit address of the first byte of serial data to the data signal line 31 (step S7).

  Then, the bidirectional buffer control unit 13c switches the data transfer direction from the transmission direction to the reception direction (= high impedance state) at the rising edge of the data direction bit in the first byte of the serial data (step S8). Note that the slave 20 receives the H level by the pull-up resistor 33. At this time, the response time calculation unit 14b matches the rising edge of one clock in the sampling clock with the timing of switching from the transmission direction to the reception direction, and starts integrating the clocks of the sampling clock.

  The addressed slave 20 recognizes the start of data transfer based on the start bit, and recognizes that its own device is designated based on the 7-bit address (step S9).

Also, the slave 20 to which the address is specified returns ACK to the master 10 based on the rising edge (or falling edge) of the eighth clock following the clock corresponding to the start bit (step S10).
And the bidirectional buffer part 13b of the master 10 will output ACK to the response time calculation part 14b of the response signal receiving part 14, if ACK from the slave 20 is received (step S11).

The response time calculation unit 14b detects the change point of the potential level from H level to ACK (L level), and calculates the integrated value of the number of sampling clocks at the time when the change point is detected as the response time (step S12). ).
Then, the response time calculation unit 14b outputs the calculated response time (the integrated value of the number of sampling clocks) to the bidirectional buffer control unit 13c (step S13).

The bidirectional buffer control unit 13c stores the input response time in the response time storage unit 13d in association with the identification information of the slave that is the target device of the response time (step S14).
Then, the master 10 determines whether or not a pseudo frame has been transmitted to all the slaves 20 connected via the clock signal line 32 (step S15).

If it is determined in step S15 that pseudo frames have not been transmitted to all the slaves 20, the master 10 designates the address of one slave 20 among the slaves 20 that have not transmitted pseudo frames, It returns to step S5 mentioned above.
If it is determined in step S15 that pseudo frames have been transmitted to all the slaves 20, the process ends.

  Next, serial communication between the master 10 and the slave 20 after the end of setup will be described with reference to FIG. In the following description, data transmission (writing) from the master 10 to one slave 20 shown in FIG. 2A will be described as an example. In addition, it is assumed that the master 10 and the slave 20 are already activated and transmit a common clock from the master 10 to all the slaves 20 connected via the clock signal line 32.

  The serial data generation unit 13a of the master 10 generates 4 bytes (slave address, word address, data 1, data 2) of serial data based on the serial data clock from the serial timing generation unit 11. Then, the serial data generation unit 13a outputs, to the bidirectional buffer unit 13b, the first byte including the 7-bit address of the designated slave 20 and the data direction bit indicating data transmission in the serial data (step S1). S101).

  The bidirectional buffer control unit 13c refers to the response time (integrated value of the number of sampling clocks) corresponding to the designated slave 20 from the response time storage unit 13d (step S102).

The bidirectional buffer control unit 13c controls the bidirectional buffer unit 13b to change the data signal line 31 from the H level to the L level (start bit) when the clock signal line 32 is at the H level. Thus, the data transfer direction is set to the transmission direction (step S103).
Then, the bidirectional buffer unit 13b starts to send the first byte of serial data to the data signal line 31 (step S104).

  Then, the bidirectional buffer control unit 13c makes the rising edge of one clock in the sampling clock coincide with the rising edge of the least significant bit of the first byte, and starts integrating the number of sampling clocks (step S105).

  Further, the bidirectional buffer control unit 13c switches the data transfer direction from the transmission direction to the reception direction so that the falling edge of the least significant bit of the first byte does not exceed the response time referenced in step S102 (step S106). ).

  Then, the slave 20 to which the address is designated returns an ACK to the master 10 based on the rising edge (or falling edge) of the clock corresponding to the least significant bit of the first byte (step S107).

When the bidirectional buffer unit 13b of the master 10 receives the ACK from the slave 20, the bidirectional buffer unit 13b outputs the ACK to the serial data generation unit 13a (step S108).
Further, the serial data generation unit 13a outputs the next byte to the bidirectional buffer unit 13b based on the input of ACK, and performs the above-described steps S104 to S108 (the first byte is the second byte, the third byte or the first byte). Repeat for 4 bytes).

  The bidirectional buffer control unit 13c controls the bidirectional buffer unit 13b to change the data signal line 31 from the L level to the H level (stop bit) when the clock signal line 32 is at the H level. Then, the data signal line 31 is opened (step S109). As a result, the master 10 finishes data transmission (writing) to one slave 20.

  As described above, in the master 10 according to the present embodiment, the frame generation unit 13 completes transmission of a frame to the data signal line 31 in each byte frame of serial data based on the detection result by the response signal reception unit 14. Adjust the timing. Thereby, even if the master 10 according to the present embodiment returns the response signal from the slave 20 without satisfying the allowable range, the master 10 can destroy the circuit in the device without generating a bus fight. There is an effect that it can be prevented.

  In particular, the master 10 according to the present embodiment transmits a pseudo frame to the slave 20 and calculates the response time of the response signal from the slave 20 before starting normal operation by the electronic device 100. In the normal operation by the electronic device 100, the master 10 adjusts the transmission time to the data signal line 31 in the least significant bit of each byte of serial data based on the calculated response time. As a result, the master 10 according to the present embodiment does not generate a bus fight even when the response timing of the response signal by the slave 20 does not satisfy the allowable range, and the circuit in the device There is an effect that destruction can be prevented.

Further, the master 10 according to the present embodiment can respond to the transmission timing of the response signal by each slave 20 without changing the circuit of the master 10 even when the transmission timing of the response signal in the plurality of slaves 20 is different. There is an effect that it can be performed.
In particular, the fact that it is possible to respond to the transmission timing of the response signal by each slave 20 without changing the circuit of the master 10 increases the manufacturing cost due to the replacement of the master 10 or the slave 20 or the circuit design change. There exists an effect that it can control.

  In the present embodiment, the pseudo frame is generated with the frame in the first byte of the serial data transmitted first to each slave 20, but the first serial data transmitted to each slave 20 is first generated. It does not have to be a single byte. However, it is preferable to generate a pseudo frame with the first byte of serial data transmitted first to each slave 20 because bus fight can be completely prevented.

  In this embodiment, the ACK response time is calculated using a pseudo frame, but the ACK response time may be calculated using a normal frame. In this case, the start point of the response time is the time when the master 10 sends the falling edge of the least significant bit of the normal frame (BIT0 in FIG. 3A) to the data signal line 31. However, it is preferable to calculate the ACK response time using the pseudo frame because the bus fight can be prevented even for the frame for calculating the ACK response time.

  In the above description, the I2C bus is taken as an example of the serial bus 30 and the data transfer between the master 10 and the slave 20 has been described. However, the serial bus 30 is not limited to the I2C bus. The present invention can also be applied to. The type of bus used for data transfer is not limited to the serial bus 30, and the present invention can also be applied to a parallel bus.

(Second Embodiment)
In FIG. 7, the electronic device 100 according to the present embodiment connects the master 10 and each slave 20 separately from the data signal line 31 and the clock signal line 32, and power-on reset from the master 10 to each slave 20. Is provided with a control signal line 34 for enabling the control.

The slave 20 includes a power supply unit 20a having a disable function for stopping its own operation based on an external control signal.
When the response time calculated by the response time calculation unit 14b is outside the preset range, the master 10 sends a control signal for stopping the corresponding slave 20 via the control signal line 34. The slave control unit 15 for transmitting to the power source unit 20a is provided. The slave control unit 15 holds a threshold value as a preset range.

  Here, as a preset range, for example, if the frame generation unit 13 generates a pseudo frame as a 7-bit frame, a quarter cycle of one clock in the clock generated by the clock generation unit 12 A range larger than (T / 4) is set. As a result, if the response time is outside the preset range, the slave 20 returns an ACK without recognizing the rising edge of the clock corresponding to the least significant bit of the first byte including the pseudo frame. Means. That is, when the response time of the response signal from the slave 20 is outside the preset range, it can be seen that the slave 20 violates the standard in the interface of the serial bus 30.

  As a preset range, if the pseudo frame is generated as an n-bit frame (0 <= n <8, where n is a natural number), (1 + 4 (7−n)) T / 4 (T is A range larger than the period of one clock) is set as a preset range.

  Further, the preset range may be set according to the number of sampling clocks. For example, if the rising edge of the third clock of the sampling clock shown in FIG. 4A matches the rising edge of the clock generated by the clock generator 12, the number of sampling clocks is three. Set a large range.

Next, a bus control method in the electronic apparatus 100 according to the present embodiment will be described with reference to FIG.
First, the response time calculation unit 14b of the master 10 outputs the response time calculated in step S12 in the first embodiment described above to the slave control unit 15 together with the identification information of the slave 20 that is the target device of this response time. (Step S201).

The slave control unit 15 compares the threshold that is a preset range with the input response time, and determines whether or not the response time is within the preset range (step S202).
In step S202, if the input response time is within a preset range, the process ends.

In step S202, if the input response time is outside the preset range, a control signal is transmitted to the power supply unit 20a of the corresponding slave 20 via the control signal line 34 (step S203).
Then, the slave 20 that has received the control signal activates the disable function for the power supply unit 20a, turns off the power of the slave 20 (step S204), and ends the process.

  As described above, in the electronic device 100 according to the present embodiment, the malfunctioning slave 20 that does not comply with the standards in the interface of the serial bus 30 is stopped as a failure, thereby preventing malfunctions caused by the slave 20 that does not comply with the standards in advance. There is an effect of being able to.

  In particular, the slave 20 that violates the standard may have the ACK returned to the master 10 superimposed on the higher-order bits than the least significant bit of each byte of serial data from the master 10. Therefore, if the timing for completing the transmission of the frame to the data signal line 31 in the frame of each byte of serial data is adjusted based on the response time, at least the least significant bit of each byte of serial data is transmitted. It will be in a state that is not. In other words, the master 10 cannot transmit the correct data consisting of 8 bits to the slave 20 that violates the standard.

[Appendix] The following appendices are further disclosed with respect to the embodiment including the above examples.
(Supplementary Note 1) In a transmission / reception control device that transmits serial data to a device via a bidirectional bus and receives a response signal from the device for each byte of the serial data, the response signal from the device is detected. A transmission / reception control device comprising: a detection unit configured to adjust a timing for completing transmission of a frame to the bus in each byte frame of the serial data based on a detection result of the detection unit;

(Supplementary Note 2) In a transmission / reception control device that transmits serial data to a device via a bidirectional bus connected to a pull-up resistor, and receives a response signal from the device for each byte of the serial data. A clock generation unit that generates a clock serving as a reference for transmission timing of a response signal from the device, and transmits the clock to the device via the clock signal line of the bus; and the serial data as the data signal line of the bus A response time calculation unit that calculates a time when a response signal from the device generated based on the clock and the state of the bus by the pull-up resistor is detected; and calculated by the response time calculation unit Based on the measured time, the data signal line in each byte frame of the serial data Reception control unit and a frame generator for adjusting the completion timing the transmission of the frame that.

(Supplementary note 3) In the transmission / reception control device according to supplementary note 2, the frame generation unit generates a pseudo frame shorter than a frame of each byte of the serial data, and transmits the pseudo frame to the device via the data signal line of the bus. The pseudo time frame is transmitted, and the response time calculation unit sends the pseudo frame to the data signal line, and then generates the pseudo frame from the device generated based on the clock and the state of the bus by the pull-up resistor. A transmission / reception control device that calculates a time until a response signal is detected.

(Supplementary Note 4) In the transmission / reception control device according to Supplementary Note 2 or 3, the frame generation unit and the serial data generation unit that generates the serial data, and bidirectional that switches a data transfer direction to the data signal line of the bus Of the serial data generated by the buffer unit and the serial data generation unit and transmitted from the bidirectional buffer unit, at least the least significant bit in the first byte of serial data to be transmitted first to the device, A bi-directional buffer control unit that controls the bi-directional buffer unit to change the direction of data transfer to the receiving direction, and the bi-directional buffer control unit is configured to perform the both based on the time calculated by the response time calculating unit. For the serial data sent from the direction buffer part, the bottom of each byte of the serial data Reception control device that adjusts the bit, the timing of the direction of the data transfer to the receiving direction.

(Supplementary Note 5) In the transmission / reception control device according to any one of Supplementary Notes 2 to 4, the transmission / reception control device includes a sampling clock generation unit that generates a sampling clock having a clock frequency higher than a clock frequency of the clock generated by the clock generation unit, The transmission / reception control device in which the response time calculation unit calculates the response time based on the sampling clock generated by the sampling clock generation unit.

(Supplementary note 6) In the transmission / reception control device according to Supplementary note 3, the first byte of the serial data includes a 7-bit address indicating the address of the device, and a data direction bit indicating transmission or request of data to the device And the pseudo-frame is a frame including the 7-bit address excluding the data direction bit.

(Additional remark 7) The 1st device which produces | generates the clock which enables data transfer, and starts and complete | finishes data transfer, The 2nd device to which an address is designated by the said 1st device, The said 1st device And a bidirectional bus connected to a pull-up resistor that connects between the second devices, the first device generates the clock, and the clock signal line of the bus is connected to the bus. Via the clock generation unit for transmitting the clock to the second device, and after sending the serial data to the data signal line of the bus, based on the clock and the state of the bus by the pull-up resistor A response time calculation unit for calculating a time when a response signal from the second device to be generated is detected; and a time calculated by the response time calculation unit. An electronic apparatus comprising at each byte of a frame of serial data, and a frame generator for adjusting the completion timing the transmission of the frame with respect to the data signal lines.

(Supplementary note 8) The electronic device according to supplementary note 7, comprising a control signal line for connecting the first device and the second device, and a disable function for stopping its own operation based on a control signal from the outside When the second device includes a power supply unit having the above and the time calculated by the response time calculation unit is out of a preset range, a control signal for stopping the corresponding second device is provided. An electronic apparatus provided with a slave control unit that transmits to a power supply unit of the second device via a signal line.

(Supplementary Note 9) The first device generates a clock that enables data transfer, transmits serial data to the second device via a bidirectional bus to which a pull-up resistor is connected, and In the data transmission method in which the second device returns a response signal for each byte of the serial data to the first device, the first device has a reference of the transmission timing of the response signal from the second device. Generating a clock and transmitting the clock to the second device via the clock signal line of the bus, and the first device sends the serial data to the data signal line of the bus. After sending, a response signal from the second device is generated based on the clock and the state of the bus by the pull-up resistor. A response time calculating step for calculating the output time, and sending a frame to the data signal line in each byte frame of the serial data based on the time calculated by the first device in the response time calculating step. A data transmission method comprising: a timing adjustment step of adjusting a completion timing.

(Supplementary Note 10) A computer of a transmission / reception control device that transmits serial data to a device via a bidirectional bus connected to a pull-up resistor and receives a response signal from the device for each byte of the serial data. In a control program to function, a computer generates a clock that is a reference of transmission timing of a response signal from the device, and a clock generation unit that transmits the clock to the device via a clock signal line of the bus; Response time calculation for calculating a time for detecting a response signal from the device generated based on the clock and the state of the bus by the pull-up resistor after sending the serial data to the data signal line of the bus And the time calculated by the response time calculating means, In each byte of the frame of the real data, the control program to function as a timing adjusting means for adjusting the completion timing the transmission of the frame with respect to the data signal lines.

DESCRIPTION OF SYMBOLS 10 Master 11 Serial timing generation part 12 Clock generation part 13 Frame generation part 13a Serial data generation part 13b Bidirectional buffer part 13c Bidirectional buffer control part 13d Response time storage part 14 Response signal receiving part 14a Sampling clock generation part 14b Response time calculation Unit 15 Slave control unit 20 Slave 20a Power supply unit 30 Serial bus 31 Data signal line 32 Clock signal line 33 Pull-up resistor 34 Control signal line 100 Electronic device

Claims (8)

In a transmission / reception control device that transmits serial data to a device via a bidirectional bus and receives a response signal from the device for each byte of the serial data.
A detection unit for detecting a response signal from the device;
Based on the detection result by the detection unit, in each byte frame of the serial data, a frame generation unit that adjusts the timing for completing transmission of the frame to the bus;
A transmission / reception control device comprising: In a transmission / reception control device that transmits serial data to a device via a bidirectional bus connected to a pull-up resistor and receives a response signal from the device for each byte of the serial data,
A clock generation unit that generates a clock serving as a reference of transmission timing of a response signal from the device, and transmits the clock to the device via a clock signal line of the bus;
Response time calculation for calculating a time for detecting a response signal from the device generated based on the clock and the state of the bus by the pull-up resistor after sending the serial data to the data signal line of the bus And
Based on the time calculated by the response time calculation unit, a frame generation unit that adjusts the timing of completing transmission of the frame to the data signal line in each byte frame of the serial data;
A transmission / reception control device comprising: The transmission / reception control device according to claim 2,
The frame generation unit generates a pseudo frame shorter than the frame of each byte of the serial data, and transmits the pseudo frame to the device via the data signal line of the bus;
After the response time calculation unit detects the response signal from the device generated based on the clock and the state of the bus by the pull-up resistor after sending the pseudo frame to the data signal line The transmission / reception control device for calculating the time of In the transmission / reception control device according to claim 2 or 3,
The frame generator
A serial data generation unit for generating the serial data;
A bidirectional buffer unit for switching the direction of data transfer to the data signal line of the bus;
Of the serial data generated by the serial data generation unit and transmitted from the bidirectional buffer unit, at least the least significant bit in the first byte of serial data to be transmitted first to the device, the bidirectional buffer unit A bidirectional buffer control unit that controls the data transfer direction to receive direction;
With
The data transfer in the least significant bit of each byte of the serial data with respect to the serial data transmitted from the bidirectional buffer unit based on the time calculated by the response time calculation unit by the bidirectional buffer control unit A transmission / reception control device that adjusts the timing for changing the direction of the signal to the reception direction. A first device that generates a clock that enables data transfer and starts and ends the data transfer; a second device that is addressed by the first device; the first device and the second device In an electronic device comprising a bidirectional bus connected to a pull-up resistor that connects between devices,
The first device is
A clock generator that generates the clock and transmits the clock to the second device via the clock signal line of the bus;
After sending the serial data to the data signal line of the bus, a time for detecting a response signal from the second device generated based on the clock and the state of the bus by the pull-up resistor is calculated. A response time calculator,
Based on the time calculated by the response time calculation unit, a frame generation unit that adjusts the timing of completing transmission of the frame to the data signal line in each byte frame of the serial data;
Electronic equipment comprising. The electronic device according to claim 5,
A control signal line for connecting the first device and the second device;
The second device includes a power supply unit having a disable function for stopping its own operation based on an external control signal,
When the time calculated by the response time calculation unit is outside a preset range, a control signal for stopping the corresponding second device is sent to the power supply of the second device via the control signal line. An electronic apparatus provided in the first device with a slave control unit that transmits to the unit. A first device generates a clock that enables data transfer, and transmits serial data to a second device via a bidirectional bus connected to a pull-up resistor, and the second device In the data transmission method of returning a response signal for each byte of the serial data to the first device,
A clock in which the first device generates a clock serving as a reference for transmission timing of a response signal from the second device, and transmits the clock to the second device via the clock signal line of the bus. Generation step;
After the first device sends the serial data to the data signal line of the bus, a response signal from the second device generated based on the clock and the state of the bus by the pull-up resistor A response time calculating step for calculating the time when
A timing adjustment step for adjusting a timing for completing transmission of a frame to the data signal line in each byte frame of the serial data based on the time calculated by the response time calculating step;
A data transmission method comprising: A control program for functioning a computer of a transmission / reception control device that transmits serial data to a device via a bidirectional bus connected to a pull-up resistor and receives a response signal from the device for each byte of the serial data In
A clock generating means for generating a clock that is a reference for transmission timing of a response signal from the device, and transmitting the clock to the device via the clock signal line of the bus; Response time calculating means for calculating a time when a response signal from the device generated based on the clock and the state of the bus by the pull-up resistor is detected after being sent to the data signal line; and the response time A control program that functions as a timing adjustment unit that adjusts a timing for completing transmission of a frame to the data signal line in each byte frame of the serial data based on the time calculated by the calculation unit.

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