JP2011019233A - Upsampling device and downsampling device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an upsampling device and downsampling device, improving processing efficiency while maintaining high accuracy by effectively utilizing a layered structure of layout data.SOLUTION: An upsampling unit 44 is equipped with: a mesh adding section 441; and a new mesh data setting section 442. The mesh adding section 441 adds a new mesh to image data inputted from a spatial filter section 423. The new mesh data setting section 442 sets a value of zero to the image data on the added mesh and outputs the image data to an inverse Fourier transform section 424 together with the image data before the mesh addition.

Description

  The present invention relates to an upsampling device and a downsampling device, and more particularly, to an improvement for improving efficiency while maintaining accuracy.

  In recent years, there has been remarkable progress in miniaturization of large-scale integrated circuits (LSIs), and the development of microfabrication technology has made this possible. Among them, the optical transfer technology is still at the center of the microfabrication technology due to the high throughput by batch exposure and the achievements of the optical technology that has been cultivated for 100 years.

  However, at the present time when the processing dimension of the fine pattern has become smaller than the wavelength of the exposure light, it is important to identify the limitations of the optical transfer technology and overcome the limitations of resolution and depth of focus. In order to perform such an analysis, a technique for calculating an optical image, a technique for correcting distortion generated from the calculated optical image, and the like have attracted particular attention in recent years. FIG. 32 is a flowchart showing a procedure of a mask data correction method disclosed in Patent Document 1 as an example of the invention of the present inventor.

  This method is disclosed in detail in Patent Document 1 and is already a well-known technique, so only a brief introduction will be given here. When processing S90 by this method is started, circuit design and layout design are performed (S91, S92). First, layout data is stored in a storage medium (S93). This layout data defines the shape and hierarchical structure of basic elements of a figure having a hierarchical structure. Next, layout data is developed (S94), and process conditions are input (S95). Thereafter, a mesh is generated (S96), and image calculation is performed (S97). Next, the figure is corrected through comparison between the image calculation result and the layout data (S98), and the correction data as the result is output (S99), thereby completing the process S90.

  Furthermore, when using these techniques, it is necessary to pay attention to the deterioration of the optical image caused by the aberration of the optical system. The details of this technique are described in Patent Document 2 or Patent Document 3 that is the invention of the present inventor. In addition, there are cases where full-shot level long-range correlation becomes a problem.

In order to perform these evaluations or optimizations, it is necessary to examine the correspondence between the calculation results related to the optical image and the experimental results in various cases. However, the calculation related to the optical image generally requires a large amount of calculation, such as the need to perform inverse Fourier transform after Fourier transform of the mask figure. Therefore, many proposals have been made to execute the Fourier transform at high speed. Common things are:
(1) Fast Fourier Transformation (FFT) (for example, “Waveform Data Processing for Scientific Measurements” described in Shigeo Minami, CQ Publisher);
(2) OCA (Optical Coherent Approximation) (for example, described in YC Pali and T. Kailath J. OP Soc. Am A, Vol. 11 (1994) 2438);
(3) Unequally spaced Fourier transform (eg, E. Barouch, B. Bradie, U. Hollerbach, and SA Orszag, J. Vac. Sci. And Technol. B8 (1990) 1432; E. Barouch, B. Bradie, U Hollerbach, and SAOrszag, Proc. SPIE Vol.1465 (1991) 254; E. Barouch, U. Hollerbach, SAOrszag, B. Bradie and M. Peckcrar, IEEE Electron Device Lett., EDL-12 (1991) 513, etc. Description);
(4) Partial copyrent approximation (for example, M. Yeung: Proc, Kodak Microelectoronics Seminar INTERFACE '85 (KTI Chemicals, Inc, San Diego, 1986) p. 115; M. Yeung: Proc. SPIE Vol. 922 (1988) 149); and
(5) Massively parallel operations (for example, K, Kamon, W. Wakamiya, H. Nagata, K. Moriizumi, T, Miyamoto, Y, Myoi and M. Tanaka; Proc, SPIE Vol. 2512 (1995) 491; T .Hanawa, K.kamon, A.Nakae, S.Nakao, and K.Moriizumi: Proc, SPIE Vol.2726 (1996) 640; A.Nakae, K.Kamon, T.Hanawa, K.Moriizumi and S.Nakao : Jpn.J.Appl.phys.Vol.35 (1996) 6395 etc.) is known.

  In recent years, remarkable speedup has been promoted through these technologies. Each of these technologies is a very effective technology, and made a great contribution to the innovation of microfabrication technology. However, it is still not enough to combine them for LSI full-shot calculations. . This is because, as an example, a 1G (gigabit) DRAM currently under development is formed by laying a huge number of 1G transistors vertically and horizontally to form a memory cell array. Even a logic device (logic circuit) has a structure including a large number of small RAMs. In addition, it is considered that LSIs will continue to be highly integrated.

  Conventionally, a technique (for example, dracula of cadence) that processes graphic data after flat development once has been common. On the other hand, in order to handle a large number of figures, a device that performs operations such as layout verification using the hierarchical structure of figure data (eg, arant hercules; menter caliber; lucent clover, etc.) Has been developed recently. In these apparatuses, as shown in FIG. 33, some data is collected in a cell 91, and the processing is speeded up by performing graphic operations and the like while maintaining the arrangement and hierarchical structure of the cells. . In FIG. 33, a large number of cells 91 are arranged in the image generation area 90, and a graphic basic element 92 is arranged in the cells 91.

  Since these devices can execute simple calculations and comparisons between figures quickly, they are suitable for applications such as design rule checking, simple logic calculations between figures, or sizing.

JP-A-8-297692 Japanese Patent Laid-Open No. 9-167731 Japanese Patent Laid-Open No. 10-335224

  However, in the case where the influence or correlation of a certain figure spreads over a plurality of cells, each element cell must be expanded, so that not only the data processing speed cannot be achieved but also the processing capability is rather reduced. It is known that even deterioration may occur.

  On the other hand, in the application of optical image calculation, the influence of a certain figure extends within the coherence distance of the optical system. In addition, the microloading effect in dry etching or the proximity effect in mask drawing may reach about 10 μm. Therefore, it is necessary to calculate how the graphic elements interfere with each other or influence each other. Rather, it can be said that it is essential to calculate the state of this correlation in various process simulations including lithography. In general, this optical coherence or various proximity effects often extend over a plurality of cells, and conventionally, it has been necessary to evaluate the cells by fully developing them. Therefore, there is a problem that even if the hierarchized data is used for the proximity correction calculation, all the data must be finally expanded, and the effectiveness of the hierarchical processing cannot be fully exhibited.

  The present invention has been made in order to solve the above-described problems in the prior art, and up-sampling that can effectively use the hierarchical structure of layout data to increase the processing efficiency while maintaining high accuracy. An object is to provide a device and a downsampling device.

  An apparatus according to a first aspect of the present invention is an upsampling apparatus that performs upsampling on discrete data, and performs the Fourier transform on the discrete data defined in a one-dimensional or multi-dimensional space, thereby obtaining the discrete data. A Fourier transform unit for transforming into a set of frequency components, the set of frequency components as data on a mesh set in the one-dimensional or multi-dimensional Fourier space, and a new mesh in the Fourier space A mesh adding unit to be added to the data, a new mesh data setting unit for setting a value of zero to the data on the added mesh, and outputting together with the data on the mesh before being added, and the new mesh data setting An inverse Fourier transform unit that performs inverse Fourier transform on the data output from the unit.

  An apparatus according to a second aspect of the present invention is a downsampling apparatus that performs downsampling on discrete data, and performs the Fourier transform on the discrete data defined in a one-dimensional or multi-dimensional space to thereby convert the discrete data. A Fourier transform unit for transforming into a set of frequency components, the set of frequency components as data on a mesh set in the one-dimensional or multi-dimensional Fourier space, and a part of the mesh in the Fourier space And a mesh removing unit that outputs the data after being removed, and an inverse Fourier transform unit that performs inverse Fourier transform on the data output from the mesh removing unit.

  In the apparatus according to the first aspect of the invention, upsampling is performed in Fourier space, so that interpolation that reflects the entire discrete data is performed. For this reason, smooth and natural data after upsampling that cannot be obtained by simple linear interpolation can be obtained.

  In the apparatus according to the second aspect of the invention, downsampling is performed in Fourier space, so that interpolation that reflects the entire discrete data is performed. For this reason, although the number of samplings is reduced, smooth and natural data after downsampling processing that cannot be obtained by simple linear interpolation or the like can be obtained.

It is a block diagram of the various manufacturing apparatuses by embodiment. It is a block diagram which shows the internal structure of the image calculation part 42 of FIG. It is a flowchart which shows the manufacturing process by the various manufacturing apparatuses of FIG. 6 is an explanatory diagram of processing according to Embodiment 1. FIG. It is explanatory drawing of operation | movement by the image calculation part. It is explanatory drawing of operation | movement by the image calculation part. It is explanatory drawing of operation | movement by the figure correction apparatus. It is a partial cutaway perspective view showing a configuration example of a mask generation device 61. FIG. 6 is an explanatory diagram illustrating a configuration example of an optical transfer device 62. It is a manufacturing process diagram which illustrates the manufacturing process of a semiconductor device. 3 is a plan view showing a configuration example of a CMP apparatus 64. FIG. It is a manufacturing process diagram which illustrates the manufacturing process of a semiconductor device. 4 is a block diagram showing an internal configuration of a Fourier transform unit 421. FIG. 5 is a flowchart showing processing by a Fourier transform unit 421. FIG. 10 is an operation explanatory diagram illustrating processing by a Fourier transform unit 421. FIG. 10 is an operation explanatory diagram illustrating processing by a Fourier transform unit 421. FIG. 10 is an operation explanatory diagram illustrating processing by a Fourier transform unit 421. It is a block diagram which shows the internal structure of the element figure Fourier-transform part 4212 and the synthetic | combination part 422. It is a flowchart which shows the process by the element figure Fourier transform part 4212 and the synthetic | combination part 422. FIG. 3 is a block diagram showing an internal configuration of a mesh generation unit 41. FIG. 5 is a flowchart showing processing by a mesh generation unit 41. 3 is a block diagram showing an internal configuration of an upsampling unit 44. FIG. 5 is a flowchart showing processing by an upsampling unit 44. FIG. 10 is an operation explanatory diagram showing processing by the upsampling unit 44. 4 is a block diagram showing an internal configuration of a downsampling unit 45. FIG. 4 is a flowchart showing processing by a downsampling unit 45. FIG. 11 is an operation explanatory diagram illustrating processing by the downsampling unit 45. 3 is a block diagram showing a configuration of an upsampling device 80. FIG. 3 is a flowchart showing processing by an upsampling device 80. 2 is a block diagram showing a configuration of a downsampling device 90. FIG. 3 is a flowchart showing processing by a downsampling device 90. It is a flowchart which shows the procedure of the conventional mask data correction method. It is explanatory drawing which shows an example of the hierarchical structure employ | adopted with the conventional mask data correction method.

Embodiment 1 FIG.
FIG. 1 is a block diagram showing the configuration of various manufacturing apparatuses that execute the manufacturing process of the present embodiment from circuit design to product shipment of devices (for example, semiconductor devices and liquid crystal display devices) to be manufactured. FIG. 2 is a block diagram showing an internal configuration of the image calculation unit 42 in FIG. Further, FIG. 3 is a flowchart showing a procedure of a manufacturing process executed using the various manufacturing apparatuses of FIG.

  Hereinafter, the apparatus and method of the present embodiment will be described with reference to FIGS. It should be noted that each element other than the image calculation unit 42 in FIG. 1 and each process other than the image calculation process (S24) in FIG. 3 is a well-known technique in itself, and detailed description thereof will be omitted. Only a brief explanation will be given. In the following description, an example in which the device to be manufactured is a semiconductor device will be mainly taken up, but the present invention is not limited to this embodiment.

  When the manufacturing process of the device to be manufactured is started, layout data representing the original drawing is created by the original drawing creating device 30 (S1). Here, the original figure means the figure before the figure correction to be compared with the figure after the figure correction (S3) is applied. In the original drawing creation device 30, first, circuit design (S11) is performed by the circuit design unit 31 based on design conditions given from the outside by the operator. The circuit design is performed so that the circuit to be designed can achieve a desired function and performance.

  Thereafter, the layout design unit 32 performs layout design (S12) based on the data related to the circuit for which the circuit design has been performed and the design conditions given from the outside. That is, layout data that defines the pattern shape of the transfer mask for realizing the designed circuit on the semiconductor substrate is generated. The generated layout data is stored in the layout data storage medium 33 (S13).

  In a large-scale integrated circuit, many basic elements are often arranged in an array in a circuit element such as a memory cell array. If the layout data of such a circuit is stored in the form of basic elements + hierarchical structure, the storage capacity of the storage medium can be saved, which is efficient. For this reason, the layout data of the large-scale integrated circuit is stored as data defining the shape and hierarchical structure of the basic elements of a figure having a hierarchical structure.

  FIG. 4 is an explanatory diagram illustrating a hierarchical structure in the layout data. In the example of FIG. 4, the memory 2, the input / output interface 3, and the logic (logic) circuit 4 are arranged on the semiconductor chip 1 (FIG. 4A). In the memory 2, a peripheral circuit 5 and a memory cell array 6 are arranged. In the memory cell array 6, a large number of memory cells 7 are arranged in a matrix (FIG. 4B). In the memory cell 7, basic elements 10, 11, and 12, which are figures located at the bottom of the hierarchical structure, are arranged (FIG. 4C).

  Next, when graphic correction is not performed (S1a), the layout data is used as it is as mask data for forming a transfer mask. On the other hand, when graphic correction is performed (S1a), the mask data correction device 29 performs image generation (S2) and graphic correction (S3). Image generation (S2) is executed by the image generation device 40, and graphic correction (S3) is executed by the graphic correction device 50.

  In the image generation (S2), first, layout data having a hierarchical structure is input from the layout data storage medium 33 (S21), and further process conditions (that is, conditions relating to the manufacturing process) are input from the outside (S22). Process conditions include, for example, a transfer mask drawing method (electron beam drawing, laser drawing, low reflection mask type, phase shift method type), and exposure apparatus optical parameters (wavelength, numerical aperture, numerical aperture ratio σ, super Resolution type, etc.), conditions relating to resist (pre-baking, PEB, negative / positive, novolac system, chemical amplification system, dry / wet phenomenon, etc.), etching conditions (dry / wet etc.), etc.

  Next, the mesh generation unit 41 sets image generation areas (that is, calculation target areas to be evaluated) in the real space and the Fourier space, and sets a mesh in this image generation area (S23). Specifically, memory areas corresponding to an image generation area in real space and an image generation area in Fourier space are allocated in a storage medium (not shown).

  Next, image calculation is performed by the image calculation unit 42 (S24). In the image calculation (S24), first, a Fourier transform unit 421 (FIG. 2) performs Fourier transform on the basic elements defined in the layout data, thereby obtaining a Fourier image of the basic elements. Next, a Fourier image of the graphic of the entire image generation region is obtained by superimposing the Fourier images of the basic elements in the Fourier space based on the hierarchical structure defined in the layout data by the synthesis unit 422 (S242). .

  Subsequently, the spatial filter unit 423 applies a spatial filter process corresponding to the distortion (distortion) predicted in the manufacturing process to the Fourier image of the entire figure. Strain is predicted based on process conditions. As described in detail in the second embodiment, various strains E1 to E5 are generated at each stage of the manufacturing process. Which of these is reflected can be instructed from the outside by an operator as shown in FIG.

  Spatial filtering itself corresponding to various distortions is a well-known technique. For example, in order to consider the influence of the numerical aperture of the optical system, a circular low-pass filter process may be performed. In addition, in order to consider the direction dependency in the characteristics of the manufacturing apparatus, elliptical filtering may be performed.

  Next, the inverse Fourier transform unit 424 performs an inverse Fourier transform on the Fourier image after the spatial filter processing, thereby obtaining an inverse Fourier image reflecting the distortion. That is, the image calculation unit 42 outputs an inverse Fourier image reflecting the distortion.

  5 and 6 are explanatory diagrams illustrating the operations of the mesh generation unit 41 and the image calculation unit 42 described above. In the example of FIG. 5, the image generation area L is set in the memory 2 illustrated in FIG. The mesh 20 generated by the mesh generation unit 41 is set in the image generation region L in the real space as illustrated in FIG. When the spatial filter processing is not performed, that is, when the distortion is not reflected, an inverse Fourier image output from the image calculation unit 42 is, for example, as illustrated in FIG. FIG. 5B illustrates an inverse Fourier image of the basic element 12 depicted in FIG.

  The basic elements 10, 11, and 12 illustrated in FIG. 4C are described as graphic data in the layout data. In the graphic data, the shapes of the basic elements 10, 11, and 12 are described by a set of coordinate values of their respective corners, for example. On the other hand, the Fourier transform unit 421 generates a Fourier image as image data on a mesh set in the Fourier space as is well known in the art.

  Further, as illustrated in FIG. 5B, the inverse Fourier transform unit 424 generates an inverse Fourier image as image data on the mesh 20 set in the real space. FIG. 5B illustrates the numerical value of the image data for each section of the mesh 20. In the example of FIG. 5B, the numerical value is 0 in the section where the basic element 12 is present, and 1 in the section where the basic element 12 does not exist. A value in the range of 0 to 1 is given depending on the ratio present.

  In the example of FIG. 5B, since distortion is not reflected, the shape of the basic element 12 represented by the inverse Fourier image is the same as the basic element 12 represented by the layout data (FIG. 4C). On the other hand, when a spatial filter process is performed, that is, when distortion is reflected, an inverse Fourier image output from the image calculation unit 42 is, for example, as illustrated in FIG.

  1-3, the inverse Fourier image, which is the image data output by the image calculation unit 42, is converted into a graphic data format similar to the layout data by the graphic conversion unit 43 (S25). The graphic correction unit 50 compares the graphic output by the graphic conversion unit 43 with the graphic specified by the layout data, thereby correcting the graphic specified by the layout data in a direction to suppress distortion and outputting the corrected data as mask data. (S3).

  For example, as a result of the calculation by the image calculation unit 42, an overall process margin can be improved by performing undersizing on a portion that is expected to be greatly finished, and oversizing a portion expected to be finished on the contrary. Figured. FIG. 7 is an explanatory diagram illustrating the shape of the basic element 12b after correction. In the example of FIG. 7, the shape of the basic element 12 when there is no strain is as shown in FIG. 5B, and the shape of the basic element 12a when considering the strain is as shown in FIG. In order to suppress or eliminate, graphic correction is performed as shown in FIG. Note that the configuration and operation of the graphic correction unit 50 are disclosed in detail in Document 1, and are well known techniques, and thus detailed description thereof is omitted.

  The mask generation device 61 generates a transfer mask based on the mask data output by the graphic correction unit 50 (S4). The optical transfer device 62 transfers the transfer mask to the resist formed on the surface of the semiconductor substrate as the material of the semiconductor device (S5). As is well known, the transferred resist is patterned into a transferred pattern shape. The substrate etching apparatus 63 performs a selective etching process on the semiconductor substrate by using the patterned resist as a shield (S6). The CMP apparatus or etch-back apparatus 64 performs CMP (Chemical Mechanical Polishing) or etch-back process on the film deposited on the semiconductor substrate that has been subjected to the selective etching process (S7). Through such various processes, the semiconductor device is completed into a product.

  As described above, in the mask data correction apparatus 29 according to the present embodiment, a Fourier image of the entire figure can be obtained by synthesizing the Fourier images of the basic elements based on the hierarchical structure. Correction of the included mask data is achieved with high efficiency while maintaining accuracy.

Embodiment 2. FIG.
In the present embodiment, various distortions in the manufacturing process reflected in the image calculation unit 42 will be described. As an example, the case where the device to be manufactured is a semiconductor device will be taken up. However, similar distortion can be assumed in the manufacturing process of other devices such as a liquid crystal display device and reflected in the image calculation unit 42. Is possible. A technique for reflecting these distortions in the spatial filter unit 423 and a technique for suppressing distortions by the graphic correction device 50 are well known in the art.

  FIG. 8 is a partially cutaway perspective view showing a known configuration example of the mask generating device 61. The electron beam generated by the LaB6 electron gun 610 includes a first shaping aperture 611, a first shaping lens 612, a first shaping deflector 613, a second shaping lens 614, and a second shaping aperture 615 that constitute the variable shaping lens portion 61a. After passing through the reduction lens 616 and the blanking electrode 617, the light passes through the deflector 618 and the reduction lens 619 constituting the convergence deflection lens portion 61b, and converges to one point on the transfer mask 60. Based on the mask data input to the mask generating device 61, a graphic represented by the mask data is drawn on the transfer mask 60.

  At this time, a drawing distortion E1 (FIG. 3) occurs between the figure represented by the mask data and the figure drawn on the transfer mask 60. The figure drawn on the transfer mask 60 corresponds to an accumulation distribution image of electron beam energy. When a laser beam is used instead of the electron beam, the drawn figure corresponds to an energy accumulation distribution image of the laser beam. The mask data correction device 29 can perform proximity correction using these energy accumulation distribution images, thereby suppressing or eliminating the drawing distortion E1.

  FIG. 9 is an explanatory diagram showing a known configuration example of the optical transfer device 62. In this specification, “light” used for transfer of a transfer mask widely represents electromagnetic waves including ultraviolet rays and the like. The light generated by the lamp 620 includes a mirror 621, a lens 622, a fly eye 623, a lens 622a, a secondary light source plate 625, a lens 622b, a mirror 621a, a lens 622c, a transfer mask 60, a lens 622d, a pupil plane 626, and a lens 622e. By passing through, the surface of the semiconductor substrate (semiconductor wafer) 100 is irradiated. Thereby, the figure of the transfer mask 60 is transferred to the surface of the semiconductor substrate 100. At this time, a transfer distortion E2 (FIG. 3) occurs between the figure drawn on the transfer mask 60 and the transfer image on the surface of the semiconductor substrate 100. The mask data correction device 29 can perform optical proximity correction using an optical image, thereby suppressing or eliminating transfer distortion E2.

  FIG. 10 is a manufacturing process diagram illustrating the manufacturing process of the semiconductor device. In this manufacturing process, first, the semiconductor substrate 100 is prepared (FIG. 10A), and then a resist 101 is applied on the main surface of the semiconductor substrate 100 (FIG. 10B). Thereafter, by using the optical transfer device 62, the figure of the transfer mask is transferred to the resist 101, and a resist pattern 102 is formed by performing development processing (FIG. 10C).

  Next, selective etching is performed on the main surface of the semiconductor substrate 100 by using the resist pattern 102 as a shield (FIG. 10D). In the etching pattern formed at this time, an etching strain E3 (FIG. 3) which is a strain from the transferred image is generated. The mask data correction device 29 can perform proximity correction using a microloading effect image in etching, thereby suppressing or eliminating the etching strain E3.

  Subsequently, by performing isotropic deposition, a film 104 is deposited so as to cover the semiconductor substrate 100 after etching (FIG. 10E). As shown in FIG. 10E, irregularities corresponding to the etching pattern are formed on the surface of the film 104. After that, by performing CMP, the film 104 is polished until the main surface of the semiconductor substrate 100 is exposed (FIG. 10F).

  FIG. 11 is a plan view showing a known configuration example of a CMP apparatus 64 for performing CMP. The semiconductor substrate 100 is placed on the rotating table 640, and the semiconductor substrate 100 further rotates on the table 640. In FIG. 11, the chip formation region 110 of the semiconductor substrate 100 is drawn in a rectangle. A polishing cloth (not shown) is attached above the table 640, and this polishing cloth is pressed against each main surface of the semiconductor substrate 100. Then, through the two rotation modes of the revolution of the table 640 and the rotation of the semiconductor substrate 100, the main surface of the semiconductor substrate 100 is polished by mechanical friction with the polishing cloth and the chemical action of the chemical solution.

  Returning to FIG. 10 (f), if the etching pattern has a density, a polishing strain E 4 along the normal direction of the main surface of the semiconductor substrate 100 is generated in the film 105 having the polishing pattern. The mask data correction device 29 can perform CMP correction using the polished image, thereby suppressing or eliminating the polishing strain E4.

  FIG. 12 is a manufacturing process diagram showing a process of performing an etch-back process instead of CMP after the process of FIG. By this step, an etch-back strain E5 along the normal direction of the main surface of the semiconductor substrate 100 is generated in the etch-back pattern of the film 105. In the mask data correction device 29, correction can be performed using the etch-back image, whereby the etch-back distortion E5 can be suppressed or eliminated.

Embodiment 3 FIG.
FIG. 13 is a block diagram illustrating a preferred internal configuration of the Fourier transform unit 421. FIG. 14 is a flowchart showing a preferred internal flow of the Fourier transform (S241) by the Fourier transform unit 421. A Fourier transform unit 421 shown in FIG. 13 includes a figure dividing unit 4211 and an element figure Fourier transform unit 4212. The figure dividing unit 4211 includes a triangular dividing unit 4213, a quadrangular dividing unit 4214, and a circular dividing unit 4215. Layout data is input to these division units 4213, 4214, and 4215.

  When the Fourier transform (S241) is started, the triangle dividing unit 4213 divides the basic element specified by the layout data into one or a plurality of triangles (S2411). For example, with respect to the basic element 10 shown in FIG. 15, the right triangle 10a is separated from the basic element 10 as shown in FIG. As a result, a right-angled polygon 10b remains in the basic element 10.

  Next, the quadrangular dividing unit 4214 divides the basic element into one or a plurality of quadrangles (S2412). For example, the quadrilaterals 10c and 10d are separated from the right-angled polygon 10b shown in FIG. 16 as shown in FIG. In this way, no matter how complex the basic element is, it can be divided into a set of simple triangles and quadrangles.

  If the basic element defined by the layout data also includes a circle, the circular division unit 4215 further separates the circle portion (S2413). In this way, the basic elements are divided into a collection of element figures that are either triangles, squares, or circles.

  The element graphic Fourier transform unit 4212 obtains a Fourier image of each group of element graphics by individually performing a Fourier transform on each of the group of element graphics formed (S2414). Since all of the triangle, quadrangle, and circle are simple shapes, the element figure Fourier transform unit 4212 can easily and quickly perform the Fourier transform through a simple calculation. The Fourier image for each element graphic obtained by the element graphic Fourier transform unit 4212 is synthesized by the synthesis unit 423 (FIG. 2) into a Fourier image of the graphic of the entire image generation region.

  As described above, in this embodiment, basic elements are divided into groups of element figures that are either triangles, squares, or circles, Fourier transforms are performed for each element figure, and the results are superimposed. As a result, a Fourier image for the graphic of the entire image generation region is obtained. For this reason, no matter how complex the basic elements are, a Fourier transform can be achieved for a figure in the entire image generation region in a short time and without degrading accuracy. Since the Fourier transform does not include approximate calculation, an accurate Fourier image that is not approximate can be obtained.

  In addition to the application to the mask data correction device 29, the Fourier transform unit 421 according to the present embodiment is variously used as a Fourier transform device that can easily and quickly obtain a Fourier image for a complex figure, in addition to the application to the mask data correction device 29. It is also possible to apply to various fields.

Embodiment 4 FIG.
FIG. 18 is a block diagram showing a preferable internal configuration of the element figure Fourier transform unit 4212 and the synthesis unit 422. FIG. 19 is a flowchart showing a preferred internal flow of the process by the element graphic Fourier transform unit 4212 (S2414) and the process by the synthesis unit 422 (S242). The element graphic Fourier transform unit 4212 illustrated in FIG. 18 includes three types of spatial frequency component calculation units 42121, 42122, and 42123 corresponding to the shape of the element graphic. Element graphic data output by the graphic dividing unit 4211 (FIG. 13) is input to the spatial frequency component calculating units 42121, 42122, and 42123. The combining unit 422 includes a first combining unit 4221 and a second combining unit 4222.

  When element graphic data is input to the element graphic Fourier transform unit 4212 (S24141), the three types of spatial frequency component calculation units 42121, 42122, and 42123 respectively perform a Fourier transform on the triangle, quadrangle, and circle in the element graphic. Individually, each Fourier image (that is, a set of spatial frequency components) is obtained (S24142, S24143, S24144). Each spatial frequency component is obtained by executing Fourier integration along the x and y directions in real space.

  The first synthesis unit 4221 superimposes the Fourier images for each element graphic according to the hierarchical structure (S2421). As a result, a Fourier image for the element graphic of the entire image generation region is obtained for each element graphic. The second synthesis unit 4222 superimposes the Fourier images for each element graphic obtained by the first synthesis unit 4221 (S2422). Thereafter, if the processing for the graphic in the entire image generation area is not completed (S2422), the process returns to step S24142. If the processing is completed in reverse (S2423), a Fourier image for the graphic in the entire image generation area is obtained. (S2424).

  In the above procedure, the spatial frequency component obtained by Fourier integration of the element figure once calculated is repeatedly used according to the hierarchical structure. Therefore, the number of times of Fourier integration and the number of operations of trigonometric functions are remarkably reduced, so that the processing capability of Fourier transform is dramatically improved. Furthermore, even large-scale data can be processed in a practical calculation time. In addition, this hierarchical processing does not include approximation and is a strict calculation, so the calculation accuracy is high. The obtained results are confirmed to be exactly the same as when the hierarchical structure is expanded and Fourier integration of each figure is performed, and it is proved that there is no deterioration in calculation accuracy.

  According to the superposition in the real space which is the prior art, all have a long correlation distance (1) electron beam forward scattering or back scattering, (2) optical interference effect, (3) microloading effect, (4) There is a problem that it is difficult to correctly introduce the deformation effect of the polishing cloth. On the other hand, in each embodiment of the present invention, since the superposition is performed in the Fourier space, it is easy to correctly reflect the effect of these long correlation distances.

Embodiment 5 FIG.
When the element graphic Fourier transform unit 4212 according to Embodiments 3 and 4 calculates the spatial frequency component of the element graphic, the element graphic is developed into a bitmap and then numerical integration is performed. Can be adopted. However, taking advantage of the fact that the figure to be subjected to the Fourier transform is a simple triangle, quadrangle, or circle, the primitive function F (x) of the Fourier integral is obtained as shown in the following equation 1, and this is used. It is possible to employ a method of analytically calculating the definite integral. Thereby, the accuracy of the Fourier transform is improved, and at the same time, high-speed calculation is achieved.

Embodiment 6 FIG.
FIG. 20 is a block diagram illustrating a preferable internal configuration of the mesh generation unit 41. FIG. 21 is a flowchart showing a preferred internal flow of mesh generation (S23) by the mesh generation unit 41. When the mesh generation (S23) by the mesh generation unit 41 shown in FIG. 20 is started, the minimum correlation distance calculation unit 411 calculates the minimum correlation distance in the manufacturing process based on the manufacturing process conditions (S231). For example, in the case of an optical system, the minimum correlation distance corresponds to the minimum resolving power R, and R is given by R = λ / 4NA. Here, λ is the exposure wavelength, and NA is the numerical aperture of the projection lens.

Next, the image generation area L (FIG. 5A) is set by the image generation area setting unit 412 (S232). Next, an optimal mesh number is determined by the mesh number optimization unit 413. The number of meshes along each of the two orthogonal directions of the image generation area is the optimum number of meshes so that the mesh width is the largest within the range not exceeding the minimum correlation distance and the number of meshes is a positive integer. It is determined. More preferably, the mesh width is the largest within a range not exceeding the minimum correlation distance, and the mesh number n is determined to be n = 2 ⁱ 3 ^j 5 ^k (i, j, k are 0 or a positive integer). (S234, 235). In the latter case, it is possible to use FFT (Fast Fourier Transform) that can be used in multiples of 2, 3, and 5.

As a special case of the above condition, in order to satisfy n = 2 ⁱ (i is a positive integer), the provisional division number n0 is determined so as to satisfy the following equation (2). Where ceil is a rounding up integer function. Next, when the number of meshes n is determined according to Equation 3, the number of meshes becomes a power of 2, which is also convenient for using the fast Fourier transform (FFT).

  The mesh generation unit 414 generates a mesh according to the number of meshes determined by the mesh number optimization unit 413 (S233).

  As described above, in the present embodiment, since the minimum number of meshes can be set, it is possible to omit useless calculation by generating meshes exceeding the necessary limit from the viewpoint of calculation accuracy, so that the calculation accuracy can be reduced. Processing can be speeded up while maintaining high.

Embodiment 7 FIG.
When calculation is performed using the minimum mesh necessary for calculation accuracy according to the sixth embodiment and the result is displayed, it may feel rough on human vision. In such a case, upsampling may be performed. FIG. 22 is a block diagram showing an internal configuration of the upsampling unit 44 inserted between the spatial filter unit 423 and the inverse Fourier transform unit 424 in FIG. 2 for such a purpose. The upsampling unit 44 includes a mesh adding unit 441 and a new mesh data setting unit 442. FIG. 23 is a flowchart illustrating a processing procedure performed by the upsampling unit 44.

  The mesh adding unit 441 adds a new mesh to the image data input from the spatial filter unit 423 (S261). The new mesh data setting unit 442 sets a value of zero to the image data on the added mesh, and outputs it to the inverse Fourier transform unit 424 together with the image data before the mesh is added (S262).

  FIG. 24 is an explanatory diagram showing processing by the mesh adding unit 441 and the new mesh data setting unit 442. The Fourier image F in the Fourier space (FIG. 24A) is converted into the inverse Fourier image R in the real space by the inverse Fourier transform by the inverse Fourier transform unit 424 (FIG. 24B). On the other hand, when a mesh is added in Fourier space and a value of zero is added to the image data on the added mesh (FIG. 24 (a)), the inverse Fourier image R is shown in FIG. 24 (c). Thus, the image becomes denser than the image of FIG.

  For example, when a new mesh is added to the Fourier space and the number of meshes is increased to 2 × 2 times in 2 dimensions, 2 × in 2 dimensions is obtained when inverse Fourier transform is performed in real space. Upsampled to 2x mesh. The ratio for increasing the number of meshes is generally arbitrary, but it is desirable to set the ratio so that FFT can be used, for example, 2 × 2.

  As described above, in this embodiment, since upsampling is performed in the Fourier space, the obtained interpolation point takes into consideration the entire image, and is smoother and more natural than simple linear interpolation. Insertion is realized. Therefore, there is an advantage that the interpolation accuracy is high.

Embodiment 8 FIG.
Contrary to Embodiment 7, when there are more calculation meshes than display device meshes, the display speed can be increased without degrading the image quality by downsampling. FIG. 25 is a block diagram showing an internal configuration of the downsampling unit 45 inserted between the spatial filter unit 423 and the inverse Fourier transform unit 424 in FIG. 2 for such a purpose. The downsampling unit 45 includes a mesh removing unit 451. FIG. 26 is a flowchart showing a processing procedure by the downsampling unit 45.

  The mesh removal unit 451 removes a part of the mesh from the image data input from the spatial filter unit 423 (S271). The image data from which the mesh has been removed is output to the inverse Fourier transform unit 424.

  FIG. 27 is an explanatory diagram showing processing by the mesh removing unit 451. The Fourier image F in the Fourier space (FIG. 27A) is converted into the inverse Fourier image R in the real space by the inverse Fourier transform by the inverse Fourier transform unit 424 (FIG. 27B). On the other hand, when a part of the mesh is removed in the Fourier space (FIG. 27 (a)), the inverse Fourier image R is larger than the image of FIG. 27 (b) as shown in FIG. 27 (c). The image becomes rough.

  For example, when the high-frequency component around the Fourier image F in the Fourier space is removed and the mesh is two-dimensionally ½ × ½ times, when the inverse Fourier transform is performed to the real space, the two-dimensional Is downsampled to 1/2 × 1/2 times mesh. The ratio for reducing the number of meshes is generally arbitrary, but it is desirable to set the ratio at which FFT can be used, such as 1/2 × 1/2.

  As described above, in the present embodiment, since the downsampling is performed in the Fourier space, the interpolation point to be obtained considers the entire image, and is smoother and more natural than simple linear interpolation. Insertion is realized. In addition, since the display speed of the calculation result is increased, the operability of the system is improved.

Embodiment 9 FIG.
By using the mask data corrected using the mask data correction device 29 of the first to eighth embodiments, an inexpensive and highly accurate transfer mask can be obtained. By manufacturing a semiconductor device such as a semiconductor integrated circuit using this special transfer mask, an inexpensive and highly reliable semiconductor device can be obtained. The same applies not only to the semiconductor device but also to other devices having a pattern structure such as a liquid crystal display device. Since the manufacturing method of these apparatuses has been described in detail with reference to FIGS. 10 and 11 in the second embodiment, further detailed description thereof will be omitted. As shown in FIG. 3, after passing through steps S5 to S7 illustrated in FIG. 10 or FIG. A device having a pattern structure such as is completed.

Embodiment 10 FIG.
The upsampling unit 44 shown in the seventh embodiment can constitute an upsampling device independent of the mask data correction device 29 by adding a Fourier transform unit and an inverse Fourier transform unit. Similarly, the downsampling unit 45 shown in the eighth embodiment can constitute a downsampling device independent of the mask data correction device 29 by adding a Fourier transform unit and an inverse Fourier transform unit. In the present embodiment, an upsampling device and a downsampling device configured as described above will be described.

  FIG. 28 is a block diagram illustrating a configuration example of the upsampling apparatus 80 according to the present embodiment, and FIG. 29 is a flowchart illustrating a procedure of the processing (S8). The upsampling device 80 first receives discrete data defined in a one-dimensional or multi-dimensional space (S81). Then, the Fourier transform unit 81 transforms the discrete data into a set of frequency components by performing Fourier transform on the received discrete data (S82). The mesh adding unit 82 adds a new mesh in the Fourier space as a set of data on the mesh set in the Fourier space of the same dimension as the one-dimensional or plural dimensions as described above (S83). .

  The new mesh data setting unit 83 sets a value of zero to the data on the added mesh, and outputs it together with the data on the mesh before being added (S84). The inverse Fourier transform unit 84 obtains upsampling data by performing inverse Fourier transform on the data output by the new mesh data setting unit 83 (S85), and outputs the obtained upsampling data (S86).

  In the upsampling device 80, upsampling is performed in Fourier space, and therefore, interpolation is performed that reflects the entire set of discrete data. For this reason, smooth and natural data after upsampling that cannot be obtained by simple linear interpolation can be obtained.

  FIG. 30 is a block diagram illustrating a configuration example of the downsampling apparatus 90 according to the present embodiment, and FIG. 31 is a flowchart illustrating a procedure of the processing (S9). The down-sampling device 90 first receives discrete data defined in a one-dimensional or multi-dimensional space (S81). Then, the Fourier transform unit 81 transforms the discrete data into a set of frequency components by performing Fourier transform on the received discrete data (S82).

  The mesh removal unit 85 removes a part of the mesh in the Fourier space as a collection of data on the mesh set in the Fourier space of the same dimension as the one-dimensional or plural dimensions as described above. Output (S87). The inverse Fourier transform unit 84 obtains down-sampling data by performing inverse Fourier transform on the data output from the mesh removal unit 85 (S85), and outputs the obtained down-sampling data (S88).

  In the downsampling device 90, downsampling is performed in the Fourier space, so that interpolation that reflects the entire set of discrete data is performed. For this reason, although the number of samplings is reduced, smooth and natural data after downsampling processing that cannot be obtained by simple linear interpolation or the like can be obtained.

  10, 11, 12 Basic element, 10a, 10c, 10d Element graphic, 20 mesh, 29 Mask data correction device, 41 Mesh generation unit, 411 Minimum correlation distance calculation unit, 413 Mesh number optimization unit, 421 Graphic division unit, 4212 Element graphic Fourier transform unit, 422 synthesis unit, 423 spatial filter unit, 43 graphic conversion unit, 451 mesh removal unit, 50 graphic correction device (graphic correction unit), 60 transfer mask, 80 upsampling device, 81, 421 Fourier transform Part, 82,441 mesh adding part, 83,442 new mesh data setting part, 84,424 inverse Fourier transform part, 90 downsampling device, 100 semiconductor substrate (material), 102 resist pattern, 104 film, E1 drawing distortion, E2 Transfer distortion, E3 etching See, E4 polishing strain, E5 etched back strain, F Fourier image, F (x) primitive, L image generating region, R inverse Fourier image.

Claims (2)

An upsampling device for performing upsampling on discrete data,
A Fourier transform unit that transforms the discrete data into a set of frequency components by performing a Fourier transform on the discrete data defined in a one-dimensional or multi-dimensional space;
A set of the frequency components as data on a mesh set in the one-dimensional or multi-dimensional Fourier space, and a mesh adding unit for adding a new mesh in the Fourier space;
A new mesh data setting unit that sets a value of zero to the data on the added mesh and outputs the data together with the data on the mesh before being added;
An upsampling device comprising: an inverse Fourier transform unit that performs inverse Fourier transform on data output from the new mesh data setting unit. A downsampling device for downsampling discrete data,
A Fourier transform unit that transforms the discrete data into a set of frequency components by performing a Fourier transform on the discrete data defined in a one-dimensional or multi-dimensional space;
A set of frequency components as data on a mesh set in the one-dimensional or multi-dimensional Fourier space, and a mesh removing unit that outputs a part of the mesh after removing the mesh in the Fourier space;
A downsampling device comprising: an inverse Fourier transform unit that performs inverse Fourier transform on data output from the mesh removal unit.

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