JP2011019136A - Solid-state imaging apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve speed-up and lower power consumption of segmentation operation while facilitating control of full pixel read-out operation.SOLUTION: A solid-state imaging apparatus 500 includes: a plurality of AD conversion circuits 200 provided one for each column so as to convert analog pixel signals, read out from pixels arranged in the corresponding column, into digital signals; a plurality of delay flip-flops 202 provided one for each column so as to hold the digital signals converted by the AD conversion circuits 200 arranged in the corresponding column; each bypass signal line 601; each buffer 600 that outputs the digital signal, held in one delay flip-flop 202 other than the delay flip-flop 202 at the final stage, to the bypass signal line 601; and each output selector 603 that outputs either the digital signal held by the delay flip-flop 202 at the final stage or the digital signal of the bypass signal line 601.

Description

  The present invention relates to a solid-state imaging device, and more particularly, to a solid-state imaging device including a plurality of pixels arranged in a matrix and a conversion circuit that converts analog pixel signals read from the plurality of pixels into digital signals.

  A plurality of unit components (for example, pixels) that are arranged in an array form (matrix form) and that are sensitive to changes in physical quantities such as electromagnetic waves input from outside such as light and radiation, or pressure (contact, etc.) In addition, semiconductor devices that detect physical quantity distribution are used in various fields.

  As an example, in the field of video equipment, a CCD (Charge Coupled Device) type or a MOS (Metal Oxide Semiconductor) type (CMOS (Complementary Metal-) that detects a change in light (an example of an electromagnetic wave), which is an example of a physical quantity. A solid-state imaging device using an imaging device (imaging device) (including an oxide semiconductor type) is also used.

  This MOS type image pickup device (MOS image sensor) includes a floating diffusion amplifier which is an amplifying device for each pixel. In reading pixel signals, a so-called column-parallel output type or column type is often used as an example of address control. In this method, one row in the pixel array unit is selected, the selected one row is accessed simultaneously, and the pixel signals from the pixel array unit are simultaneously accessed in units of rows, that is, all pixels in one row are simultaneously parallel. Is a method of reading out.

  In addition, in a solid-state imaging device, there is a method in which an analog pixel signal read from the pixel array unit is converted into digital data by an analog-digital converter (AD converter: Analog Digital Converter) and then output to the outside. Sometimes taken.

  The same applies to the column-parallel output type solid-state imaging device, and various signal output units have been devised. As an example of the most advanced form, a method of providing an AD conversion device for each column and extracting pixel information of digital data to the outside is considered.

  FIG. 10 is a block diagram showing a configuration of a conventional MOS solid-state imaging device (MOS image sensor).

  This solid-state imaging device 100 shown in FIG. 10 includes a pixel unit 102, a plurality of column signal lines 103, a CDS processing unit 104, an AD conversion unit 105, a digital memory 106, an output unit 107, and a vertical drive unit 108. A vertical decoder 109 and a control circuit 110.

  The pixel unit 102 includes a plurality of pixels including a light receiving element 101 that are arranged in an array (two-dimensional matrix) and output a voltage signal corresponding to the amount of incident light. The plurality of pixels output voltage signals to the plurality of column signal lines 103.

  A CDS (Correlated Double Sampling) processing unit 104 performs CDS processing on the voltage signals of the plurality of column signal lines 103.

  An AD converter (ADC: Analog Digital Converter) 105 converts an analog signal subjected to CDS processing into a digital signal.

  The digital signal converted by the AD conversion unit 105 is output to the digital memory 106. The output terminal of the digital memory 106 is connected to the output unit 107.

  On the other hand, the light receiving elements 101 arranged in an array in the pixel unit 102 are driven by the vertical driving unit 108. The vertical drive unit 108 is controlled by a vertical decoder 109.

  An external control signal 111 is input to the control circuit 110. Further, the control circuit 110 controls the vertical decoder 109, the digital memory 106, the CDS processing unit 104, and the AD conversion unit 105.

  FIG. 11 is a circuit diagram showing a detailed configuration of the conventional digital memory 106 and the output unit 107.

  As illustrated in FIG. 11, the AD conversion unit 105 includes a plurality of AD conversion circuits 200. The digital memory 106 includes a plurality of selectors 201 and a plurality of delay flip-flops 202. The output unit 107 includes a plurality of output circuits 203.

  In the case of this conventional example, the digital signal ADOUT output from the AD conversion circuit 200 is 12 bits. Note that the number of bits of the digital signal ADOUT may be, for example, 10 bits, 16 bits, or the like as necessary.

  The digital memory 106 is connected with the same number of AD conversion circuits 200 as the number of pixels (n) in the horizontal direction of the light receiving elements 101 arranged in the pixel unit 102.

  Further, in the digital memory 106, the selector 201 and the delay flip-flop 202 are arranged in the number of bits of the digital signal ADOUT of the n columns × AD conversion unit 105 (12 in this conventional example). In the following, it is assumed that there are 1 to n columns from the left side of FIG. 11, and 0 to 11 bits from the upper side of FIG.

  The selector 201 is a two-input selector. One bit of the digital signal ADOUT output from the AD conversion circuit 200 of the corresponding column is input to the first input terminal of each selector 201. A latch control signal LATSW is input to the control terminal of each selector 201. The output signal of each selector 201 is input to the delay flip-flop 202 in the corresponding column.

  Each delay flip-flop 202 receives a clock signal DMCLK. Further, the output signal of the delay flip-flop 202 of the same bit in the adjacent column (previous column) is input to the second input terminal of each selector 201.

  As described above, the output signal of the delay flip-flop 202 in the first column to which the output signal of the selector 201 in the first column is input is input to the selector 201 in the second column. In this way, the n delay flip-flops 202 of each bit are sequentially connected serially via the selector 201. A plurality of sets of delay flip-flops 202 connected in a serial chain are arranged in parallel by the number of output bits (12 bits) of the AD conversion circuit 200.

  The 12 delay flip-flops 202 in the nth column connected to the AD conversion circuit 200 in the nth column output signals to the output unit 107 in parallel. The output unit 107 includes the same number (12) of output circuits 203 as the number of output bits of the AD conversion unit 105. Each output circuit 203 receives the output signal of the delay flip-flop 202 in the nth column of each bit.

  Next, the operation of the conventional solid-state imaging device 100 will be described with reference to FIG. FIG. 12 is a timing chart showing the operation of the solid-state imaging device 100.

  DF1 [0:11] shown in FIG. 12 is data held in 12 delay flip-flops 202 in the first column. This DF1 [0:11] is a set of 12 bits. Similarly, DF2 [0:11] is data held in 12 delay flip-flops 202 in the second column, and ... DFn [0:11] is 12 delays in the nth column. Data held in the flip-flop 202. DOUT [0:11] is an output signal of the output unit 107.

  The data D1 to Dn are data obtained by digitally converting analog signal amounts of the light receiving elements 101 arranged in the 1st to nth columns, respectively.

  First, the solid-state imaging device 100 controls the vertical decoder 109 according to the external control signal 111. Thereby, the vertical drive unit 108 drives the light receiving element 101 arranged in the pixel unit 102. The light receiving element 101 converts a physical quantity (light or electromagnetic wave) sensed by the light receiving element 101 itself into a potential (analog signal). This analog signal is output to the column signal line 103. Noise is removed from the output analog signal by the CDS processing unit 104 and then input to the AD conversion unit 105. The AD conversion unit 105 converts the analog signal output from the CDS processing unit 104 into a digital signal, and outputs the converted digital signal to the digital memory 106.

  The digital signal ADOUT output from the AD conversion unit 105 is input to the plurality of selectors 201. When the latch control signal LATSW is at the H level, the selector 201 outputs the digital signal ADOUT from the AD conversion unit 105. When the latch control signal LATSW is at L level, the selector 201 outputs data output from the delay flip-flop 202 at the previous stage of the horizontal serial chain connected to the input terminal.

  Here, during the period t00 to t02 shown in FIG. 12, the latch control signal LATSW becomes H level, and the clock signal DMCLK rises to H level at time t01 included in the period t00 to t02. As a result, the digital signal ADOUT output from all the AD conversion circuits 200 arranged in the AD conversion unit 105 is latched by the plurality of delay flip-flops 202. Thereafter, at time t02, the latch control signal LATSW becomes L level, and the signal output from the selector 201 is switched.

  Thereafter, each time the clock signal DMCLK rises to the H level, the delay flip-flop 202 latches the input data of the delay flip-flop 202 in the preceding row. For example, the data D2 held in the delay flip-flop 202 in the second column before the clock signal is input is latched in the delay flip-flop 202 in the third column as the clock signal is input. At the same time, the delay flip-flop 202 in the second column itself holds the output data D1 of the AD conversion circuit 200 in the first column.

  Thus, every time the clock signal DMCLK rises to the H level, the scan shift operation is performed. As a result, the output unit 107 sequentially outputs data Dn of the AD conversion circuit 200 in the n-th column to data D1 of the AD conversion circuit 200 in the first column.

  For example, Patent Document 1 discloses a configuration similar to the solid-state imaging device 100.

JP 2008-172609 A

  However, the above-described MOS solid-state imaging device has the following problems.

  FIG. 13 is a diagram illustrating an image of a general cutout operation.

  Here, the cut-out operation is an operation that uses only data of a necessary region, instead of using data of all the light receiving elements 101 among the plurality of light receiving elements 101 arranged in the pixel unit 102.

  For example, at the time of the cutout operation, only data of the light receiving element 101 arranged in the cutout area 400 shown in FIG. 13 is used. This cut-out operation can realize reduction in power consumption by not operating unnecessary portions, and improvement in operation speed (increase in frame rate) by operating only necessary areas.

  However, when the above-described conventional solid-state imaging device 100 performs this clipping operation, when the digital memory 106 transfers the data of the delay flip-flop 202 in the horizontal direction, the digital memory 106 includes the output region 401 including the clipping region 400. It is necessary to transfer all the minute data. As illustrated in FIG. 13, the output area 401 includes an unnecessary area located on the right side of the cutout area 400. Therefore, the transfer time required for transferring the data in this area is wasted. Accordingly, the speed of data transfer is hindered. In addition, much power is consumed accordingly.

  Further, as a method for speeding up the horizontal transfer of digital data, for example, as in Patent Document 1, for example, all columns of a digital memory (described as a data holding unit in Patent Document 1) are a plurality of blocks each including a plurality of columns. There is a way to divide. Specifically, a configuration can be adopted in which one output driver is provided in the subsequent stage of the digital memory of each block, or the output driver is provided only in the subsequent stage of any one of the digital memories in the plurality of blocks. The structure which provides one can be taken.

  By dividing the digital memory in this way, it is possible to reduce the power consumption of the cutting operation by operating only the part necessary for the cutting operation. However, in the case of the all-pixel reading operation using the entire data of the digital memory, an operation across blocks is required, and another problem that the control becomes complicated arises.

  An object of the present invention is to provide a solid-state imaging device capable of achieving a high speed and low power consumption of a cut-out operation and easily controlling an all-pixel readout operation. To do.

  In order to achieve the above object, a solid-state imaging device according to the present invention is a solid-state imaging device, a plurality of pixels arranged in a matrix, and a reading unit that reads an analog pixel signal from the plurality of pixels, A plurality of conversion circuits for converting analog pixel signals read from the pixels arranged in the corresponding column into digital signals, one for each column, and one for each column. A plurality of data holding units that hold digital signals converted by the conversion circuit, the plurality of data holding units are connected in series, and each data holding unit receives a digital signal to be held in a subsequent stage The digital signal held by the data holding unit in the previous stage is transferred to the data holding unit, and the solid-state imaging device further includes a bypass signal line and a final one of the plurality of data holding units. Connected to one data holding unit other than the data holding unit, a buffer for outputting a digital signal held in the one data holding unit to the bypass signal line, and a digital held by the data holding unit in the final stage A first selector that selects one of the signal and the digital signal of the bypass signal line, outputs the selected digital signal, and an output circuit that outputs the digital signal output by the first selector;

  According to this configuration, in the solid-state imaging device according to the present invention, when the first selector selects the digital signal of the bypass signal line, only the data of the pixels included in the necessary cut-out area is stored in the plurality of data holding units. Can be transferred. Thereby, the solid-state imaging device according to the present invention can realize a high-speed cutting operation and low power consumption.

  Furthermore, in the solid-state imaging device according to the present invention, the first selector selects all the pixels using the data holding units connected in series for the number of columns by selecting the digital signal held in the data holding unit at the final stage. Can be transferred. Therefore, the solid-state imaging device according to the present invention can realize the all-pixel reading operation with easier control than in the case where all the columns of the digital memory are divided into a plurality of blocks each including a plurality of columns.

  The solid-state imaging device includes: a first operation mode for outputting a digital signal corresponding to pixel signals of all pixels of the plurality of pixels; and a plurality of first pixel pixels that are a part of the plurality of pixels. A second operation mode for outputting only a digital signal corresponding to the signal, and the solid-state imaging device is further held in the first selector by the data holding unit at the final stage in the first operation mode. There may be provided a control circuit for selecting a digital signal and causing the first selector to select the digital signal of the bypass signal line in the second operation mode.

  The solid-state imaging device is connected to each of a plurality of first data holding units included in a plurality of data holding units other than the final stage data holding unit, and held in the corresponding first data holding unit. A plurality of buffers including the buffer for outputting the digital signal to be output to the bypass signal line may be provided.

  According to this configuration, the solid-state imaging device according to the present invention can select an arbitrary cutout position and cutout size from a plurality of cutout positions and a plurality of cutout sizes.

  Further, the plurality of buffers are tristate buffers, and the control circuit further includes only one of the plurality of buffers corresponding to the first data holding unit in the second operation mode. The digital signal held in the output state may be output to the bypass signal line, and all other buffers may be in a high impedance state.

  Further, the plurality of buffers are connected corresponding to all of the data holding units other than the data holding unit in the final stage, and output the digital signals held in the corresponding data holding units to the bypass signal line. May be.

  According to this configuration, the solid-state imaging device according to the present invention can arbitrarily change the cutout position and the cutout size.

  The control circuit designates one of the first operation mode and the second operation mode, and designates one of the plurality of buffers in the second operation mode. The solid-state imaging device further includes a decoder circuit that converts the first signal into a second signal having the same number of bits as the number of columns, and the decoder The circuit sets only one of the plurality of bits of the second signal to the first logic and sets all other bits to the second logic, and each bit of the second signal is one of the plurality of buffers. Or corresponding to the first selector, and each buffer is in the output state when the corresponding bit of the second signal is the first logic, and the corresponding bit of the second signal is the second logic. Place When the corresponding bit of the second signal is the first logic, the first selector selects the digital signal held by the data holding unit at the final stage, and the corresponding When the bit of the second signal is the second logic, the digital signal of the bypass signal line may be selected.

  According to this configuration, the control circuit can perform the designation of the first operation mode and the second operation mode and the designation of the cut-out position using the first signal, so that the number of wirings can be reduced. Furthermore, the solid-state imaging device can reduce power consumption by setting all the buffers to a high impedance state in the first operation mode.

  The bypass signal line may be supplied with a signal only from the buffer.

  According to this configuration, the solid-state imaging device according to the present invention can suppress an increase in circuit compared to a case where the cutout position is variable.

  The buffer is a tri-state buffer, and the control circuit further places the buffer in a high impedance state during the first operation mode, and connects the buffer to the buffer during the second operation mode. The digital signal held in the first data holding unit may be in an output state in which it is output to the bypass signal line.

  According to this configuration, since the solid-state imaging device according to the present invention can be controlled so that the buffer does not operate in the first operation mode, power consumption can be reduced.

  The solid-state imaging device may further include an operation stop unit that stops the operation of the data holding unit in a column that does not include the first pixel in the second operation mode.

  According to this configuration, the solid-state imaging device according to the present invention can stop unnecessary data holding units in the second operation mode, so that power consumption can be reduced.

  In addition, each time a clock signal is input, each data holding unit transfers a digital signal to be held to a subsequent data holding unit, and receives the digital signal held by the previous data holding unit, and the operation stop unit In the second operation mode, supply of the clock signal to the data holding unit in a column not including the first pixel may be stopped.

  The length of the bypass signal line may be a length from the position of the buffer to the position of the output circuit.

  According to this configuration, the solid-state imaging device according to the present invention can optimize the transfer time of the bypass signal line in the horizontal direction depending on the cut-out position, so that higher speed operation can be realized.

  The horizontal length of the bypass signal line may be ½ or less of the horizontal length of the area where the plurality of data holding units are arranged.

Each of the data holding units is a flip-flop, and the solid-state imaging device further includes:
One is provided for each column, and one of the digital signals converted by the conversion circuit in the corresponding column and the digital signal held in the previous data holding unit is selected, and the selected digital signal is selected in the corresponding column. A plurality of second selectors that output to the data holding unit may be provided.

  Note that the present invention can be realized not only as such a solid-state imaging device but also as a control method of a solid-state imaging device that controls such a solid-state imaging device.

  Furthermore, the present invention can be realized as a semiconductor integrated circuit (LSI) that realizes part or all of the functions of such a solid-state imaging device, or can be realized as a camera including such a solid-state imaging device.

  As described above, the present invention can provide a solid-state imaging device that can speed up the cut-out operation and reduce power consumption and can easily control the all-pixel readout operation.

1 is a block diagram of a solid-state imaging device according to Embodiment 1 of the present invention. 1 is a circuit diagram of a digital memory and an output unit according to Embodiment 1 of the present invention. FIG. 2 is a circuit diagram of a horizontal decoder according to the first embodiment of the present invention. 3 is a timing chart of the solid-state imaging device according to Embodiment 1 of the present invention. It is a figure which shows the image of the cutting-out operation | movement by the solid-state imaging device which concerns on Embodiment 1 of this invention. It is a block diagram of the solid-state imaging device concerning Embodiment 2 of the present invention. FIG. 6 is a circuit diagram of a digital memory and an output unit according to Embodiment 2 of the present invention. It is a timing chart of the solid-state imaging device concerning Embodiment 2 of the present invention. It is a circuit diagram of a digital memory and an output unit according to the third embodiment of the present invention. It is a block diagram of the conventional solid-state imaging device. It is the circuit diagram of the conventional digital memory and an output part. It is a timing chart of the conventional solid-state imaging device. It is a figure which shows the image of the conventional cut-out operation | movement.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the following, a case where a MOS solid-state imaging device, which is an example of an XY address type solid-state imaging device, is used will be described as an example. The MOS solid-state imaging device will be described on the assumption that all pixels are composed of NMOS.

  However, this is an example, and the target device is not limited to the MOS type solid-state imaging device. For example, all of the semiconductor devices for physical quantity distribution detection including a plurality of unit components that are sensitive to electromagnetic waves input from the outside, such as light or radiation, arranged in a line or matrix. All the embodiments described later can be similarly applied.

(Embodiment 1)
Which of the output data of the scan shift circuit connected in the number of stages corresponding to the total number of columns and the data of the bypass signal line used in the cut-out operation is output by the solid-state imaging device according to the first embodiment of the present invention. An output selector for switching between. As a result, the solid-state imaging device according to the present invention can realize a high-speed cutting operation and low power consumption, and can easily control the all-pixel reading operation.

  First, the configuration of the solid-state imaging device 500 according to Embodiment 1 of the present invention will be described.

  FIG. 1 is a block diagram showing a configuration of a solid-state imaging apparatus 500 according to Embodiment 1 of the present invention. In addition, the same code | symbol is attached | subjected to the element similar to FIG.

  A solid-state imaging device 500 illustrated in FIG. 1 includes a pixel unit 102, a plurality of column signal lines 103, a CDS processing unit 104, an AD conversion unit 105, a vertical driving unit 108, a vertical decoder 109, and a digital memory 501. , A horizontal decoder 502, a control circuit 503, and an output unit 504.

  The solid-state imaging device 500 includes a first operation mode in which an all-pixel reading operation for outputting digital signals corresponding to pixel signals of all pixels of a plurality of pixels and a plurality of first ones that are a part of the plurality of pixels. A second operation mode for performing a cut-out operation for outputting only a digital signal corresponding to the pixel signal of the pixel.

  The pixel unit 102 is arranged in a matrix (two-dimensional matrix) and includes a plurality of pixels that output an analog voltage signal (pixel signal) corresponding to the amount of incident light. Each pixel includes a light receiving element 101 that converts light into an electrical signal. In the following, it is assumed that the number of columns (the number of pixels in the horizontal direction) of the light receiving elements 101 arranged in the pixel unit 102 is n columns.

  Each column signal line 103 is provided for each column, and pixel signals are output from a plurality of pixels arranged in the corresponding column.

  A CDS (Correlated Double Sampling) processing unit 104 generates n analog signals by performing CDS processing on each of the pixel signals on the n column signal lines 103.

  An AD conversion unit (ADC: Analog Digital Converter) 105 converts n analog signals subjected to CDS processing by the CDS processing unit 104 into digital signals ADOUT, respectively, and converts the converted n digital signals ADOUT into the digital memory 501. Output.

  The digital memory 501 holds the n digital signals ADOUT output from the AD conversion unit 105 and outputs the held n digital signals ADOUT to the sequential output unit 504. In other words, the digital memory 501 is a shift register that acquires n digital signals ADOUT in parallel and outputs the output n digital signals ADOUT in series.

  The output unit 504 outputs a digital signal output from the digital memory 501 to the outside of the solid-state imaging device 500.

  The horizontal decoder 502 controls the digital memory 501. Specifically, the horizontal decoder 502 controls switching between the all-pixel reading operation and the cutout operation, and also controls the cutout position during the cutout operation.

  The vertical driving unit 108 corresponds to a reading unit of the present invention, and reads pixel signals from the plurality of pixels by driving the plurality of pixels. The vertical decoder 109 controls the vertical driving unit 108.

  An external control signal 111 is input to the control circuit 503 from the outside. The external control signal 111 includes a signal that designates an all-pixel reading operation or a cutout operation, and a signal that designates a cutout position and a cutout range at the time of the cutout operation.

  The control circuit 503 controls the vertical decoder 109, the digital memory 501, the horizontal decoder 502, the CDS processing unit 104, and the AD conversion unit 105 according to the external control signal 111.

  FIG. 2 is a circuit diagram illustrating detailed configurations of the AD conversion unit 105, the digital memory 501, and the output unit 504.

  As illustrated in FIG. 2, the AD conversion unit 105 includes n AD conversion circuits 200. Each AD conversion circuit 200 corresponds to each column of the pixel unit 102 and converts the pixel signal of the pixel arranged in the corresponding column into a digital signal ADOUT. The AD conversion circuit 200 corresponds to the conversion circuit of the present invention.

  Each digital signal ADOUT is 12 bits in the first embodiment of the present invention. Note that the number of bits of the digital signal ADOUT is not limited to 12 bits, and may be, for example, 10 bits or 16 bits as necessary.

  Further, the AD conversion unit 105 outputs n digital signals ADOUT [0:11] to the digital memory 501.

  The digital memory 501 includes n columns × the number of bits of the digital signal ADOUT × (12 in the case of the first embodiment of the present invention) selectors 201, n columns × x bits of delay flip-flops 202, It includes n−1 columns × x bits buffers 600 and x bypass signal lines 601.

  Further, one selector 201 and one delay flip-flop 202 are arranged corresponding to each combination of columns and bits in n columns × x bits.

  Similarly, one buffer 600 is arranged corresponding to each combination of columns and bits in n−1 columns × x bits. In other words, the plurality of buffers 600 are connected to each of the delay flip-flops 202 other than the delay flip-flop 202 in the final stage (nth column). In addition, one bypass signal line 601 is arranged corresponding to each bit of x bits.

  In the following, it is assumed that there are 1 to n columns from the left side of FIG. 2, and 0 to 11 bits from the upper side of FIG.

  Further, the latch control signal LATSW, the clock signal DMCLK, and the bypass control signal BPEN [1: n] are input to the digital memory 501.

  The latch control signal LATSW and the clock signal DMCLK are generated by the control circuit 503. Further, the bypass control signal BPEN [1: n] is generated by the horizontal decoder 502. The bypass control signal BPEN [1: n] is an n-bit signal.

  The delay flip-flop 202 corresponds to the data holding unit of the present invention. The delay flip-flop 202 holds the digital signal ADOUT converted by the AD conversion circuit 200 in the corresponding column. Further, n delay flip-flops 202 of each bit are connected in series. Each time the delay flip-flop 202 receives the clock signal DMCLK, the delay flip-flop 202 transfers the digital signal held to the delay flip-flop 202 in the subsequent stage and also holds the digital signal held in the delay flip-flop 202 in the previous stage. Receive.

  Each selector 201 is a two-input selector. This selector 201 corresponds to the second selector of the present invention, and selects one of the digital signal ADOUT converted by the AD conversion circuit 200 in the corresponding column and the digital signal held in the preceding delay flip-flop 202. The selected signal is output to the delay flip-flop 202 of the corresponding column.

  Specifically, a 1-bit signal corresponding to the corresponding bit among the digital signals ADOUT [0:11] output from the AD conversion circuit 200 in the corresponding column is input to the first input terminal of each selector 201. Is done. Further, the output signal of the delay flip-flop 202 corresponding to the previous column is input to the second input terminal of each selector 201. A latch control signal LATSW is input to the control terminal of each selector 201. Also, the output terminal of each selector 201 is connected to the input terminal of the corresponding column and bit delay flip-flop 202.

  Each selector 201 outputs the digital signal ADOUT output from the AD conversion circuit 200 and input to the first input terminal when the latch control signal LATSW is at the H (high) level. The selector 201 also outputs a signal output from the preceding delay flip-flop 202 in the horizontal serial chain connected to the second input terminal when the latch control signal LATSW is at L (low) level. To do.

  The clock signal DMCLK is input to the clock terminal of each delay flip-flop 202.

  As described above, the output signal of the delay flip-flop 202 in the first column to which the output signal of the selector 201 in the first column is input is input to the selector 201 in the second column. In this manner, the n delay flip-flops 202 of each bit are sequentially connected serially via the selector 201. A set of n delay flip-flops 202 of each bit connected in a serial chain is arranged in parallel in x bits (12 bits).

  Further, the 12 delay flip-flops 202 in the n-th column output the output signals to the output unit 504 in parallel.

  The buffer 600 outputs the digital signal held in the corresponding delay flip-flop 202 to the bypass signal line 601.

  Specifically, the input terminal of each buffer 600 is connected to the output terminal of the corresponding column and bit delay flip-flop 202. Each buffer 600 is a tri-state buffer, and according to the bypass control signal BPEN of the corresponding column, an output state (a state in which an H level or L level signal is output) and a high impedance state (a state in which no signal is output) And can be switched. For example, the bypass control signal BPEN [1] is connected to the buffer 600 in the first column. Similarly, the bypass control signal BPEN [k] is connected to the k columns of buffers 600 (k = 1 to n−1).

  The output terminals of the (n−1) buffers 600 for each bit are commonly connected to one bypass signal line 601 for the corresponding bit.

  The output unit 504 includes x output circuits 602, x output selectors 603, and an inverter 604.

  The output selector 603 corresponds to the first selector of the present invention. The output selector 603 selects one of the digital signal held by the final-stage delay flip-flop 202 and the digital signal of the bypass signal line 601 and outputs the selected digital signal.

  That is, the two input terminals of each output selector 603 have an output terminal of the delay flip-flop 202 at the final stage (n-th column) of the scan chain of the corresponding bit and a bypass signal line 601 of the corresponding bit. Connected. The output terminal of the output selector 603 is connected to the input terminal of the output circuit 602 for the corresponding bit. Further, the bypass control signal BPEN [n] is input to the control terminal of each output selector 603 via the inverter 604.

  Each output selector 603 outputs the output data of the delay flip-flop 202 of the corresponding bit in the nth column when the bypass control signal BPEN [n] is at the H level, and the bypass control signal BPEN [n] In the case of L level, the data of the bypass signal line 601 of the corresponding bit is output.

  The output circuit 602 outputs the digital signal output from the corresponding bit output selector 603 to the outside.

  Hereinafter, the configuration of the horizontal decoder 502 will be described.

  FIG. 3 is a circuit diagram showing a detailed configuration of the horizontal decoder 502.

  The horizontal decoder 502 converts the horizontal address signal HAD [0: y] into a bypass control signal BPEN [1: n]. In other words, the horizontal decoder 502 generates the bypass control signal BPEN [1: n] by decoding the horizontal address signal HAD [0: y]. Here, y <n.

  Further, the horizontal address signal HAD [0: y] is generated by the control circuit 503. The horizontal address signal HAD [0: y] designates one of the all-pixel reading operation and the cutout operation, and designates one of the plurality of columns of buffers 600 in the cutout operation (the cutout position is set). Signal).

  Each bit of the bypass control signal BPEN [1: n] corresponds to one of the plurality of columns of buffers 600 or the output selector 603 as described above. Specifically, each bit of the bypass control signal BPEN [1: n−1] corresponds to the x buffers 600 in the 1st to (n−1) th column, and the bypass control signal BPEN [n] is an output selector. Corresponding to 603.

  As described above, when the bypass control signal BPEN [n] becomes H level, the data of all columns is transferred. This is equivalent to the selection of the nth column as the cutout position. That is, each bit of the bypass control signal BPEN [1: n] corresponds to each column of the pixel unit 102.

  The horizontal decoder 502 includes y inverters 701, 3 × n four-input NAND elements 702, and n three-input NOR elements 703.

  The horizontal address signal HAD [0: y] is prepared in the number necessary for uniquely selecting the number of pixels in the horizontal direction. Here, it is assumed that the horizontal address signal HAD is 12 bits and y = 11.

  The inverter 701 generates an inverted horizontal address signal obtained by inverting the logic of the corresponding bit signal of the horizontal address signal HAD [0:11].

  Three NAND elements 702 and one NOR element 703 are arranged corresponding to each column.

  Twelve input terminals of the three 4-input NAND elements 702 in each column correspond to each bit of the 12-bit horizontal address signal HAD [0:11], and the horizontal address signal HAD and inverted horizontal address of the corresponding bits. Either one of the signals is input. The combination of the horizontal address signal HAD and the inverted horizontal address signal input to the 12 input terminals is different for each of the three 4-input NAND elements 702 in each column.

  The input terminals of each NOR element 703 are connected to the output terminals of three NAND elements 702 in the corresponding column. Each NOR element 703 generates a bypass control signal BPEN [k] (k = 1 to n) of the corresponding column.

  With the above configuration, the horizontal decoder 502 sets only one bit out of n bits of the bypass control signal BPEN [1: n] to H level according to the logic of the horizontal address signal HAD [0:11] All bits are set to L level.

  Next, the operation of the solid-state imaging device 500 according to Embodiment 1 of the present invention will be described using FIG.

  First, the cut-out operation of the solid-state imaging device 500 will be described.

  FIG. 4 is a timing chart showing the cut-out operation of the solid-state imaging device 500.

  DF1 [0:11] shown in FIG. 4 is data held in 12 delay flip-flops 202 in the first column. This DF1 [0:11] is a set of 12 bits. Similarly, DF2 [0:11] is data held in 12 delay flip-flops 202 in the second column, and ... DFn [0:11] is 12 delays in the nth column. Data held in the flip-flop 202. DOUT [0:11] is an output signal of the output unit 504.

  The data D1 to Dn are data obtained by digitally converting analog signal amounts of the light receiving elements 101 arranged in the 1st to nth columns, respectively.

  First, the control circuit 503 controls the vertical decoder 109 according to the external control signal 111. Accordingly, the vertical driving unit 108 drives the light receiving element 101 arranged in the pixel unit 102 in accordance with control by the vertical decoder 109. Specifically, the vertical drive unit 108 selects one row designated by the vertical decoder 109. Further, the vertical decoder 109 sequentially designates the rows included in the cutout area.

  The n light receiving elements 101 arranged in the row selected by the vertical driving unit 108 use a potential (analog signal) obtained by converting a physical quantity (light or electromagnetic wave) sensed by the light receiving element 101 itself as a column signal of a corresponding column. Output to line 103.

  Next, the CDS processing unit 104 removes noise by performing CDS processing on n analog signals of the n column signal lines 103. Next, the AD conversion unit 105 converts n analog signals subjected to the CDS processing by the CDS processing unit 104 into n digital signals ADOUT, and outputs the n digital signals ADOUT to the digital memory 501.

  The n digital signals ADOUT output from the AD conversion unit 105 are input to the selectors 201 in the corresponding columns.

  Next, the control circuit 503 sets the latch control signal LATSW to the H level during the period t10 to t12 shown in FIG. 4, and raises the clock signal DMCLK to the H level at time t11 included in the period t10 to t12. As a result, the n × x delay flip-flops 202 latch all the n digital signals ADOUT output from the AD conversion unit 105.

  At the same time, at time t11, the control circuit 503 generates a horizontal address signal HAD [0:11] that specifies the cutout operation and specifies m columns (m = 1 to n−1) corresponding to the cutout positions. Accordingly, the horizontal decoder 502 sets only the bypass control signal BPEN [m] to the H level in response to the horizontal address signal HAD [0:11], and other bypass control signals BPEN [k] (k = 1 to m−). 1, m + 1 to n) are set to L level.

  As a result, the x number of tristate buffers 600 in the m-th column connected to the bypass control signal BPEN [m] that is at the H level are in the output state. That is, the data held by the x delay flip-flops 202 in the m-th column are output to the x bypass signal lines 601 respectively.

  Further, since the bypass control signal BPEN [n] is at the L level, each of the x output selectors 603 outputs the signal of the corresponding bit bypass signal line 601 to the corresponding bit output circuit 602.

  As described above, the control circuit 503 causes the plurality of output selectors 603 to select the digital signals of the plurality of bypass signal lines 601 and delays only one column of the buffers 600 among the plurality of buffers 600 during the cut-out operation. The digital signal held in the flip-flop 202 is output to the bypass signal line 601, and the buffers 600 of all other columns are set to the high impedance state.

  As a result, the output signals of the x delay flip-flops 202 in the m-th column are output to the corresponding bit output circuit 602 through the corresponding bit bypass signal lines 601.

  Thereafter, at time t12, the control circuit 503 sets the latch control signal LATSW to the L level. As a result, each selector 201 outputs the data output by the delay flip-flop 202 of the corresponding bit in the preceding stage.

  After time t12, every time the clock signal DMCLK rises to H level, the delay flip-flop 202 latches the input data. Therefore, the data D2 held in the delay flip-flop 202 in the second column before the clock input is latched in the delay flip-flop 202 in the third column. The delay flip-flop 202 in the second column itself holds the output data D1 of the AD conversion circuit 200 in the first column.

  Similarly, the delay flip-flop 202 in the m-th column initially holds the data Dm in the m-th column. However, when the clock signal DMCLK rises to the H level, the data Dm−1 in the m−1th column is stored. The data Dm-1 is output.

  Thus, every time the clock signal DMCLK rises to the H level, the scan shift operation is performed, so that the output unit 504 can sequentially output data Dm from the m-th column to data D1 of the first column.

  FIG. 5 is a diagram showing an image of the cut-out operation of the solid-state imaging device 500 according to Embodiment 1 of the present invention.

  As described above, since the bypass control signal BPEN [m] (m is a target cut-out position) becomes H level according to the horizontal address signal HAD [0:11], the output unit 504 according to the clock signal DMCLK. From, data from the cut-out position m is output.

  Therefore, the control circuit 503 can output only the data of a necessary cutout portion from the output unit 504 by inputting the clock signal DMCLK h times corresponding to the number of horizontal pixels of the cutout region 900.

  On the other hand, during the all-pixel reading operation, the control circuit 503 generates a horizontal address signal HAD [0:11] that specifies the all-pixel reading operation. Accordingly, the horizontal decoder 502 generates a bypass control signal BPEN [1: n] in which only the bypass control signal BPEN [n] is at the H level. Therefore, the output selector 603 selects the digital signal held by the delay flip-flop 202 at the final stage.

  In this manner, the control circuit 503 causes the output selector 603 to select the digital signal held by the delay flip-flop 202 at the final stage during the all-pixel reading operation.

  Further, the control circuit 503 can output data of all pixels from the output unit 504 by inputting the clock signal DMCLK n times corresponding to the total number of horizontal pixels.

  As described above, the solid-state imaging device 500 according to Embodiment 1 of the present invention can transfer only the pixel data included in the necessary cutout area 900 in the digital memory 501. As a result, it is possible to reduce power consumption as compared to the conventional method in which an area other than the cutout area 900 needs to be transferred. In addition, the solid-state imaging device 500 according to Embodiment 1 of the present invention can realize high-speed transfer without waste in the number of clocks input when transferring a necessary portion.

  Further, the solid-state imaging device 500 according to the first embodiment of the present invention includes any one of the output data of the scan shift circuit connected in the number of stages corresponding to the total number of columns and the data of the bypass signal line 601 used in the clipping operation. Output selector 603 for switching whether to output. Thereby, the solid-state imaging device 500 can transfer data of all pixels using a high-speed clock signal in the all-pixel reading operation. Therefore, the solid-state imaging device 500 can realize a normal all-pixel reading operation with easy control compared to the case where all the columns of the digital memory are divided into a plurality of blocks each including a plurality of columns as described in Patent Document 1. .

  Furthermore, the control circuit 503 can control an arbitrary bypass control signal BPEN by controlling the horizontal address signal HAD. That is, the solid-state imaging device 500 can arbitrarily change the cutout position and the cutout size.

  In addition, the horizontal decoder 502 specifies the cut-out operation and the all-pixel reading operation, and converts the horizontal address signal HAD [0:11] that specifies the cut-out position at the time of the cut-out operation into the bypass control signal BPEN [1: n]. . Further, the digital memory 501 uses the bypass control signal BPEN [1: n] to switch between the clipping operation and the all-pixel reading operation, and switches the clipping position at the time of the clipping operation. As described above, by sharing the signal designating the operation mode and the signal designating the cut-out position, the solid-state imaging device 500 can reduce the number of wires.

  Furthermore, the solid-state imaging device 500 sets all the buffers 600 to a high impedance state during the all-pixel reading operation. As a result, power consumption during the all-pixel reading operation can be reduced.

(Embodiment 2)
In the first embodiment, the example in which the buffer 600 is arranged for the output of the delay flip-flop 202 of all the columns has been described. However, in the second embodiment of the present invention, the delay flip-flop of one column is arranged. An example in which the buffer 600 is arranged only for the output of the flop 202 will be described.

  FIG. 6 is a block diagram of a solid-state imaging apparatus 1000 according to Embodiment 2 of the present invention. Elements similar to those in FIG. 1 are denoted by the same reference numerals, and redundant description is omitted.

  The solid-state imaging device 1000 illustrated in FIG. 6 differs from the solid-state imaging device 500 illustrated in FIG. 1 in the configuration of a digital memory 1001, a control circuit 1003, and an output unit 1004. Further, the solid-state imaging device 1000 does not include the horizontal decoder 502 shown in FIG.

  The control circuit 1003 generates a bypass control signal BPSEL instead of the n-bit bypass control signal BPEN [1: n] described above, and outputs the bypass control signal BPSEL to the digital memory 1001.

  The digital memory 1001 holds the n digital signals ADOUT output from the AD conversion unit 105 and outputs the held n digital signals ADOUT to the sequential output unit 1004.

  The output unit 1004 outputs the digital signal output from the digital memory 501 to the outside of the solid-state imaging device 500.

  FIG. 7 is a circuit diagram showing detailed configurations of the AD conversion unit 105, the digital memory 1001, and the output unit 1004. Elements similar to those in FIG. 2 are denoted by the same reference numerals, and redundant description is omitted.

  The digital memory 501 shown in FIG. 2 described above includes the (n−1) columns × x bits of the buffer 600, but the digital memory 1001 illustrated in FIG. 7 includes the x buffers 600 and the digital memory 501. Different.

  In addition, one buffer 600 is arranged corresponding to each bit of x bits.

  Each input terminal of the x number of buffers 600 is connected to the output terminal of the delay flip-flop 202 of the bit corresponding to the m-th column. Each buffer 600 is a tri-state buffer, and switches between an output state (a state in which a signal of H level or L level is output) and a high impedance state (a state in which no signal is output) according to the bypass control signal BPSEL.

  The output terminals of the x buffers 600 are connected to the bypass signal line 601 for the corresponding bit. In other words, each of the x bypass signal lines 601 is supplied with a signal only from the buffer 600 of the corresponding bit.

  The output unit 1004 includes x output circuits 602 and x output selectors 603.

  Each output selector 603 is connected to the output terminal of the delay flip-flop 202 at the final stage (n-th column) of the scan chain of the corresponding bit and the bypass signal line 601 of the corresponding bit. The output terminal of the output selector 603 is connected to the input terminal of the output circuit 602. Further, the bypass control signal BPSEL is input to the control terminal of each output selector 603.

  Each output selector 603 outputs the output data of the delay flip-flop 202 corresponding to the n-th column when the bypass control signal BPSEL is at L level, and the bypass control signal BPEN [n] is at H level. In this case, the data of the bypass signal line 601 of the corresponding bit is output.

  Further, the control circuit 1003 sets the bypass control signal BPSEL to the L level during the all-pixel reading operation, thereby causing each output selector 603 to hold the digital signal held in the delay flip-flop 202 of the bit corresponding to the final stage. And x buffers 600 are put into a high impedance state. Further, the control circuit 1003 causes each output selector 603 to select the digital signal of the bypass signal line 601 corresponding to the corresponding bit by setting the bypass control signal BPSEL to the H level at the time of the cut-out operation, and x buffers 600. To the output state.

  Here, the bypass signal line 601 may be as long as the horizontal length of the digital memory 1001, or only between the cut-out position m (position of the buffer 600) and the output selector 603. It may be arranged. In other words, the length of the bypass signal line 601 may be the length from the position of the buffer 600 to the position of the output circuit 602 for the corresponding bit.

  In the former case, since the performance is constant without depending on the set cut-out position m, the control is easy. On the other hand, in the latter case, it is possible to optimize the transfer time of the bypass signal line 601 in the horizontal direction depending on the cutout position m, so that higher speed operation can be realized.

  As shown in FIG. 5, the cutout position m is normally located on the side where the output unit 504 is disposed with respect to the center of all n columns in the horizontal direction. That is, in the latter case, the horizontal length of the bypass signal line 601 is ½ or less of the horizontal length of the digital memory 1001 (an area in which the plurality of delay flip-flops 202 are arranged). .

  Next, the operation of the solid-state imaging device 1000 according to Embodiment 2 of the present invention will be described using FIG.

  First, the cut-out operation of the solid-state imaging device 1000 will be described.

  FIG. 8 is a timing chart showing the operation of the solid-state imaging device 1000.

  First, the control circuit 1003 controls the vertical decoder 109 according to the external control signal 111. Accordingly, the vertical driving unit 108 drives the light receiving element 101 arranged in the pixel unit 102 in accordance with control by the vertical decoder 109. Specifically, the vertical drive unit 108 selects one row designated by the vertical decoder 109. Further, the vertical decoder 109 sequentially designates the rows included in the cutout area.

  The n light receiving elements 101 arranged in the row selected by the vertical driving unit 108 use a potential (analog signal) obtained by converting a physical quantity (light or electromagnetic wave) sensed by the light receiving element 101 itself as a column signal of a corresponding column. Output to line 103.

  Next, the CDS processing unit 104 removes noise by performing CDS processing on n analog signals of the n column signal lines 103. Next, the AD conversion unit 105 converts n analog signals subjected to the CDS processing by the CDS processing unit 104 into n digital signals ADOUT, and outputs the n digital signals ADOUT to the digital memory 501.

  The n digital signals ADOUT output from the AD conversion unit 105 are input to the selectors 201 in the corresponding columns.

  Next, the control circuit 1003 sets the latch control signal LATSW to H level during the period t20 to t12 shown in FIG. 8, and raises the clock signal DMCLK to H level at time t11 included in the period t10 to t12. As a result, the n × x delay flip-flops 202 latch all the n digital signals ADOUT output from the AD conversion unit 105.

  At the same time, the control circuit 1003 sets the bypass control signal BPSEL to the H level at time t21.

  As a result, the x tri-state buffers 600 are in the output state. Therefore, the data of the delay flip-flop 202 in the m-th column is output to the bypass signal line 601.

  Since the bypass control signal BPSEL is at the H level, each of the x output selectors 603 outputs the signal of the corresponding bit bypass signal line 601 to the corresponding bit output circuit 602.

  Therefore, the output signals of the x delay flip-flops 202 in the m-th column are output to the corresponding output circuit 602 through the corresponding bypass signal lines 601.

  Thereafter, at time t22, the control circuit 1003 sets the latch control signal LATSW to the L level. As a result, each selector 201 outputs the data output by the delay flip-flop 202 of the corresponding bit in the preceding stage.

  After time t22, every time the clock signal DMCLK rises to H level, the delay flip-flop 202 latches the input data. Therefore, the data D2 held in the delay flip-flop 202 in the second column before the clock input is latched in the delay flip-flop 202 in the third column. The delay flip-flop 202 in the second column itself holds the output data D1 of the AD conversion circuit 200 in the first column.

  Similarly, the delay flip-flop 202 in the m-th column initially holds the data Dm in the m-th column. However, when the clock signal DMCLK rises to the H level, the data Dm−1 in the m−1th column is stored. The data Dm-1 is output.

  Thus, every time the clock signal DMCLK rises to the H level, the scan shift operation is performed, so that the output unit 1004 can sequentially output data Dm from the m-th column to data D1 of the first column.

  Moreover, the figure which shows the image of the cutting-out operation | movement of the solid-state imaging device 1000 which concerns on Embodiment 2 of this invention is the same as that of FIG.

  As described above, since the bypass control signal BPSEL becomes H level, the data from the cut-out position m is output from the output unit 1004 according to the clock signal DMCLK.

  Therefore, the control circuit 1003 can output only the data of a necessary cutout portion from the output unit 1004 by inputting the clock signal DMCLK h times corresponding to the number of horizontal pixels in the cutout region 900.

  On the other hand, in the case of the all-pixel reading operation for outputting the data of all the pixels included in the pixel unit 102, the control circuit 1003 sets the bypass control signal BPSEL to the L level.

  Accordingly, each of the x output selectors 603 outputs the output data of the delay flip-flop 202 in the n-th column of the corresponding bits to the corresponding output circuit 602.

  Therefore, the control circuit 1003 can output data of all pixels from the output unit 1004 by inputting the clock signal DMCLK n times corresponding to the total number of horizontal pixels.

  As described above, the solid-state imaging device 1000 according to the second embodiment of the present invention, similarly to the solid-state imaging device 500 according to the first embodiment, the output data of the scan shift circuit connected in the number of stages corresponding to the total number of columns, An output selector 603 is provided for switching which of the data of the bypass signal line 601 used in the cutout operation is to be output. Thereby, the solid-state imaging device 1000 can transfer the data of all pixels using a high-speed clock signal in the all-pixel reading operation. Therefore, the solid-state imaging device 1000 can realize a normal all-pixel reading operation with easier control than in the case where all the columns of the digital memory are divided into a plurality of blocks each including a plurality of columns as described in Patent Document 1. .

  Furthermore, the solid-state imaging device 1000 according to the second embodiment of the present invention suppresses an increase in circuit compared with the solid-state imaging device 500 according to the first embodiment by setting the cutout position as a fixed position (m-th column). be able to.

  The solid-state imaging device 1000 sets all the buffers 600 to a high impedance state during the all-pixel reading operation. As a result, power consumption during the all-pixel reading operation can be reduced.

(Embodiment 3)
In the third embodiment of the present invention, a modification of the solid-state imaging device 1000 according to the second embodiment will be described. The solid-state imaging device 1000 according to Embodiment 3 of the present invention differs from the solid-state imaging device 1000 according to Embodiment 2 in the configuration of the digital memory 1001.

  FIG. 9 is a circuit diagram of a digital memory 1001A according to Embodiment 3 of the present invention. Note that the same elements as those in FIG. 7 are denoted by the same reference numerals, and redundant description is omitted.

  A digital memory 1001A illustrated in FIG. 9 includes an operation stop unit 1400 in addition to the configuration of the digital memory 1001 illustrated in FIG.

  The operation stop unit 1400 stops the operation of the delay flip-flop 202 in the column that does not include the first pixel from which data is read out during the cut-out operation. Specifically, the operation stop unit 1400 stops the supply of the clock signal DMCLK to the delay flip-flop 202 in the column that does not include the first pixel during the cut-out operation.

  The operation stop unit 1400 includes a plurality of AND elements 1401 and an inverter 1402.

  A bypass control signal BPSEL is input to the inverter 1402.

  The plurality of AND elements 1401 are arranged in a column that is not used during the cut-out operation among the n columns. In addition, one AND element 1401 is arranged corresponding to each of the columns that are not used during the cut-out operation.

  Each AND element 1401 receives the clock signal DMCLK and the output signal of the inverter 1402. The output terminal of each AND element 1401 is connected to the clock terminals of the x delay flip-flops 202 in the corresponding column.

  Note that the clock signal DMCLK is inputted as it is to the clock terminals of the h delay flip-flops 202 corresponding to the columns included in the region used in the cut-out operation, as in the second embodiment.

  With the above configuration, when the bypass control signal BPSEL becomes H level during the cutout operation, the operation stopping unit 1400 fixes the clock input terminal of the delay flip-flop 202 in the column not used during the cutout operation to the L level. Therefore, these delay flip-flops 202 do not operate when transferring data in the horizontal direction during the cut-out operation. Therefore, the solid-state imaging device 1000 according to Embodiment 3 of the present invention can suppress power consumption during the cut-out operation.

  During the all-pixel reading operation, the bypass control signal BPSEL is at the H level, so that the clock signal DMCLK is supplied to all the delay flip-flops 202.

  The solid-state imaging device according to the first to third embodiments of the present invention has been described above, but the present invention is not limited to the first to third embodiments.

  For example, in the first embodiment, an example in which the buffers 600 are arranged in all columns except the nth column will be described, and in the second embodiment, an example in which the buffer 600 is arranged only in the mth column will be described. However, the buffers 600 may be arranged in two or more columns from the first column to the (n-1) th column excluding the nth column. For example, the buffer 600 may be arranged for each predetermined column.

  The solid-state imaging devices according to the first to third embodiments are typically realized as an LSI that is an integrated circuit. Note that one chip may be included so as to include all processing units included in the solid-state imaging device, or the solid-state imaging device may be configured by a plurality of chips.

  Further, the circuit integration is not limited to LSI, and may be realized by a dedicated circuit or a general-purpose processor. Further, an FPGA (Field Programmable Gate Array) that can be programmed after manufacturing the LSI or a reconfigurable processor that can reconfigure the connection and setting of the circuit cells inside the LSI may be used.

  Moreover, you may implement | achieve part or all of the function of the solid-state imaging device which concerns on Embodiment 1-3 of this invention, when processors, such as CPU, run a program.

  Further, the present invention may be the above program or a recording medium on which the above program is recorded. Needless to say, the program can be distributed via a transmission medium such as the Internet.

  Moreover, you may combine at least one part among the functions of the solid-state imaging device which concerns on the said Embodiment 1-3, and its modification.

  Moreover, all the numbers (bit number etc.) used above are illustrated in order to specifically describe the present invention, and the present invention is not limited to the illustrated numbers. Furthermore, the logic levels represented by high / low or the switching states represented by on / off are illustrative for the purpose of illustrating the present invention, and different combinations of the illustrated logic levels or switching states. Therefore, it is possible to obtain an equivalent result. Furthermore, the configuration of the logic circuit shown above is exemplified for specifically explaining the present invention, and an equivalent input / output relationship can be realized by a logic circuit having a different configuration. In addition, the connection relationship between the components is exemplified for specifically explaining the present invention, and the connection relationship for realizing the function of the present invention is not limited to this.

  Further, various modifications in which the present embodiment is modified within the scope conceivable by those skilled in the art are also included in the present invention without departing from the gist of the present invention.

  The present invention can be applied to a solid-state imaging device, and in particular to a MOS solid-state imaging device. Further, the present invention can be applied to cameras such as a digital still camera and a digital video camera provided with a solid-state imaging device.

100, 500, 1000 Solid-state imaging device 101 Light receiving element 102 Pixel unit 103 Column signal line 104 CDS processing unit 105 AD conversion unit 106, 501, 1001, 1001A Digital memory 107, 504, 1004 Output unit 108 Vertical drive unit 109 Vertical decoder 110 , 503, 1003 Control circuit 111 External control signal 200 AD converter circuit 201 Selector 202 Delay flip-flop 203, 602 Output circuit 400, 900 Cutout area 401 Output area 502 Horizontal decoder 600 Buffer 601 Bypass signal line 603 Output selector 604, 701 , 1402 Inverter 702 NAND element 703 NOR element 1400 Operation stop unit 1401 AND element ADOUT Digital signal BPEN, BPSEL Viper Control signal DMCLK clock signal LATSW latch control signal HAD the horizontal address signal

Claims (13)

A solid-state imaging device,
A plurality of pixels arranged in a matrix;
A readout unit that reads out an analog pixel signal from the plurality of pixels;
A plurality of conversion circuits that are provided for each column and convert analog pixel signals read from the pixels arranged in the corresponding columns into digital signals;
A plurality of data holding units that are provided for each column and hold digital signals converted by the conversion circuit of the corresponding column;
The plurality of data holding units are connected in series,
Each data holding unit transfers a digital signal to be held to a subsequent data holding unit, and receives a digital signal held by the previous data holding unit,
The solid-state imaging device further includes:
A bypass signal line;
A buffer connected to one data holding unit other than the data holding unit at the last stage among the plurality of data holding units, and outputs a digital signal held in the one data holding unit to the bypass signal line;
A first selector that selects one of the digital signal held by the data holding unit in the final stage and the digital signal of the bypass signal line, and outputs the selected digital signal;
A solid-state imaging device comprising: an output circuit that outputs a digital signal output by the first selector. The solid-state imaging device outputs a digital signal corresponding to pixel signals of all pixels of the plurality of pixels, and pixel signals of a plurality of first pixels that are a part of the plurality of pixels. A second operation mode for outputting only a corresponding digital signal;
The solid-state imaging device further includes:
In the first operation mode, the first selector selects the digital signal held by the data holding unit at the final stage, and in the second operation mode, the first selector selects the digital signal of the bypass signal line. The solid-state imaging device of Claim 1. The solid-state imaging device
A digital signal connected to each of a plurality of first data holding units included in a plurality of data holding units other than the data holding unit at the last stage is connected to the bypass signal. The solid-state imaging device according to claim 2, further comprising a plurality of buffers including the buffer that outputs to a line. The plurality of buffers are tri-state buffers;
In the second operation mode, the control circuit further outputs a digital signal held in the corresponding first data holding unit to only one of the plurality of buffers to the bypass signal line. The solid-state imaging device according to claim 3, wherein the output state is set and all other buffers are set to a high impedance state. The plurality of buffers are connected to each of all data holding units other than the data holding unit in the final stage, and output a digital signal held in the corresponding data holding unit to the bypass signal line. The solid-state imaging device according to 3 or 4. The control circuit specifies one of the first operation mode and the second operation mode, and specifies any one of the plurality of buffers in the second operation mode. Generating a first signal with fewer bits,
The solid-state imaging device further includes:
A decoder circuit for converting the first signal into a second signal having the same number of bits as the number of columns;
The decoder circuit sets only one of the plurality of bits of the second signal to the first logic, and sets all other bits to the second logic,
Each bit of the second signal corresponds to one of the plurality of buffers or the first selector,
Each of the buffers is in the output state when the corresponding bit of the second signal is the first logic, and is in a high impedance state when the corresponding bit of the second signal is the second logic,
The first selector selects a digital signal held by the data holding unit in the final stage when the bit of the corresponding second signal is the first logic, and the bit of the corresponding second signal is The solid-state imaging device according to claim 5, wherein a digital signal of the bypass signal line is selected in the case of the second logic. The solid-state imaging device according to claim 2, wherein the bypass signal line is supplied with a signal only from the buffer. The buffer is a tri-state buffer;
The control circuit further sets the buffer in a high impedance state during the first operation mode, and stores the buffer in a first data holding unit connected to the buffer during the second operation mode. The solid-state imaging device according to claim 7, wherein a signal is output to the bypass signal line. The solid-state imaging device further includes:
The solid-state imaging device according to claim 7, further comprising an operation stop unit that stops the operation of the data holding unit in a column that does not include the first pixel in the second operation mode. Each of the data holding units transfers a digital signal to be held to a subsequent data holding unit each time a clock signal is input, and receives the digital signal held by the previous data holding unit,
The solid-state imaging device according to claim 9, wherein the operation stop unit stops the supply of the clock signal to the data holding unit in a column that does not include the first pixel in the second operation mode. The solid-state imaging device according to claim 7, wherein a length of the bypass signal line is a length from a position of the buffer to a position of the output circuit. The solid-state imaging device according to claim 11, wherein a horizontal length of the bypass signal line is equal to or less than ½ of a horizontal length of an area where the plurality of data holding units are arranged. Each of the data holding units is a flip-flop,
The solid-state imaging device further includes:
One is provided for each column, and one of the digital signals converted by the conversion circuit in the corresponding column and the digital signal held in the previous data holding unit is selected, and the selected digital signal is selected in the corresponding column. The solid-state imaging device according to claim 1, further comprising a plurality of second selectors that output to the data holding unit.

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