JP2011018358A - Link bridge - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an improved system for transferring information between a plurality of buses.SOLUTION: A bridge accessible from a host processor includes links and interface means for first and second buses. First and second interfaces are configured as follows: (a) serially outputting information via a link whose format is different from first and second bus formats;(b) responding to a pending transaction having a feature representing an address crossing the bridge and recognize initial exchanges at the first bus and the second bus; (c) and allowing a host processor that communicates via the first bus to (i) use on the first bus an address type that is substantially the same as that used to access the second bus device. (ii) The first bus arbitrates one bus-compatible device on the second bus without using the second bus.

Description

  The present invention relates to a data processing system, and in particular to a bridge system having an information transfer mechanism between buses.

  Computers can use the bus for data transfer between the host processor and various devices such as memory devices and input / output devices. As used herein, an “input / output” device refers to a device that generates input or receives output (or both). Therefore "input / output" is used separately. These buses are arranged in a hierarchical structure in which the host processor is connected to a high level bus reserved for exchanging data that is most urgently needed by the processor. The low level bus is connected to a peripheral device with low priority.

  There are several other reasons for having separate buses. Installing too many devices on a single bus creates a high load. Such a load makes it difficult to drive the bus due to power requirements and delays caused by signal processing of many devices. Also, some devices on a bus periodically act as masters and request control from the bus to communicate with slave devices. By separating several devices on separate buses, the master device can communicate with other devices on the low level bus without interfering with the bus used by the host processor or other master devices.

  The PCI bus standard is specified by Oregon's PCI Special Interest Group of Hillsboro. The PCI bus has a 32-bit width and a multiplexed address-data (AD) bus portion, and can be expanded to a 64-bit width AD bus portion. Maintaining a high data throughput rate (eg, 33 MHz clock rate) on the PCI bus places a fixed limit on the electrical AC / DC load on the bus. Considering speed also limits the capacitance that can be placed on the bus due to the physical length and load of the bus, while future PCI bus rates (eg 66 MHz) exacerbate the electrical load and capacitance related. If these load restrictions are not recognized, transmission delays and operations that cannot be synchronized occur between bus devices.

  In order to avoid these load restrictions, the PCI bus standard specifies a bridge that allows the primary PCI bus to communicate with the secondary PCI bus via the bridge. Additional loads are placed on the secondary bus without increasing the load on the primary bus. See US Pat. Nos. 5,548,730 and 5,694,556 for various types of bridges.

  The PCI bridge monitors a hierarchical structure that allows an initiator or bus master on either bus to complete a transaction with a target on another bus. As used herein, hierarchical structure refers to a system where high-level or low-level concepts are meaningful. For example, the PCI bus system is hierarchical in various scores. The order of levels is monitored when the high level host processor communicates from the high level bus, typically through the bridge, to the low level bus. The level order is also monitored when the same level bus does not communicate directly but communicates via a bridge interconnected to a higher level bus. Also, the order of levels is monitored when data is filtered by its address before being allowed to pass through the bridge based on the included levels. There are other hierarchical systems that monitor the order of levels by using one or more prior concepts or by using different concepts.

  Some personal computers include a slot for an add-on card that allows the card to be connected to a peripheral bus in the computer. Because users often require additional slots, expansion cards are designed to connect between expansion units that provide additional slots for add-on cards and the peripheral bus. See US Pat. Nos. 5,006,981, 5,191,657 and 5,335,329 for systems for bus expansion. See also US Pat. No. 5,524,252.

  In portable computers, special considerations are required when a user connects additional peripheral devices. Often the user takes the portable computer to the desktop and connects through a coupling station or port replicator for a keyboard, monitor, printer, and the like. The user also wishes to connect to the network through a network interface card in the coupling station. In some cases, users require additional devices such as hard devices and CD-ROM drives. Although technically possible to a limited extent, extending a portable computer bus through a cable requires a large number of wires and because of the ring time caused by the substantial length of the cable difficult.

  In US Pat. No. 5,696,949, the host chassis has a PCI to PCI bridge connected via a cable bus to a PCI to PCI bridge in the expansion chassis. This system is relatively complex because two independent bridges communicate on a single cable bus. This cable bus essentially contains all the lines normally found on the PCI bus. This method uses a delay technique that handles the clock ring time associated with the cable bus. The clock signal generated on the extended side of the cable bus is as follows: (a) It is sent across the cable bus, but there is a delay depending on the length of the cable. (B) The delay line causes a delay equal to the extension side of the cable bus before the extension side is used. Such a design complicates the system and makes it difficult to provide a workspace in various physical designs, thus limiting to pre-designed length adjustment cables.

  U.S. Pat. No. 5,590,377 shows a primary PCI bus for a portable computer that is PCI-connected to a PCI-to-PCI bridge in a combined station. When combined, the primary bus and the secondary bus are physically in close contact. The cable is not separable between the coupling station and the portable computer. In this arrangement, there is no interface circuit between the primary PCI bus and the coupling station. See US Application 5,724,529.

  US Pat. No. 5,540,597 proposes avoiding the addition of a PCMCIA connector when connecting peripheral devices to a PC card slot in a portable computer, but does not disclose any associated bridge technology for that purpose.

  U.S. Pat. No. 4,882,702 shows a programmable controller that controls industrial machines and processes. The system serially exchanges data with various input / output modules. One of these modules can be replaced with an expansion module capable of serial communication with various groups of additional input / output modules. This system is not similar to a bridge in that the communication method with the expansion module is different from the communication method with the input / output module. In the expansion module, the system changes to a block transfer mode where a group of status bytes is transferred to all expansion devices. This system is also limited to input / output processing and does not support various memory processes that can be addressed. See US Pat. Nos. 4,413,319 and 4,504,927.

  In US Pat. No. 5,572,525, another bus designed for equipment (IEEE488 general purpose equipment bus) interrupts bus information to packets transferred serially over a transfer cable to another expansion unit Connect to an expansion unit. This other expansion device restores the serial packet to parallel data applied to the second equipment bus. This expansion device is an intelligent system that operates through a message interpretation layer before the parallel / serial conversion layer and all other layers. This system is therefore different from a bridge. This system is also limited in the type of processing it performs. See U.S. Patent 4,959,833.

  U.S. Pat. No. 5,325,491 shows a system for interfacing a local bus to a cable with multiple wires for coupling to a remote peripheral device. See U.S. Patents 3,800,097, 4,787,029, 4,961,140, 5,430,847.

  Small Computer System Interface (SCSI) defines a bus standard for various peripheral devices. This SCSI bus is part of an intelligent system that responds to high level instructions. Therefore, a SCSI system requires a software driver that the hardware can communicate with the SCSI bus. This fairly complex system is very different from the bridge defined by the PCI standard. There are many other complex technologies and protocols for data transfer, including Ethernet, Token Ring, TCP / IP, ISDN, FDDI, HIPPI, ATM, Fiber Channel, etc. These are not related to bridge technology.

  See also US Patents 4,954,949, 5,038,320, 5,111,423, 5,446,869, 5,495,569, 5,497,498, 5,507,002, 5,517,623, 5,530,895, 5,542,055, 5,555,510, 5,572,688, 5,611,053.

  There is therefore a need for an improved system for transferring information between multiple buses.

SUMMARY OF THE INVENTION In accordance with an exemplary embodiment illustrating the features and advantages of the present invention, a bridge is provided that can be accessed by a host processor to extend access from a first bus to a second bus to a portable computer. The first bus and the second bus are independently connected to a plurality of bus-compatible devices of the respective buses. Possible devices include memory devices and input / output devices. The bridge has a link with interface means for the first bus and the second bus. A first interface is coupled between the first bus and the link. A second interface is coupled between the second bus and the link. The first and second interfaces that operate as a single bridge operate as follows. (A) Before starting to transfer the information from the link, the information is serially output via a link of a format different from the first bus and the second bus format without waiting for an acknowledgement by the link; b) accepting an initial exchange on the first bus and the second bus in response to a pending transaction characterized by a destination that crosses the bridge; (c) a host processor communicating via the first bus Selectively address different devices including memory devices and input / output devices compatible with two buses, and (i) substantially the same address used to access the second bus device A type is used on the first bus; (ii) the first one is compatible with the second bus without using the second one. Mediate.

In accordance with another concept of the invention, a processor accessible bridge can extend access from the first bus to the second bus. The first bus and the second bus are independently connected to a plurality of bus-compatible devices of the respective buses. Possible devices include memory devices and input / output devices. The bridge has a link with interface means for the first bus and the second bus. A first interface is coupled between the first bus and the link. A second interface is coupled between the second bus and the link. The first interface and the second interface that operate as a single bridge can operate as follows. (A) Send information serially via a link of a format different from the formats of the first bus and the second bus. (B) The first bus exchanges information between the first bus and the second bus according to a hierarchy higher than the predetermined second bus. And (c) the host processor that communicates via the first bus selectively addresses different devices including a compatible memory device and input / output device to the second bus, and (i) the second bus Using substantially the same address type on the first bus as used to access the device of the first, and (ii) the first without using the second Arbitrate one of the compatible devices to the second bus, and (iii) do not pass information through hierarchical level arbitration.

  In accordance with another concept of the present invention, a processor-accessible bridge can extend access from the first bus to the second bus. The first bus and the second bus are independently connected to a plurality of bus-compatible devices of the respective buses. The bridge has a link and first and second bus interfaces. A first interface is coupled between the first bus and the link. A second interface is coupled between the second bus and the link. The first interface and the second bus interface operate as a single bridge and over a link different from the format of the first bus and the second bus without waiting for the acknowledgment input by the link before arbitrating the transmission of information by the link. Can send information serially.

  By using the apparatus and method described above, in the improved system, transmission of information between the buses is achieved. In a preferred embodiment, the two buses communicate over a bidirectional link formed with a set of unidirectional links. Each uses a twisted pair or twin axis line (depending on the desired speed and the expected transmission distance). Information from the bus is FIFO (first-in first-out) before being serialized into a frame for transmission on the link. Received frames are deserialized and loaded into the FIFO register before being placed on the destination bus. Preferably, interrupts, error signals, and status signals are transmitted over the link.

  In this preferred embodiment, the address and data are taken together by four bits acting as either a control or byte enable signal, in one transaction simultaneously from the bus. Two or more additional bits are added to the tag as either an address cycle, a non-posted write acknowledgment, or a data burst (or single cycle) in each transaction. If these transactions are posted write, they are quickly recorded in the FIFO register before being encoded into a frame number that is sent serially to the link. When prefetched reads are allowed, the FIFO register can store prefetched data if the initiator requests it. For a single cycle write or other transaction that must straddle a response, the bridge can signal an initiator to wait immediately before the request reaches the target.

  In the preferred embodiment, one or more buses follow the PCI or PCMCIA bus standard (although other bus standards can be used). The preferred device operates as a bridge with configuration registers loaded with information characterized by the PCI standard. The device transfers information between the buses depending on whether the pending address is in the range held by the configuration register. This scheme works with devices on the other side of this bridge, which is given a unique base address to avoid address collisions.

  In a highly desirable embodiment, the device is made as two independent application specific integrated circuits (ASICs) connected by a cable. Preferably, these two integrated circuits have the same structure, but can operate in two different modes according to a control signal applied to one of its pins. When operating with hierarchical buses (primary and secondary buses), these integrated circuits are put into a mode appropriate for the associated bus. The ASIC associated with the secondary bus preferably has an arbitrator that can grant the benefits of secondary bus master control. This preferred ASIC can provide multiple ports that support a mouse and keyboard as well as parallel and serial ports.

  When used in a portable computer, one of the ASICs is assembled with a connector in a package designed to fit a PC card slot according to the PCMIC standard. This ASIC can be connected by cable to other ASICs, which are placed at the coupling station. Thus, the device can operate as a bridge between the card bus where the coupling station is located and the PCI bus. This design is particularly useful for combined stations, as the desired ASIC can provide mouse and keyboard ports. Also, the secondary PCI bus implemented by the ASIC can be connected to the video card or video processing card of the main coupling circuit board for driving the monitor.

  In some embodiments, an ASIC is installed on a portable computer by an original equipment manufacturer (OEM). This portable computer has a special connector that is routed to a cable that connects to a coupling station with an ASIC. For such an embodiment, it is highly advantageous that the ports for various devices are in the desired ASIC. The OEM can take advantage of the existing features of the ASIC, and without it, it can omit circuits that need to implement such a port.

  Other objects, features and advantages of the present invention, as well as the general description above, will be more fully described with reference to the accompanying drawings and the following detailed description and embodiments of the invention based on the drawings. To be understood.

FIG. 4 is a diagrammatic block dialog showing bridges separated by links in a bridge according to the principles of the present invention. FIG. 2 is a schematic block diagram illustrating a bridge according to the principles of the present invention using the link of FIG. FIG. 3 is a schematic block diagram illustrating the bridge of FIG. 2 using a coupling system according to the principles of the present invention. It is sectional drawing of the cable of FIG. FIG. 4 is a diagram of the bridge of FIG. 3 relating to a portable computer and various peripheral devices. FIG. 6 shows a coupling station similar to that of FIG. 5 but with a portable computer modified to include an application specific integrated circuit designed to support the link to the coupling station.

Detailed Description of the Preferred Embodiment Referring to FIG. 1, a bridge is shown as coupling between a first bus 10 and a second bus 12 (alternatively referred to as a primary bus 10 and a secondary bus 12). These buses may be PCI or PCMCIA 32-bit buses, but other types of buses are contemplated and the description is not limited to any particular type of bus. This type of bus usually has address and data lines. In some cases, such as the PCI bus, the address and data are multiplexed on the same line. In addition, these buses have signal lines that allow devices on the bus to successfully process transactions. In the case of the PCI standard, these signal lines include four lines that are used for either control or byte enabling (C / BE [3: 0]). Other signal lines based on the PCI standard are for acquiring bus control, for handshaking, and the like (eg, FRAME22 #, TRDT #, IRDY #, STOP #, DEVSEL #, etc.) .

  Buses 10 and 12 are shown connected to a first interface 14 and a second interface 16 (also referred to as interfaces 14 and 16), respectively. Bus information selected by interfaces 14 and 16 for transmission is loaded into registers 18 and 20. Input bus information selected by interfaces 14 and 16 for delivery to the bus is retrieved from registers 22 and 24, respectively. In one embodiment, the registers 18-24 are each 16x38 FIFO registers, but other types of registers of different sizes can be used in other embodiments.

  In this embodiment, registers 18-24 are at least 38 bits wide. Of these, 36 bits are reserved for 4 control bits (C / BE # [3: 0]] and 32 address / data bits (AD [31: 0]) based on the PCI bus standard. The remaining two bits can be used to send an additional tag to identify the nature of the transaction involved. Other bits may be needed to characterize each subject transaction. Transactions can be tagged such as address cycle, non-bossed write acknowledgement, data burst, end of data burst (or single cycle). Thus, the output write transaction can be tagged as a single cycle transaction or a burst portion. The output read request can be tagged as part of the burst with a byte enable code (C / BE) sequence for each successive read cycle of the burst. It will be appreciated that other coding schemes using different numbers of bits may be used in alternative embodiments.

  Balancing the structure shown in FIG. 1 is a link designed to achieve bi-directional communication between interfaces 14 and 16 via registers 18-24. For example, encoder 28 can receive the oldest 38 bits from register 20 and change it to 5 bytes (40 bits). The extra 2 bits are encoded to represent the interrupt, status signal and error signal supplied from block 34.

  Each of these 5 bytes is converted into a 10-bit frame that can carry not only the information useful to coordinate the link but also the information in each byte. For example, these frames can carry comma markers, idle markers or flow control signals in a well-known manner. A transceiver system operating with such bytes encoded in a 10-bit frame is commercially available from Hewlett-Packard under the model number HDMP-1636 or 1646. The frame generated by the encoder 28 is transferred to the receiving unit 48 that supplies serial information to the decoder 30 via the transmitting unit 44 by the unidirectional link 46. Similarly, the encoder 26 transfers the serial information through the transmission unit 38 to the reception unit 42 that supplies the serial information to the decoder 32 via the unidirectional link 40.

  Flow control is necessary when there is a risk of overflow in the FIFO. For example, if the FIFO register 22 is almost full, it provides a threshold detect signal 36 to the encoder 26 and forwards this information to the decoder 32 via the link 40. In response, the decoder 32 issues a threshold stop signal 50 to the encoder 28, which stops the transfer of serial information, thereby preventing the FIFO register 22 from overflowing in advance. Similarly, prediction of FIFO register 24 overflow causes a threshold detect signal 52 to flow through encoder 28 and link 46, causing decoder 30 to issue a threshold stop signal 54, which causes encoder 26 to receive more frames of information. Stop sending. In one embodiment, the system examines the received information to determine whether it contains a transmission error or in some manner whether the original form is compromised. In such an event, the system can request retransmission of information that has been compromised, thereby ensuring a highly trusted link.

  In this embodiment, elements 14, 18, 22, 26, 30, 38 and 48 are part of a single application specific integrated circuit (ASCI). Elements 16, 20, 24, 28, 32, 42 and 44 are also part of the ASCI 58. As will be described later, the first ASIC 56 and the second ASIC 58 have the same configuration, but operate in different modes. Other embodiments do not use an ASIC, but can instead use programmable logic or similar circuitry. As will be shown later, the ASIC 56 operates in a mode designed to fit the primary bus 10 and sends an output to block 57 (for reasons described herein). Conversely, ASIC 58 receives input from block 34.

  Encoders 26 and 28 have parallel outputs 27 and 29, respectively, as an option for applications that require such information. For such applications, decoders 30 and 32 have parallel inputs 31 and 33, respectively. These optional inputs and outputs can be connected to a transmit / receive chip as described above provided by Hewlett-Packard Company with model number HDMP-1636 or -1646. These devices allow the system to transmit serial information using an external transmit / receive chip. This allows the users of the ASIC units 56 and 58 to control more of the link transmission methods.

  Referring to FIG. 2, the ASIC parts 56 and 58 are shown in more detail. The encoder, decoder, transmitter, receiver, and FIFO register are incorporated into blocks 60 and 62, which are interconnected by a bidirectional cable comprised of the unidirectional links 40 and 46 described above. The interface 14 is connected to the primary bus 10, which is also shown connected to a number of bus-compatible devices 64. Similarly, the interface 16 is connected to the second bus 12, which is also connected to a number of bus-compatible devices 66. Devices 64 and 66 are PCI compliant devices and can operate as memory devices or input / output devices.

  The interface 14 is shown connected to the first register means 68, which operates as a configuration register according to the PCI standard. Since this system operates as a bridge, the configuration register 68 typically has information related to the bridge. The configuration register 68 also includes a base register and a restriction register for designating a range of addresses or a predetermined list for devices existing on the secondary bus 12. Based on the PCI standard, devices on the PCI bus have their own base registers, which allow mapping of memory space and / or I / O space. As a result, the base and limit register 68 in the configuration register 68 coordinates the mapping performed by individual PCI devices. The information in the configuration register 68 is reflected in the second configuration register 67 (also referred to as second configuration means). This makes the configuration information immediately available to the interfaces on both sides of the link.

  In this embodiment, the ASIC 58 has an arbitration device 70. The arbiter receives a request from a master on the secondary bus 12 to control the bus. The arbiter has a fair algorithm that grants permission to the request by issuing a permission signal to one of the competing master requests. In this hierarchical scheme, the secondary bus 12 requires bus arbitration, but the primary bus 10 arbitrates by itself. Accordingly, the ASIC 56 is set to a mode in which the arbitrating device 72 is disabled. The mode of ASICs 56 and 58 is set by control signals applied to pins 74 and 76, respectively. This mode selection reverses the direction of the signals associated with blocks 57 and 34.

  In this embodiment, the ASIC 58 is in a mode that implements the third bus 78. Bus 78 conforms to the PCI standard, but is more conveniently implemented in another standard. Bus 78 is connected to a number of devices that operate as port means. For example, devices 80 and 82 can implement a PS / 2 port that can be connected to either a mouse or a keyboard. Device 84 implements an ECP / EPP parallel port for driving a printer or other device. Device 86 executes a normal serial port. Devices 80, 82, 84 and 86 are shown with input / output lines 81, 83 and 87. Devices 80-86 are addressed on bus 10 as if they were PCI devices on bus 12. In this embodiment, a bus 88 having the same devices as shown on bus 78 is shown in ASIC 56, which enables OEM companies to implement these ports without the need for independent input / output circuitry. Make it possible.

  Referring to FIG. 3, the ASIC 58 is shown in a coupling station 130 that is connected to an oscillator 91 that generates remote and internal clocks. The ASIC 58 has lines 81 and 83 connected via a connection device 90 for connecting to a keyboard and a mouse, respectively. Serial line 85 and parallel line 87 are shown connected to transceivers 92 and 94, respectively, which also connects 90 for connection to various parallel and serial peripheral circuits such as printers and modems. Connect to.

  The ASIC 58 is shown connected to the secondary bus 12 described above. The bus 12 is shown connected to an adapter card 96 that allows the PCI bus 12 to communicate with IDE devices such as hardware devices, pack-up tape devices, CD-ROM devices, and the like. Another adapter card 98 is shown to allow communication from the bus 12 to a universal serial port (USB). The network interface card 100 enables communication with various networks operating on the bus 12 based on the Ethernet standard, the token ring standard, and the like. Video adapter card 102 (or referred to as video means) allows the user to operate other monitors. The add-on card 104 is one of various cards selected by the user to perform an effective function. While this embodiment is implemented by an add-on card and shows various functions, other embodiments can perform one or more functions of a common circuit board in a dock (e.g., IDE). Functions including things like adapter cards).

  The ASIC 58 communicates via the receiver / transmitter 106, which provides a physical interface to the cables 40, 46 via the terminal connector 108. The connector 108 is a 20 pin connector that can send high speed signals through an EMI shield (eg, a low strength helix connector of the type provided by the Molex company), but other coupling types can be used instead. The opposite ends of the cables 40, 46 are connected to the physical interface 112 via a gigabyte terminal connector 110, which operates as a receiver / transmitter. Interface 112 is shown connected to the first ASIC 56, which is also shown connected to an oscillator 114 for generating a local clock signal. This design specification allows for the use of an external transmitter / receiver (eg, lines 27, 29, 31 and 33 external SERDES in FIG. 1), but other embodiments are ASIC 56 and Considering 58 internal devices, these external devices can be omitted.

  While this embodiment is adapted to work with portable computers having a PCMCIA 32-bit bus 10, other types of computers can be used. Accordingly, the ASIC 56 is shown with a package 116 having an outline according to the PCMCIA standard, and the package 116 is adapted to fit into a slot in a portable computer. Therefore, the ASIC 56 has a connector 118 for connecting to the bus 10. The cables 40, 46 are typically permanently connected to the package 116, but in other embodiments, removable connectors can be used, in which case the user can attach the package 116 to the portable computer if desired. Can be left inside.

  The power supply 120 is shown to generate various supply voltages that are used to power various components. In some embodiments, these supply lines can be connected directly to a portable computer to charge the battery.

  Referring to FIG. 4, the unidirectional links 40 and 46 are indicated by twin axis lines 40A and 40B and are covered by respective shields 40B and 48B. A single shield 122 surrounds lines 40 and 46. Four parallel wires 124 (more are possible as alternative embodiments) are shown mounted around the periphery of the shield 122 for various purposes. These wires 124 may carry power management signals, dock control signals or other signals that are useful at the interface between the coupling station and the portable computer. Although the twin axis line provides high reliability, it can be used in other embodiments where the transmission distance is not large and where a twisted pair or other transmission medium need not have a high bit rate. Here, hard wire coupling is illustrated, but in other embodiments, wireless or other types of connections could be used instead.

  Referring to FIG. 5, the package 116 is shown in a position where it is connected to the PCMCIA slot of the portable computer 126. The computer 126 has a primary bus 10 and a host processor 128. Package 116 is shown connected to the connector 108 of coupling station 130 via cables 40, 46. The coupling station 130 is shown connected to a keyboard 132 and a mouse 134 via a PS / 2 port. Printer 136 is shown coupled to parallel port 130 of coupling station 130. Said video means 102 is shown connected to a monitor 138. The coupling station 130 is indicated by an internal hard device 140 that connects the adapter card. A CD-ROM device 142 is further mounted on the coupling station 130 and connected to the secondary bus via a suitable adapter card (not shown). The add-on card 104 is shown having its own cable 144.

  Referring to FIG. 6, the modified portable computer 126 ′ is again shown as having a host processor 128 and a primary bus 10. However, also in this embodiment, the portable computer 126 ′ includes the ASIC 56. Thus, no circuitry is required between the ASIC 56 and the cables 40, 46 (apart from peripheral devices). In this case, the laptop end of the cables 40, 46 has a connector 142 similar to that at the other end of the cable (connector 108 in FIG. 5). Connector 143 is paired with connector 141 and is designed to support high speed speed links. As before, connectors 141 and 143 can carry various power management signals and other signals related to the coupling system.

  An important advantage of this arrangement is that it includes circuitry with serial boats, parallel ports, PS / 2 boats for mice and keyboards, and the like. Since the portable computer 126 'typically includes such a port, the ASIC 56 simplifies the portable computer design. This advantage has the added advantage of having a single ASIC design (ie, the same structure for ASICs 56 and 58), which can be operated on either a portable computer or a combined station, thereby facilitating ASIC design. , And reduce the required inventory.

  In order to facilitate understanding of the principles associated with the apparatus described above, its operation is briefly described. This operation is described in connection with the combined system of FIGS. 3 and 5 (which is generally related to FIG. 2), but the operation is similar for other types of arrangements. For a coupling system, coupling is accomplished by plugging package 116 into portable computer 126 (FIG. 5). This achieves a link between the primary bus 10 and the ASIC 56 (FIG. 3).

  At this point, it is assumed that an initiator (host processor or master) accessing the primary bus 10 asserts control of the bus. The initiator normally sends a request signal to an internal arbitration device (not shown) that will give control permission to the initiator. In some event, the initiator claiming control of the primary bus 10 exchanges an appropriate handshake signal and sends an address to the bus 10. A control signal applied to the signal line of bus 10 indicates whether the transaction is a read, write, or other type of transaction.

  Interface 14 (FIG. 2) sees the pending (pending) address and it is a transaction with a device on the other side of the bridge (ie, second bus 12) or the bridge. Determine if it is a transaction with itself. The configuration register 68 is already loaded with information indicating the range of addresses that determine the jurisdiction of the interface 14 in a normal manner.

  Assuming a write transaction is pending on the bus 10, the interface 14 transfers 32 address bits (PCI standard) to the FO register 18 (FIG. 1) along with four bus control bits. Encoder 26 adds at least two bits indicating that this information is an address cycle. This information is then broken down into frames that can carry flow control and other signals before being serially transferred over link 40.

  Without waiting, the interface 14 proceeds to the data cycle and receives up to 32 bits of data from the bus 10 with 4 bytes of enable bits. As before, this information is tagged, supplemented with additional information, and broken down into frames for link 40 serial transfer. This transmission information is tagged to indicate whether it is a burst or part of a single cycle.

  Upon receipt, decoder 32 returns the frame to its original 32-bit format and loads the two cycles described above into the stack of registers 24. The interface 16 finally recognizes the first cycle as an address cycle in the write request. The interface 16 then negotiates control over the bus 12 in the usual manner and gives the bus 12 an address. The bus 12 device responds to the write request by performing normal handshaking.

  Next, the interface 16 sends the write data stocked in the register 24 to the bus 12. If this transaction is a burst, interface 16 continues to send data to bus 12 by fetching it from register 24. However, if the transaction is a single cycle write, interface 16 closes the bus 12 transaction and loads the register 20 with an acknowledgement. Since this acknowledgment does not require sending data or address information, a unique code is placed in register 20 so that encoder 28 can analyze it into a frame for transmission on link 46 before You can tag this line appropriately. Upon receipt, decoder 30 generates a unique code that is loaded into register 22 and ultimately transferred to interface 14, which sends an acknowledgment that the write was successful to the device on bus 10.

  On the other hand, when the initiator sets a control bit for instructing a read request during an address cycle, if the interface 14 is in its jurisdiction, the cycle is received. The interface 14 notifies the initiator on the bus 10 that it is not ready to return data (for example, a retry signal, which is a stop signal defined under the PCI standard). The initiator can start (but cannot end) a data cycle by driving the signal line of the bus 10 with byte enable information. Using the same technique, this address information and subsequent byte enable information is received by the interface 14 and loaded into the register 18 with the tag. These two types of information are then encoded and sent serially over link 40. When received, this information is loaded into the stack of registers 24. Finally, the interface 16 recognizes the first item as a read request and sends address information to the secondary bus 12. The device on the secondary bus 12 responds and performs the appropriate handshake. The interface 16 then transfers the next item of information from the register 24, including the byte enable, onto the bus 12, so that the target device can respond with the requested data. This response data is loaded into the register 20 via the interface 16. If pre-fetch is instructed, the interface 16 initiates a number of successive read cycles to store data in the register 20 from successive addresses, whether requested by the initiator or not.

  As before, this data is tagged, broken down into frames, sent serially over link 46, decoded, and loaded into register 22. The transmission data can include pre-fetch data to be stored in the register 22. The interface 14 returns to the primary bus 10 to send the first item of data and, if necessary, allows the initiator to perform the next read cycle. The transmitted data can include prefetch data stored in the register 22. If the next read cycle is performed as part of the bus transaction, the requested data is already in register 22 for immediate delivery to bus 10 by interface 14. If these pre-fetch data are not required in the next cycle, they are discarded.

  Eventually, the initiator releases control of the bus 10. Next, it is assumed that the initiator 12 on the bus 12 sends a request for controlling the bus 12 to the arbitrating device 70 (FIG. 2). If the arbitrating device 70 permits the control, the initiator makes a read or write request by sending an address to the bus 12. The interface 16 responds if this address is not within the jurisdiction range of the address specified in the configuration register 67 (whether it is the jurisdiction of the high level bus 10). In the same way as before, but with the reverse flow over the links 40, 46, the interface 16 receives the address and data cycle and communicates it over the links 40, 46. Before the bus 10 is granted, the interface 14 sends a request to an arbiter (not shown) associated with the bus 10.

  In some cases, the initiator on the primary bus 10 desires to read or write from the port means 80, 82, 84, or 86. These four items are arranged to operate as a PCI standard device. The interface 16 therefore operates as before except that information is routed through the bus 78 rather than through the bus 12.

  Other types of transactions are also performed, including writing and reading configuration registers 67 and 68 (FIG. 2). Other types of transactions defined under the PCI bus standard (or other bus standards) can be performed as well.

  The interrupt signal is generated by the port or by another ASIC 58 device. External interrupts are also received as indicated by block 34. As noted earlier, the interrupt signal can be embedded in the code sent over link 46. When system 60 receives an interrupt, it decodes and forwards to block 57, which may simply be one or more pins of ASIC 56 (eg, PCI standard INTA). This interrupt signal is sent to either the host bus 10 or an interrupt controller that transfers the interrupt to the host processor. System errors are forwarded in a similar manner to produce output on the pins of the ASIC 56 that are either routed directly to the bus 10 or are handled using the given hardware. . The designer can also send individual status signals if desired, which can be manipulated in a similar manner by links 40,46.

  Various modifications are implemented with respect to the preferred embodiment described above. In other embodiments, the illustrated ASIC is divided into several discrete packages, and in some cases, a commercially available integrated circuit. Also, the medium for the link may be a wire, optical fiber, infrared light, radio radio signal, or other media. In addition, the primary and secondary buses have one or more devices, and these devices may be one or more and include memory devices and input / output devices. In addition, the device operates at various clock speeds, bandwidths and data rates. Furthermore, passing transactions through the bridge is stored as posted write or as prefetched data, but some embodiments do not use such techniques. The bridges described herein can also be part of a hierarchy that uses multiple bridges with primary sides connected to the same bus or equivalent or different level buses. Further, the illustrated ports may be of different numbers or types, or may be omitted in certain embodiments. Further, the illustrated arbitration device can omit arbitration for a secondary bus whose design is not dedicated by the master. The sequence of steps can be omitted above, and in other embodiments, these steps can be increased or decreased in number, or performed with different instructions without departing from the scope of the present invention.

Obviously, many modifications and variations of the present invention are possible in light of the above teachings. Therefore, within the scope of the appended claims, the invention may be practiced otherwise than as specifically described.

Claims (26)

A bridge accessible by a processor for extending access to a second bus over a first bus, wherein the first bus and the second bus are each separately connected to each of a plurality of bus compatible devices The bridge is adapted to
Link,
A first interface adapted to couple between the first bus and the link;
A second interface adapted to couple between the second bus and the link;
With
The first interface and the second interface send address information corresponding to the transfer of information before starting the transfer of information over the link, and an acknowledgment of the address information arrives over the link A bridge operable to transfer the information serially over the link in a different format than that of the first bus and the second bus without waiting to do so. A part of the bus-compatible device includes a memory device and an input / output device, and the first interface and the second interface are (a) pending having a feature meaning a destination over the bridge. Accepting to initiate an exchange between the first bus and the second bus in response to a bus transaction, and (b) the processor communicating via the first bus,
(I) using substantially the same type of addressing on the first bus as used to access devices on the first bus;
(Ii) without first interposing a second bus-compatible device on the second bus;
2. Operable to allow individually addressable selectable different ones of bus-compatible devices on the second bus including memory devices and input / output devices that may be present. The described bridge.   The first interface and the second interface are capable of exchanging information between the first bus and the second bus according to a predetermined hierarchical structure that gives the first bus a higher level than the second bus. Item 14. The bridge according to item 1. The first interface and the second interface (a) pass information between the first bus and the second bus according to a predetermined hierarchical structure that gives the first bus a higher level than the second bus. And (b) the processor communicating via the first bus is
(I) using substantially the same type of addressing on the first bus as used to access devices on the first bus;
(Ii) without first interposing a second bus compatible device on the second bus;
(Iii) the information does not go through intermediate hierarchical levels,
2. Operable to allow individually addressable selectable different ones of bus-compatible devices on the second bus including memory devices and input / output devices that may be present. The described bridge.   The first bus and the second bus have a plurality of signal lines that allow a bus-compatible device to negotiate bus communication, and the first interface is a pending transaction on the first bus. In response to the pending transaction on the first bus being sent to the second bus and being processed by the pending transaction before being acknowledged by the second bus, The bridge according to claim 1, 2 or 4, wherein the bridge is operable to apply a retry signal to at least one of the signal lines on the bus.   6. The bridge of claim 5, wherein less than all information on the signal line of the first bus is transmitted over the link by the first interface.   The first interface selectively responds to an address appearing on the first bus that is in a predetermined list of addresses corresponding to bus compatible devices accessible via the second bus. 5. The bridge according to claim 1, 2, or 4, wherein the bridge does not respond to an address corresponding to another bus-compatible device on the first bus.   8. The bridge according to claim 7, further comprising a register for storing the predetermined list.   8. The bridge of claim 7, wherein the first interface comprises a first register for storing the predetermined list, and the second interface comprises a second register for storing the predetermined list.   9. The bridge of claim 8, wherein the register is operable to establish a base address for the first bus of one or more bus compatible devices on the second bus.   5. A bridge according to claim 1, 2 or 4, comprising a register for defining a base address of one or more bus compatible devices on the second bus to the first bus.   The bridge according to claim 1, 2 or 4, wherein the first interface and the second interface allow communication between bus compatible devices on the second bus without going through the first bus. .   Has the authority to give permission to use the second bus to either one of the second interface or the bus-compatible device on the second bus, but has the right to give permission to use the first bus The bridge of claim 12, comprising no arbitration device.   The bridge of claim 1, 2 or 4, wherein the first interface and the second interface comprise first and second programmable devices connected between the link and the first bus and the second bus.   The first interface and the second interface comprise first and second application specific integrated circuit devices respectively connected between the link and the first bus and the second bus. The described bridge.   16. The bridge of claim 15, wherein the first and second application specific integrated circuit devices are of the same configuration, each having a control pin for receiving a control signal establishing operation in one of two modes.   Each of the first and second application specific integrated circuit devices is enabled only when it is the second application specific integrated circuit device, and is either the second interface or a bus compatible device on the second bus. 17. The bridge according to claim 16, further comprising an arbitration device that is authorized to grant permission to use the second bus to one and not authorized to grant permission to use the first bus.   16. The bridge of claim 15, wherein the first and second application specific integrated circuit devices comprise a plurality of port means coupled to the second interface comprising a plurality of input / output boats.   5. The bridge according to claim 1, 2 or 4, wherein the processor is interrupt-driven and the second interface can transmit an interrupt signal for interrupting the processor to the first interface via the link. .   20. The bridge of claim 19, wherein the processor is responsive to an error signal and the second interface transmits an error signal addressed to the processor over the link.   The first bus operates at a predetermined clock speed, and the link propagates data between the first interface and the second interface having a bit transfer rate greater than the predetermined clock speed. The bridge according to claim 1, 2 or 4.   The bridge of claim 21, wherein the set of links is a set of unidirectional links that carry information in opposite directions.   23. The bridge of claim 22, wherein the unidirectional link is driven for different signal transfers.   The bridge according to claim 1, 2 or 4, wherein the second bus is a PCI bus.   The second interface is responsive to a transaction from the link representing an initial read request to send back the second bus over the link for the purpose of satisfying pending and expected transactions. 5. A bridge according to claim 1, 2 or 4, operable to fetch and prefetch data from a requirement of one of the above bus compatible devices.   The first interface and the second interface are substantially the same type of addressing used by at least one bus-compatible device on the second bus to access a device on the second bus. A bridge as claimed in claim 1, 2 or 4, operable on the second bus to permit addressing of one or more bus compatible devices on the first bus. .

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