JP2011018137A - Low power consumption circuit design method and semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce power consumption of a semiconductor integrated circuit device, with respect to a low power consumption circuit design method and the semiconductor integrated circuit device.SOLUTION: A processor part 1 of a semiconductor integrated circuit device 80 is supplied with a plurality of power source voltages lower than a power source voltage of 3.3 V supplied to a peripheral part 3. The processor part 1 is composed of a first circuit area to which a power source voltage of 1.2 V is supplied, a second circuit area to which a power source voltage of 1.0 V is supplied, and a third circuit area to which a power source voltage of 0.8 V is supplied. The first to third circuit areas are each provided with a logic circuit composed of a high threshold transistor and a logic circuit composed of a low threshold transistor.

Description

  The present invention relates to a low power consumption circuit design method and a semiconductor integrated circuit device.

  Multifunctionality, high functionality, and miniaturization are progressing in consumer and industrial electronic devices. As a result, in system LSIs and SoCs (System on a Chip) used in electronic devices, the total number of elements increases due to the increase in circuit scale, and the operating frequency increases, resulting in a rapid increase in power consumption. There is an increasing demand for lower power consumption. In particular, system LSIs and SoCs installed in digital consumer devices such as mobile phones, PDAs, and digital cameras have a strong demand for low power consumption. In order to reduce power consumption, it is very important to reduce dynamic power during operation and leakage power during standby. Various measures have been studied and put into practical use for reducing leakage power during standby, but clock gating technology is mainly employed for reducing dynamic power during operation ( For example, see Patent Document 1.)

  In the clock gating technique described in Patent Document 1 or the like, there is a problem that power consumption cannot be reduced when the system is fully operating, and leakage power is generated in a circuit portion that is not operating. . In addition, the technology to variably control the frequency and power supply voltage is effective to reduce dynamic power during operation, but there is a problem that the degree of design difficulty is high, and it is very difficult to expand widely to various products. It is.

JP 2009-53989 A

  An object of the present invention is to provide a low power consumption circuit design technique and a semiconductor integrated circuit device capable of reducing power consumption.

  A low power consumption circuit design method according to an aspect of the present invention is an LSI low power consumption circuit design method in which a plurality of libraries having different power supply voltages are provided, and the library includes a plurality of transistors having different threshold voltages. The method includes a step of selecting a power supply voltage and a threshold voltage of a transistor to be applied to each circuit region of the LSI from logic synthesis and timing analysis of the LSI, and a step of arranging and wiring the LSI.

  Further, in the semiconductor integrated circuit device of one embodiment of the present invention, the peripheral portion to which the first power supply voltage is supplied, the second power supply voltage lower than the first power supply voltage is supplied, and the threshold voltage of the transistor is A first circuit area in which a plurality of different logic circuits are provided, and a third power supply voltage lower than the second power supply voltage is supplied, and a plurality of logic circuits in which the threshold voltages of the transistors are different are provided. And a third circuit region to which a fourth power supply voltage lower than the third power supply voltage is supplied and a plurality of logic circuits having different threshold voltages of the transistors is provided, and the peripheral section And a core portion that operates at a higher speed.

  According to the present invention, it is possible to provide a low power consumption circuit design method capable of reducing power consumption and a semiconductor integrated circuit device.

1 is a block diagram showing a schematic configuration of a semiconductor integrated circuit device according to Embodiment 1 of the present invention. FIG. 3 is a diagram illustrating a layout of a processor unit according to the first embodiment of the invention. The figure which shows the operating frequency for every area | region of the processor part which concerns on Example 1 of this invention. The figure which shows the power consumption for every area | region of the processor part which concerns on Example 1 of this invention. 3 is a flowchart showing a low power consumption circuit design of the semiconductor integrated circuit device according to the first embodiment of the present invention. 3 is a flowchart showing logic synthesis & timing analysis according to the first embodiment of the present invention. FIG. 6 is a block diagram illustrating a schematic configuration of a semiconductor integrated circuit device according to a second embodiment of the invention. FIG. 6 is a block diagram illustrating a schematic configuration of a semiconductor integrated circuit device according to a third embodiment of the invention.

  Embodiments of the present invention will be described below with reference to the drawings.

  First, a low power consumption circuit design method and a semiconductor integrated circuit device according to Embodiment 1 of the present invention will be described with reference to the drawings. 1 is a block diagram showing a schematic configuration of a semiconductor integrated circuit device, FIG. 2 is a diagram showing a layout of a processor unit, FIG. 3 is a diagram showing an operating frequency for each region of the processor unit, and FIG. 4 is a diagram for each region of the processor unit. It is a figure which shows power consumption. In this embodiment, three types of high potential side power supplies are supplied to the processor unit.

  As shown in FIG. 1, a semiconductor integrated circuit device 80 includes a processor unit (core unit) 1, a data transfer unit 2, a peripheral unit 3, and terminals Pad1 to Pad4. The semiconductor integrated circuit device 80 is a SoC (System on a Chip), and is used in a digital consumer device with reduced power consumption, such as a mobile phone. The semiconductor integrated circuit device 80 is also called a consumer system LSI.

  The semiconductor integrated circuit device 80 is supplied with four types of high potential side power supplies VDD1 to VDD4 from the outside. The high potential side power supply VDD1 is supplied to the peripheral unit 3 through the terminal Pad1. The high-potential-side power supply VDD2 is supplied to the processor unit (core unit) 1 and the data transfer unit 2 via the terminal Pad2. The high potential side power supply VDD3 is supplied to the processor unit (core unit) 1 through the terminal Pad3. The high potential side power supply VDD4 is supplied to the processor unit (core unit) 1 through the terminal Pad4.

Here, the relationship among the voltage Vdd1 of the high potential side power supply VDD1, the voltage Vdd2 of the high potential side power supply VDD2, the voltage Vdd3 of the high potential side power supply VDD3, and the voltage Vdd4 of the high potential side power supply VDD4 is
Vdd1 >>Vdd2>Vdd3> Vdd4 ... Formula (1)
Set to The voltage Vdd1, the voltage Vdd2, the voltage Vdd3, and the voltage Vdd4 vary depending on the technology node used in the semiconductor integrated circuit device 80, and an optimum voltage corresponding to the technology node is appropriately selected. Here, the voltage Vdd1 is selected to be 3.3V, the voltage Vdd2 is 1.2V, the voltage Vdd3 is 1.0V, and the voltage Vdd4 is 0.8V.

The relationship between the operating frequency f _FNCa of the processor unit (core unit) 1, the operating frequency f _{FNCb of} the data transfer unit 2, and the operating frequency f _{FNCc of} the peripheral unit 3 is
f _FNCa > f _FNCb > f _{FNCc ···} Equation (2)
Set to

The power consumption P of the semiconductor integrated circuit device 80 is
P ≒ {(A x Nt) · f · C · VDD ² } + (Nt · Ileak · VDD) ··· Equation (3)
It is expressed. {(A × Nt) · f · C · VDD ² } is dynamic power (power during operation), (Nt · Ileak · VDD) is leakage power (standby power), A is an activation rate, Nt is the total number of gates, f is an operating frequency, C is a capacity, VDD is a power supply voltage, and Ileak is a leakage current during standby. The dynamic power (power during operation) is proportional to the square of the power supply voltage, and the leakage power (standby power) is proportional to the product of the leakage current and the power supply voltage.

The relationship among the power consumption P of the semiconductor integrated circuit device 80, the power consumption P11 of the processor unit (core unit) 1, the power consumption P12 of the data transfer unit 2, and the power consumption P13 of the peripheral unit 3 is
P = P11 + P12 + P13 ... Formula (4)
P11 >>P12> P13 ... Formula (5)
It is expressed.

  The peripheral unit 3 transmits external information to the processor unit (core unit) 1 and transmits information processed by the processor unit (core unit) 1 to the outside. The data transfer unit 2 is provided with a DMA (Direct Memory Access) controller 15. The DMA controller 15 transfers the memory information into the chip without going through the CPU. The data transfer unit 2 transfers the memory information stored in the external memory to the processor unit (core unit) 1 and transfers the memory information to the inside via the DMA controller 15.

  The processor unit (core unit) 1 includes a CPU 11, a DSP 12, a cache memory 13, and a cache memory 14. Although the processor unit (core unit) 1 varies depending on the specifications of the semiconductor integrated circuit device 80, the processor unit (core unit) 1 operates at a high speed at a frequency of 100 MHz or more in a digital consumer device application with low power consumption.

  A CPU (Central Processing Unit) 11 is a master device that performs overall control of the semiconductor integrated circuit device 80. A DSP (Digital Signal Processor) 12 is a slave device that executes arithmetic processing based on an instruction from the CPU 11. The cache memory 13 operates in accordance with an instruction from the CPU 11 and is, for example, an L1 or L2 cache memory, and includes an SRAM. The cache memory 14 operates in accordance with an instruction from the CPU 11 and is, for example, an L3 or L4 cache memory, and is composed of an SDRAM that is slower than an SRAM.

In the processor unit (core unit) 1, not all circuits necessarily operate at the operating frequency f _FNCa . For example, separating a first circuit area which operates at an operating frequency f _FNCA, a second circuit area which operates slower than the operating frequency f _FNCA, the third circuit region operates slower than the second circuit region be able to.

  Specifically, as shown in FIG. 2, the processor unit (core unit) 1 includes a power supply region 21 to which the high potential side power supply VDD2 is supplied, a power supply region 25 to which the high potential side power supply VDD2 is supplied, It is divided into a power supply region 22 to which the potential side power supply VDD3 is supplied, a power supply region 24 to which the high potential side power supply VDD3 is supplied, and a power supply region 23 to which the high potential side power supply VDD4 is supplied. The power supply regions 21 and 25 correspond to the first circuit region, the power supply regions 22 and 24 correspond to the second circuit region, and the power supply region 23 corresponds to the third circuit region.

  As shown in the above equation (3), the dynamic power in the circuit area is proportional to the square of the power supply voltage, so that it is possible to reduce the dynamic power by appropriately selecting the power supply voltage corresponding to the operating frequency as appropriate. Become. Further, since the leakage power in the circuit area is proportional to the product of the power supply voltage and the leakage current, it is possible to reduce the leakage power by appropriately selecting the power supply voltage as appropriate.

  The power supply region 21 is provided with a logic circuit that operates at 1.2 V and a memory cell 27a. For example, a CTS buffer CTSBU, a flip-flop FF1, a peripheral logic circuit (a decoder, a buffer, a sense amplifier, a memory controller, etc.) of a memory cell 27a (not shown) and the like are provided. For these circuits, any one of the threshold voltages (Vth (high) / Vth (low)) of two types of transistors is appropriately selected.

  The power supply region 25 is provided with a logic circuit and a memory cell 27d operating at 1.2V. For example, a NOR circuit NOR2, a flip-flop FF6, a register 28, peripheral logic circuits (a decoder, a buffer, a sense amplifier, a memory controller, etc.) of a memory cell 27d (not shown) and the like are provided. For these circuits, any one of the threshold voltages (Vth (high) / Vth (low)) of two types of transistors is appropriately selected.

  The power supply region 22 is provided with a logic circuit that operates at 1.0 V and a memory cell 27b. For example, a flip-flop FF2, an OR circuit OR1, an inverter INV1, peripheral logic circuits (a decoder, a buffer, a sense amplifier, a memory controller, etc.) of a memory cell 27b (not shown), and the like are provided. For these circuits, any one of the threshold voltages (Vth (high) / Vth (low)) of two types of transistors is appropriately selected.

  The power supply region 24 is provided with a logic circuit that operates at 1.0 V and a memory cell 27 c. For example, a flip-flop FF4, an AND circuit AND1, a flip-flop FF5, peripheral logic circuits (a decoder, a buffer, a sense amplifier, a memory controller, etc.) of a memory cell 27c (not shown), and the like are provided. As for these circuits, any one of the threshold voltages (Vth (high) / Vth (low)) of two types of transistors is appropriately selected.

  The power supply region 23 is provided with a logic circuit that operates at 0.8V. For example, a NAND circuit NAND1, a flip-flop FF3, a NOR circuit NOR1, an inverter INV2, and the like are provided. For these circuits, any one of the threshold voltages (Vth (high) / Vth (low)) of two types of transistors is appropriately selected.

  A signal output from the circuit in the power supply region 21 is directly input to the circuit in the power supply region 22. The signal output from the circuit in the power supply region 22 is level-shifted (the signal level is increased) by the level sister 26a, and the level-shifted signal is input to the circuit in the power supply region 21.

  A signal output from the circuit in the power supply region 22 is directly input to the circuit in the power supply region 23. The signal output from the circuit in the power supply region 23 is level-shifted (the signal level is increased) by the level sister 26b, and the level-shifted signal is input to the circuit in the power supply region 22.

  The signal output from the circuit in the power supply region 23 is level-shifted (the signal level is increased) by the level sister 26 c and the level-shifted signal is input to the circuit in the power supply region 24. A signal output from the circuit in the power supply region 24 is directly input to the circuit in the power supply region 23.

  The signal output from the circuit in the power supply region 24 is level-shifted (the signal level is increased) by the level sister 26d, and the level-shifted signal is input to the circuit in the power supply region 25. A signal output from the circuit in the power supply region 25 is directly input to the circuit in the power supply region 24.

  Note that logic circuits are classified into combinational circuits and sequential circuits. The combinational circuit includes a logic gate (INV, AND, OR, NAND, NOR, XOR, etc.), a decoder, an encoder, a MUX, and the like. The sequential circuit includes a flip-flop, a counter, a shift register, and the like.

As shown in FIG. 3, the operating frequency f _FNC1 of the circuits in the power supply areas 21 and 25 driven by 1.2 V, the operating frequency f _FNC2 of the circuits in the power supply areas 22 and 24 driven by 1.0 V, 0.8 V The relationship of the operating frequency f _FNC3 of the circuit in the power supply area 23 to be driven is
f _FNC1 > f _FNC2 > f _{FNC3 .....} Formula (6)
It is expressed. For this reason, the margin A of the circuits in the power supply regions 21 and 25 driven by 1.2 V with respect to the target operating frequency of the core portion, and the margin of the circuits of the power supply regions 22 and 24 driven by 1.0 V with respect to the target operating frequency of the core The relationship between the degree C and the margin C of the circuit of the power supply region 23 driven by 0.8 V with respect to the core target operating frequency is
C >> B >> A ......... Formula (7)
It is expressed.

  As a result, as compared with the case where the power supply voltage of 1.2 V is supplied to the power supply regions 21 to 25 shown in FIG. 4A, the processor unit (core unit) 1 has 3 as shown in FIG. By supplying various types of power supply voltages, the power consumption of the circuits in the power supply areas 22 and 24 is reduced (power reduction (1)), and the power consumption of the circuits in the power supply area 23 is reduced (power reduction (2). )).

Specifically, the reduction amount ΔP1 in the power reduction (1) is
ΔP1 ≒ {(A × Nt1) ・ f _FNC2・ C1 ・ (1.2−1.0) ² } + {Nt1 ・ Ileak ・ (1.2−1.0)} ・ ・ Formula (8)
It is expressed. Reduction amount ΔP2 in power reduction (2) is
ΔP2 ≒ {(A × Nt2) ・ f _FNC3・ C2 ・ (1.2−0.8) ² } + {Nt2 ・ Ileak ・ (1.2−0.8)} ・ ・ Formula (9)
It is expressed. Nt1 and Nt2 are the total number of gates of the circuit in the power supply region, and C1 and C2 are capacitances in the power supply region.

  Next, a low power consumption circuit design method for a semiconductor integrated circuit device will be described with reference to the drawings. FIG. 5 is a flowchart showing low power consumption circuit design of the semiconductor integrated circuit device, and FIG. 6 is a flowchart showing logic synthesis & timing analysis.

  As shown in FIG. 5, first, an RTL (Register Transfer Level) description using HDL (Hardware Description Language) is synthesized from an operation description close to a software program based on system designed information (step S1). .

  Next, the RTL description is refined, and the logic analysis and timing analysis around the gate-level logic circuit and the memory cell are performed (step S2).

  Specifically, as shown in FIG. 6, three types of libraries used for logic analysis & timing analysis are prepared. The 0.8V library 31 includes a logic circuit for a transistor threshold voltage (Vth (high)) and a logic circuit for a transistor threshold voltage (Vth (low)). In the 1.0 V library 32, a logic circuit of a transistor threshold voltage (Vth (high)) and a logic circuit of a transistor threshold voltage (Vth (low)) are prepared. In the 1.2V library 33, a logic circuit of a transistor threshold voltage (Vth (high)) and a logic circuit of a transistor threshold voltage (Vth (low)) are prepared.

  First, logic synthesis is started using the logic circuit of the threshold voltage (Vth (high)) of the transistor of the 0.8V library 31 having the lowest voltage (step S21). After the logic synthesis, timing analysis is performed on the logic-synthesized circuit area (step S22). It is determined whether the timing of the logic-synthesized circuit area falls within a desired timing range. If the determination of all circuit areas is OK, the process proceeds to the next step. If there is an NG circuit area, the process returns to step S21, and logic synthesis & timing analysis is performed using the logic circuit of the threshold voltage (Vth (low)) of the transistor of the 0.8V library 31 to bring it into the desired timing range. Determine if it is in. If the determination of all circuit areas is OK, the process proceeds to the next step. If there is an NG circuit area, the process proceeds to the next logic synthesis & timing analysis (step S23).

  Next, logic synthesis is started using the logic circuit of the threshold voltage (Vth (high)) of the transistors in the 1.0 V library 32 (step S24). After the logic synthesis, timing analysis is performed on the logic-synthesized circuit area (step S25). It is determined whether the timing of the logic-synthesized circuit area is within a desired timing range. If the determination of all circuit areas is OK, the process proceeds to the next step. If there is an NG circuit area, the process returns to step S24 to perform logic synthesis & timing analysis using the logic circuit of the threshold voltage (Vth (low)) of the transistor of the 1.0V library 32, and to the desired timing range. Determine if it is in. If the determination of all circuit areas is OK, the process proceeds to the next step. When there is an NG circuit area, the process proceeds to the next logic synthesis & timing analysis (step S26).

  Subsequently, logic synthesis is started using the logic circuit of the threshold voltage (Vth (high)) of the transistors in the 1.2 V library 33 (step S27). After the logic synthesis, timing analysis is performed on the logic-synthesized circuit area (step S28). It is determined whether the timing of the logic-synthesized circuit area is within a desired timing range. If the determination of all circuit areas is OK, the process proceeds to the next step. If there is an NG circuit area, the process returns to step S24 to perform logic synthesis and timing analysis using the logic circuit of the threshold voltage (Vth (low)) of the transistor in the 1.2V library 33, and within the desired timing range. Determine if it is in. If the determination of all circuit areas is OK, the process proceeds to the next step. If there is a circuit area whose determination is NG, the process returns to the RTL description (step S29).

  Then, after logic synthesis & timing analysis, a level shifter for level-shifting the signal level is inserted between the circuit region having a low power supply voltage and the circuit region having a high power supply voltage (step S3). After the level shifter is inserted, layout and placement and routing are performed (step S4).

As described above, in the low power consumption circuit design method and the semiconductor integrated circuit of this embodiment, the processor unit (core unit) 1, the data transfer unit 2, the peripheral unit 3, and the terminals Pad 1 to 4 are provided. The peripheral unit 3 is supplied with a power supply voltage of 3.3 V via a terminal Pad 1, and the processor unit (core unit) 1 is supplied with a power supply voltage of 1.2 V via a terminal Pad 2 and via a terminal Pad 3. Then, a power supply voltage of 1.0 V is supplied, and a power supply voltage of 0.8 V is supplied via the terminal Pad4. A power supply voltage of 1.2 V is supplied to the data transfer unit 2 via a terminal Pad2. The processor unit 1 includes a first circuit region to which a power supply voltage of 1.2 V is supplied, a second circuit region to which a power supply voltage of 1.0 V is supplied, and a third circuit region to which a power supply voltage of 0.8 V is supplied. It consists of the circuit area. In the first to third circuit areas, a logic circuit composed of a high threshold transistor and a logic circuit composed of a low threshold transistor are provided. The logic synthesis and timing analysis of the low power consumption circuit design is started by using a logic circuit having the lowest power supply voltage and a high threshold transistor.

  For this reason, reduction in dynamic power during operation and reduction in leakage power during standby can be achieved. Further, power consumption can be reduced even when the system is fully operating.

  In this embodiment, three types of high potential side power supplies having a voltage lower than that of the high potential side power supply VDD1 are supplied to the processor unit (core unit) 1, but two types of high potential side power supplies are supplied. Also good. The library prepares two types of threshold voltages of transistors (Vth (high) and Vth (low)), but three types of threshold voltages of transistors (Vth (high), Vth (medium), and Vth (low)). ) May be prepared.

  Next, a semiconductor integrated circuit device according to Embodiment 2 of the present invention will be described with reference to the drawings. FIG. 7 is a block diagram showing a schematic configuration of the semiconductor integrated circuit device. In this embodiment, the high potential power source supplied to the processor unit is generated inside the chip.

  In the following, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted, and only different portions are described.

  As shown in FIG. 7, the semiconductor integrated circuit device 81 includes a processor unit (core unit) 1, a data transfer unit 2, a peripheral unit 3, regulators 41 to 43, and a terminal Pad1. The semiconductor integrated circuit device 81 is a SoC (System on a Chip), and is used for a digital consumer device with low power consumption, such as a mobile phone.

  The semiconductor integrated circuit device 81 is supplied with a high potential side power supply VDD1 from the outside. The high potential side power supply VDD1 is supplied to the peripheral unit 3 through the terminal Pad1.

  The regulator 41 is provided between the terminal Pad1, the processor unit (core unit) 1 and the data transfer unit 2, and generates a high potential side power source VDD2 obtained by stepping down the high potential side power source VDD1 to generate the processor unit (core unit) 1 and This is supplied to the data transfer unit 2.

  The regulator 42 is provided between the terminal Pad 1 and the processor unit (core unit) 1, generates a high potential side power source VDD 3 obtained by stepping down the high potential side power source VDD 1, and supplies it to the processor unit (core unit) 1.

  The regulator 43 is provided between the terminal Pad 1 and the processor unit (core unit) 1, generates a high potential side power supply VDD 4 obtained by stepping down the high potential side power supply VDD 1, and supplies it to the processor unit (core unit) 1. For the regulators 41 to 43, for example, a synchronous rectification step-down DC-DC converter or an asynchronous rectification step-down DC-DC converter is used. By providing the regulators 41 to 43 in the semiconductor integrated circuit device 81, voltage fluctuations of the high potential side power supplies VDD2 to VDD4 can be significantly suppressed.

  As described above, the semiconductor integrated circuit device according to the present embodiment includes the processor unit (core unit) 1, the data transfer unit 2, the peripheral unit 3, the regulators 41 to 43, and the terminal Pad1. The regulator 41 steps down a 3.3V power supply voltage supplied from the outside to generate a 1.2V power supply voltage, and supplies the 1.2V power supply voltage to the processor unit (core unit) 1 and the data transfer unit 2. The regulator 42 steps down a 3.3V power supply voltage supplied from the outside to generate a 1.0V power supply voltage and supplies it to the processor unit (core unit) 1. The regulator 43 steps down a 3.3V power supply voltage supplied from the outside to generate a 0.8V power supply voltage, and supplies it to the processor unit (core unit) 1.

  For this reason, reduction in dynamic power during operation and reduction in leakage power during standby can be achieved. Further, power consumption can be reduced even when the system is fully operating.

  Next, a semiconductor integrated circuit device according to Embodiment 3 of the present invention will be described with reference to the drawings. FIG. 8 is a block diagram showing a schematic configuration of the semiconductor integrated circuit device. In this embodiment, three types of high-potential-side power are also supplied to the data transfer unit.

  In the following, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted, and only different portions are described.

  As shown in FIG. 8, the semiconductor integrated circuit device 82 includes a processor unit (core unit) 1, a data transfer unit 2, a peripheral unit 3, and terminals Pad 1 to 4. The semiconductor integrated circuit device 82 is a SoC (System on a Chip), and is used for a digital consumer device with low power consumption, for example, a mobile phone.

In the data transfer unit 2, not all circuits necessarily operate at the operating frequency f _FNCb . For example, it is _separated into a fourth circuit region that operates at the operating frequency f _FNCb, a fifth circuit region that operates at a lower speed than the operating frequency f _FNCb, and a sixth circuit region that operates at a lower speed than the fifth circuit region. be able to. The fourth circuit region is supplied with the high potential power source VDD2, the fifth circuit region is supplied with the high potential power source VDD3, and the sixth circuit region is supplied with the high potential power source VDD4.

  When the high potential side power supply supplied to the fifth and sixth circuit regions is lowered, the dynamic power can be reduced in proportion to the square of the difference between the power supply voltages, and the Stein proportional to the product of the power supply voltage difference and the leakage current can be achieved. Reduction of buy power can be achieved respectively.

  As described above, the semiconductor integrated circuit device according to the present embodiment includes the processor unit (core unit) 1, the data transfer unit 2, the peripheral unit 3, and the terminals Pad 1 to 4. The peripheral unit 3 is supplied with a power supply voltage of 3.3 V via a terminal Pad 1, and the processor unit (core unit) 1 is supplied with a power supply voltage of 1.2 V via a terminal Pad 2 and via a terminal Pad 3. Then, a power supply voltage of 1.0 V is supplied, and a power supply voltage of 0.8 V is supplied via the terminal Pad4. The data transfer unit 2 is supplied with a power supply voltage of 1.2 V through the terminal Pad2, supplied with a power supply voltage of 1.0 V through the terminal Pad3, and supplied with a power supply voltage of 0.8 V through the terminal Pad4. Is done. The data transfer unit 2 includes a fourth circuit area to which a 1.2V power supply voltage is supplied, a fifth circuit area to which a 1.0V power supply voltage is supplied, and a 0.8V power supply voltage to be supplied. 6 circuit areas. In the first to sixth circuit areas, a logic circuit composed of a high threshold transistor and a logic circuit composed of a low threshold transistor are provided.

  For this reason, reduction in dynamic power during operation and reduction in leakage power during standby can be achieved. Further, power consumption can be reduced even when the system is fully operating.

  The present invention is not limited to the above-described embodiments, and various modifications may be made without departing from the spirit of the invention.

  In the embodiment, the present invention is applied to SoC, but can also be applied to SiP, MCP, laminated W-CSP, and the like.

The present invention can be configured as described in the following supplementary notes.
(Supplementary Note 1) A peripheral portion to which a first power supply voltage is supplied via a first terminal, a second power supply voltage lower than the first power supply voltage is supplied via a second terminal, and a transistor A first circuit region in which a plurality of logic circuits having different threshold voltages are provided, and a third power supply voltage lower than the second power supply voltage is supplied via a third terminal, and the threshold voltage of the transistor is A second circuit region in which a plurality of different logic circuits are provided, and a fourth power supply voltage lower than the third power supply voltage is supplied through the fourth terminal, and a plurality of threshold voltages of the transistors are different from each other. A semiconductor integrated circuit device comprising: a third circuit region provided with a logic circuit; and a core unit operating at a higher speed than the peripheral unit.

(Supplementary Note 2) A first regulator that receives a first power supply voltage via a first terminal and generates a second power supply voltage obtained by stepping down the first power supply voltage, and the first power supply voltage A first regulator that receives the first power supply voltage, the second regulator generating a third power supply voltage lower than the second power supply voltage, and the first power supply voltage; A third regulator that lowers the voltage and generates a fourth power supply voltage lower than the third power supply voltage, a peripheral unit to which the first power supply voltage is supplied, and the second power supply voltage are supplied, A first circuit region in which a plurality of logic circuits having different threshold voltages of the transistors is provided, and a second circuit region in which a plurality of logic circuits having different threshold voltages of the transistors are provided by supplying the third power supply voltage. And the fourth Power supply voltage is supplied, and a third circuit region in which a plurality of logic circuits having different threshold voltages of the transistors are respectively provided, a semiconductor integrated circuit device comprising a core portion which operates at a higher speed than the peripheral portion.

1 Processor part (core part)
2 Data transfer unit 3 Peripheral unit 11 CPU
12 DSP
13, 14 Cache memory 15 DMA controller 21-25 Power supply area 31 0.8V library 32 1.0V library 33 1.2V library 41-43 Regulator 81-82 Semiconductor integrated circuit device AND1 AND circuit CLK clock CTSBU CTS buffer FF1 _FF6 Flip-flops f _{FNC1 to} f _FNC3 Operating frequency INV1, INV2 Inverter NAND1 NAND circuit NOR1, NOR2 NOR circuit OR1 OR circuit Pad1-Pad4 terminals VDD1-VDD4 High potential side power supply

Claims (5)

A plurality of libraries having different power supply voltages are provided, and the library is a low power consumption circuit design method for LSI in which a plurality of transistors having different threshold voltages are prepared,
Selecting a power supply voltage and a threshold voltage of a transistor to be applied to each circuit area of the LSI from logic synthesis and timing analysis of the LSI;
Performing the placement and routing of the LSI;
A low power consumption circuit design method characterized by comprising: In the step of selecting the power supply voltage and the threshold voltage of the transistor,
Start logic synthesis using the library with the lowest power supply voltage and the highest transistor threshold voltage. If the timing analysis decision is NG, use a transistor with a threshold voltage lower than the highest threshold voltage. A first step of performing logic synthesis and timing analysis again,
For the circuit area determined as NG in the timing analysis in the first step, logic synthesis is started using a library having a power supply voltage higher than the lowest power supply voltage and the highest threshold voltage of the transistor, If the determination result of the timing analysis is NG, a second step of performing logic synthesis and timing analysis again using a transistor having a threshold voltage lower than the highest threshold voltage;
The low-power consumption circuit design method according to claim 1, further comprising: Among the plurality of power supply voltages, the signal level is between the first circuit region to which the first power supply voltage is supplied and the second circuit region to which the second power supply voltage higher than the first power supply voltage is supplied. Inserting a level shifter that shifts the level higher
The low-power-consumption circuit design method according to claim 1, further comprising: A peripheral unit to which a first power supply voltage is supplied;
A first circuit region in which a plurality of logic circuits each having a different threshold voltage of a transistor are provided, the second power supply voltage being lower than the first power supply voltage; and a third lower than the second power supply voltage Are supplied with a second circuit region in which a plurality of logic circuits having different threshold voltages are provided, and a fourth power supply voltage lower than the third power supply voltage is supplied. A third circuit region provided with a plurality of different logic circuits, and a core unit that operates at a higher speed than the peripheral unit,
A semiconductor integrated circuit device comprising:   A fourth circuit region provided with a plurality of logic circuits each having a different threshold voltage of the transistor to which the second power supply voltage is supplied; and a plurality of transistors having a different threshold voltage for the transistor to which the third power supply voltage is supplied. A fifth circuit region in which a logic circuit is provided; and a sixth circuit region in which a plurality of logic circuits to which the fourth power supply voltage is supplied and whose threshold voltages are different from each other are provided. 5. The semiconductor integrated circuit device according to claim 4, further comprising a data transfer unit that operates at a high speed and operates at a lower speed than the core unit.

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