JP2011017609A - Defect inspecting apparatus and defect inspecting method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten an inspection time by improving an inspection throughput in a surface defect inspection of a semiconductor substrate.SOLUTION: A defect inspecting apparatus is provided, which includes: a reticle information database 26 for storing reticle information; an inspection result database 27 for storing a defect inspection result; a standard calculating part 24 for calculating an abnormal determination standard on the basis of the defect inspection result; a standard-failure detection count calculating part 23 for calculating detection counts of defect repetition abnormalities which exceed the failure determination standard, by checking the calculated failure determination standard and the defect inspection result; an inspection time calculating part 21 for calculating a time needed for an inspection on the basis of an inspection condition; an failure detection ability calculating part 28 for calculating failure detection counts per unit time; a distribution-failure detection limit thinning-out rate calculating part 25 for calculating a thinning-out rate in which a distribution failure being partially distributed in a surface of the semiconductor substrate is detected at an optional detection rate or above; and an inspection area calculating part 22 for determining an inspection area by automatically setting an inspection zone having the maximum failure detection counts per unit inspection time.

Description

  The present invention relates to a defect inspection apparatus and a defect inspection method, and more particularly to an improvement in operating efficiency of a semiconductor product manufacturing facility in a semiconductor product manufacturing process. More specifically, the present invention relates to a defect inspection apparatus and a defect inspection method for inspecting a defect state that leads to a defect of a semiconductor product in a defect inspection process of a circuit pattern formed on a semiconductor substrate such as a silicon wafer by a defect inspection apparatus. .

  Conventionally, a defect inspection on a semiconductor substrate such as a silicon wafer in a manufacturing process of a semiconductor device is performed using an optical defect inspection apparatus as disclosed in Patent Document 1 and Patent Document 2. Although the defect inspection in the manufacturing process of the semiconductor product using this optical defect inspection apparatus is not specified in the above-mentioned Patent Documents 1 and 2, it is basically a specification for performing a full inspection, based on the specification. The entire surface of the silicon wafer is inspected.

In this type of defect inspection, in recent years, a minute defect in a minute pattern has been inspected, and such a defect inspection requires a high-magnification detection optical system.
In addition, the inspection area has increased with the increase in the diameter of silicon wafers.

JP 2000-315712 A JP-A-3-167456

  However, since the range that can be measured by a single inspection becomes small as a result of increasing the magnification, the inspection throughput is reduced, and the entire surface inspection requires a great deal of time. In addition, as the diameter of the semiconductor substrate is further increased, if the inspection area per unit time is the same, as the area of the semiconductor substrate such as a silicon wafer increases, it takes time corresponding to the ratio of the area of the conventional semiconductor substrate. As a result, an increase in the overall inspection time is spurred.

  In addition to the above, since the defect inspection apparatus with high detection sensitivity is expensive, not only the inspection throughput is reduced but also the inspection cost is increased, leading to an increase in the manufacturing cost of the semiconductor device.

Here, an optical defect inspection apparatus represented by Patent Document 2 has a basic configuration as shown in FIG.
That is, in the defect inspection by the optical defect inspection apparatus, the stage 2 on which the semiconductor substrate 1 such as a silicon wafer is mounted is moved in the XY directions according to the signal from the stage control unit 3 while executing the inspection operation described later. It is done by letting. Here, the inspection operation irradiates illumination from the illumination system 4 onto an inspection area on the semiconductor substrate 1 that is arbitrarily set in advance, forms an image of reflected light from the inspection area by the detection optical system 5, The image sensor 6 receives the light and converts it into an analog electrical signal. The AD converter 7 converts the signal into a digital signal. The detected digital image signal is stored in the CPU 9 as a reference digital image signal. The comparison inspection unit 8 compares and detects the difference as a defect such as a foreign object.

In this case, the inspection area, a threshold value for determining the comparison inspection result and explicitly expressing the difference as a difference, and the like are set by the inspection recipe manager 10 as an inspection recipe.
However, the inspection recipe manager 10 does not have a function of calculating and determining a threshold value for determining an inspection area or a defect and proposing it to an operator or engineer who operates the defect inspection apparatus. Therefore, in the defect inspection using the conventional defect inspection device, the engineer who actually operates determines and inputs the inspection parameters such as the inspection area and threshold based on the result derived from another system, and explicitly There is only a means to set in the inspection recipe manager 10.

  The inspection parameters such as inspection areas and thresholds set by this engineer are based on enormous amounts of data, so it is common to calculate by summing up the results of sampling for a certain period of time. It was difficult to reflect the state of the place where the semiconductor substrate to be processed was reflected in the inspection recipe.

  A general in-line type defect inspection is performed in a process as shown in FIG. 9 (main processes are illustrated). First, (a) a silicon wafer of the same type in a lot in a product to be inspected is extracted and a full inspection is performed. Next, (b) a newly increasing defect is identified by overlay analysis of the defect map. (C) The defect is categorized based on the shape and the like by a SEM (Scanning Electron Microscope) review device or the like. The category classification in this case is directly related to the degree of influence of defects on the yield of the semiconductor device. (D) For the defects classified into categories, the presence / absence of each chip of the semiconductor device is confirmed for each defect category, and the number of chips having defects in the corresponding category is counted (Defective Die Count, usually abbreviated as DDC). The increase / decrease trend of the count is managed by an SPC (Statistical Process Control) method or the like, and an abnormal value with respect to the management standard is detected.

  Even in this full-scale inspection, if the number of detected abnormalities, the elapsed time, and the number of samples taken are analyzed, the tendency shown in FIG. 10 is shown. From this result, it can be seen that the entire surface inspection is not necessarily an efficient defect inspection method.

  From the above results, it was clear that thinning inspection is one of the effective means for increasing inspection throughput, but until now, optimization of thinning area and thinning method as shown above Because we could not build a concrete environment that realizes the optimization and optimization, we had to use a method with low reliability by sacrificing accuracy using methods such as statistical prediction.

  The present invention solves the above problems, and provides a defect inspection apparatus and a defect inspection method capable of improving defect inspection throughput and performing defect inspection with relatively high accuracy and high reliability. It is intended.

  In order to solve the above problems, a defect inspection apparatus of the present invention has an abnormal defect as a semiconductor substrate from a reticle information database that accumulates reticle information, an inspection result database that accumulates defect inspection results, and a defect inspection result. A standard calculation unit that calculates an abnormality determination standard that is a threshold value determined as a standard abnormality detection that compares the calculated abnormality determination standard with a defect inspection result and calculates the number of detections of multiple abnormal defects exceeding the abnormality determination standard Number of cases calculation unit, inspection time calculation unit that calculates the time required for inspection from inspection conditions, abnormality detection capability calculation unit that calculates the number of abnormality detections per unit time, and defects in full inspection from within the semiconductor substrate within the standard Distribution anomaly detection that calculates a thinning-out rate that can detect distribution anomalies that occur unevenly in the semiconductor substrate surface exceeding the predetermined limit at an arbitrary detection rate or higher It is intended to and a critical thinning rate calculating unit.

  With this configuration, the inspection recipe is optimized, the inspection time per semiconductor substrate in the defect inspection apparatus is shortened, and the relative throughput is improved. As a result, inspection costs can be reduced. In addition, since the coverage rate (applicable rate) of a variety is improved even in a factory that produces a variety of products in small quantities, the accuracy of the state management of the atmosphere at the production site is improved.

  The defect inspection apparatus of the present invention further calculates an inspection area that automatically sets an inspection area that maximizes the number of detected abnormalities per unit inspection time from the reticle information and accumulated defect inspection results, and determines the inspection area. It is preferable to comprise a part.

  The defect inspection apparatus according to the present invention further provides an inspection area with a thinning rate that exceeds a limit that can detect a distribution abnormality distributed in the semiconductor substrate surface exceeding a predetermined limit in a full-surface inspection at an arbitrary detection rate or more. It is preferable that an inspection area calculation unit to be determined is provided.

  The defect inspection apparatus of the present invention further determines the inspection area so as to cover all the chips in the reticle used for forming the pattern on the semiconductor substrate at the thinning rate derived from the defect inspection apparatus and the defect inspection method. It is preferable to include an inspection area calculation unit.

  Further, the defect inspection method of the present invention creates a plurality of types of thinning inspection patterns obtained by thinning a part of the measurement area from the semiconductor substrate to be inspected based on the reticle information, and the individual inspection based on the defect inspection result information. The number of defects detected in the thinning inspection pattern is calculated, and the threshold value for the number of defects having a large difference value is obtained by subtracting the number of false NG defects that are out of specification at the time of full-column inspection from the number of true NG defects that are out of specification even at the time of full-row inspection. Alternatively, the threshold value of the defect number having a large ratio of the true NG defect number to the false NG defect number is set as a defined value for determining that the semiconductor substrate is not defined, and the maximum value among the standard values of each thinning inspection pattern A difference value or a ratio of the true NG defect number to the erroneous NG defect number is large, and a pattern having the highest thinning rate is set as an optimum thinning inspection pattern.

  Further, the defect inspection method of the present invention creates a plurality of types of thinning inspection patterns obtained by thinning a part of the measurement area from the semiconductor substrate to be inspected based on the reticle information, and the individual inspection based on the defect inspection result information. The number of defects detected in the thinning inspection pattern is calculated, and the threshold value for the number of defects having a large difference value is obtained by subtracting the number of false NG defects that are out of specification at the time of all-column inspection from the number of true NG defects that are out of specification at the time of all-column inspection. Alternatively, a threshold value for the number of defects in which the ratio of the true NG defect number to the false NG defect number is large is set as a specified value for determining that the semiconductor substrate is not specified, and the occurrence of defects exceeds a predetermined limit in the entire surface inspection. A detection limit thinning rate is calculated based on the distribution abnormality state distributed in the semiconductor substrate surface, and the maximum difference value or the number of erroneous NG defects is determined among the standard values of each thinning inspection pattern. That the proportion of true NG number of defects increases, and wherein the thinning rate in the detection limits thinning rate following thinning rate is set as the optimal thinning test pattern highest.

  By using the standard calculation unit that calculates the abnormality determination standard shown above, the standard abnormality detection number calculation unit, the abnormality detection capability calculation unit, and the distribution abnormality detection limit decimation rate calculation unit, the target semiconductor device is provided. When detecting defects on the semiconductor device on the semiconductor substrate, it is possible to create the most efficient inspection pattern.

  However, since this assumes that the defect distribution is uniformly distributed over the entire surface of the semiconductor substrate, further optimization by using reticle information and detection results of distribution anomalies can reduce the negative effect of inspection omissions. The effect to minimize can be expected.

  In addition, if only past inspection results are emphasized, an uninspected area may be generated in a semiconductor substrate in an environment where a certain uneven distribution is prominently generated, which is derived from a defect inspection apparatus and a defect inspection method. By deciding the inspection area to cover all the chips in the reticle used to form the pattern on the semiconductor substrate with the thinning rate, and applying correction to the inspection area for inspecting all the chips, It is possible to prevent a defect inspection from being missed by minimizing the possibility of an uninspected area.

  Since the inspection time can be minimized by using the defect inspection apparatus and the defect inspection method according to the present invention, the increase in the inspection time due to the miniaturization of the target pattern and the increase in the inspection time due to the increase in the inspection area can be suppressed. In addition, it is possible to suppress the inspection cost that increases due to miniaturization and area expansion, and to increase the number of target varieties, so that the quality of the factory as a whole can be improved.

  In addition, in order to realize the same function by the conventional defect inspection apparatus, a plurality of systems for realizing the above function are separately provided and manual cooperation is required. Therefore, it is inferior in reliability and immediacy as compared with the case where the system is configured and operated as a single device as in the present invention. That is, according to the defect inspection apparatus and the defect inspection method of the present invention, not only the inspection cost can be suppressed, but also the reliability and immediacy can be improved.

The block diagram which shows the structure of the defect inspection apparatus which concerns on embodiment of this invention Plan view of a semiconductor substrate (silicon wafer) for which a defect inspection area thinning inspection pattern is created by the defect inspection apparatus Plan view showing an example of the same semiconductor substrate (silicon wafer) A plan view showing four examples of defect inspection area thinning inspection patterns (referred to as thinning patterns in FIG. 4) created by the defect inspection apparatus (A)-(e) is an example of the concept of thinning inspection pattern optimization, (a) is a diagram showing the relationship between the wafer number and the number of defects in all row inspection, and (b) is one-chip row thinning inspection. The figure which shows the relationship between the wafer number and defect number in (c) is a figure which shows the relationship between the wafer number and defect number in (N-1) xn inspection, (d) is a difference value and a standard value. The figure which shows the relationship of (a), The figure which shows the relationship between a difference value and a thinning-out rate The figure which shows the idea of the limit thinning-out inspection pattern with respect to partial distribution in the defect inspection apparatus which concerns on embodiment of this invention The figure which shows the view of inspection pattern optimization when there exists partial distribution in the defect inspection apparatus which concerns on embodiment of this invention Block diagram showing the configuration of a conventional defect inspection apparatus Diagram showing the flow of general defect inspection process Chart showing the relationship between inspection area and number of detected abnormalities

Hereinafter, a defect inspection apparatus and a defect inspection method according to embodiments of the present invention will be described with reference to the drawings.
As shown in FIG. 1, the defect inspection apparatus according to the embodiment of the present invention has a defect inspection area in addition to the components having the same functions as those of the standard optical defect inspection apparatus shown in FIG. An evaluation device 29 having a function of determining a thinning inspection pattern, a function of evaluating the validity of the inspection result, and a function of evaluating inspection efficiency is provided.

  That is, the defect inspection apparatus according to the embodiment of the present invention has the following components and functions as in the conventional defect inspection apparatus. That is, the defect inspection is performed by moving the stage 12 on which the semiconductor substrate 11 made of a silicon wafer or the like is moved in the XY directions according to a signal from the stage control unit 13 while executing an inspection operation described later. Here, the inspection operation irradiates illumination from the illumination system 14 onto an inspection region on the semiconductor substrate 11 that is arbitrarily set in advance, forms an image of the reflected light from the inspection region by the detection optical system 15, and applies the light to the inspection region. The image sensor 16 receives the light and converts it into an analog electrical signal. The AD converter 17 converts the signal into a digital signal. The detected digital image signal is used as a reference digital image signal stored on the CPU 19. The comparison is made by detecting the difference as a defect such as a foreign object in comparison with the comparison inspection unit 18.

Next, the evaluation apparatus 29 provided in the defect inspection apparatus according to the embodiment of the present invention will be described in detail below.
In addition to the inspection recipe manager 20 for setting the inspection area of the semiconductor substrate 11 and the threshold value of the number of defects as an inspection recipe, the evaluation apparatus 29 stores a reticle information database 26 for storing reticle information and a defect inspection result. The inspection result database 27, the standard calculation unit 24 that calculates the abnormality determination standard from the defect inspection result, and the calculated abnormality determination standard and the defect inspection result are collated to calculate the number of detections of defect anomalies exceeding the abnormality determination standard. Standard abnormality detection number calculation unit 23, inspection time calculation unit 21 that calculates the time required for inspection from inspection conditions, abnormality detection capability calculation unit 28 that calculates the number of abnormality detections per unit time, Distribution difference in which the occurrence of defects exceeds a predetermined limit in the entire surface inspection from the wafer (semiconductor substrate 11) and is unevenly distributed in the wafer surface. Inspection that maximizes the number of abnormal detections per unit inspection time from the distribution abnormality detection limit thinning rate calculation unit 25 that calculates a thinning rate that can be detected at an arbitrary detection rate or higher, and reticle information and accumulated defect inspection results An inspection area calculation unit 22 that automatically sets an area and determines an inspection area is provided.

  In the evaluation apparatus 29, a reticle information database 26 for accumulating reticle information and an inspection area calculation unit 22 are connected to the inspection recipe manager 20 in order to realize a function for determining a thinned inspection pattern for a defect inspection area.

  In addition, an inspection result database (hereinafter referred to as inspection result DB) 27 and a standard abnormality detection number calculation unit 23 are connected to the inspection area calculation unit 22 in order to realize a function of evaluating the validity of the inspection results.

  The standard abnormality detection number calculation unit 23 is directly connected to the inspection result DB 27 to calculate a total abnormality detection number (connection route), and the standard calculation unit 24 is used to detect abnormality in each inspection pattern. There are two paths, the path for calculating the number of cases. In the path on the standard calculation unit 24 side, the function itself compares and evaluates the standard value obtained from the thinning inspection from the data in the inspection result DB 27 with the standard value at the time of the full inspection of the standard abnormality detection number calculation unit 23, and the SN ratio is maximized. This is provided because it is functionally necessary to calculate the thinning rate.

The distribution abnormality detection limit decimation rate calculation unit 25 is connected to the inspection area calculation unit 22 through a path different from the standard abnormality detection number calculation unit 23 and the standard calculation unit 24 described above.
The inspection time calculation unit 21 and the abnormality detection capability calculation unit 28 that calculates the detection capability of unit time receive an instruction from the inspection recipe manager 20 and output the result to the inspection area calculation unit 22. The inspection recipe manager 20 determines an inspection recipe using the result of the inspection area calculation unit 22 and controls the defect inspection apparatus.

A specific function of the above configuration and a defect inspection method according to the embodiment of the present invention will be described below.
(About the function to determine the thinning inspection pattern of the defect inspection area)
First, design information of a semiconductor device is required to determine a thinning inspection pattern of a defect inspection area. Therefore, a reticle design stored in a reticle information database 26 having design information of a reticle embodying design information is designed. The inspection area is calculated and set based on the information. The portion having the function of calculating the inspection area is the inspection area calculation unit 22.

  The inspection area calculation unit 22 is used to refer to reticle design information, and as shown in FIG. 2, a single chip in the vertical direction (Y direction) is taken as one row with respect to the inspection scan direction (X direction). From the number of chips in the Y direction in one shot (in FIG. 5, n is the number of chips. However, in FIG. 5, from the third stage chip to the (n−1) th stage chip is omitted. The inspection pattern for thinning out the inspection area is set in increments of one column until the column inspection (shown). This inspection thinning line is determined from the number of shots from the upper stage in the wafer surface and the number of chips from the upper stage in the shot. The number of shot stages from the upper stage is evenly thinned using random numbers, and the number of chips from the upper stage is Thinning out in order from the top to the bottom (that is, the order of the first row of chips in the a-th shot, the second row of chips in the b-th shot, the third row of chips in the c-th shot,. However, a, b, and c are thinned out by random numbers), and the part of the lowermost chip number is thinned out, and then the part of the uppermost chip number is thinned out and repeated. A collection of these functions is a function for determining a thinning inspection pattern [(N−1) × n pattern] of the inspection area. For example, when the number of shot stages is 10 and the number of chips is 5, 45 patterns are determined by (10-1) × 5. Usually, there is almost no case of such a minimum configuration, but in order to help understanding, the case where the number of shot stages is 3 and the number of chips is 2 is shown in FIGS. In this case, the number (type) of thinning inspection patterns is composed of four patterns of (3-1) × 2, as shown on the right side of the illustrated surface.

(About the function to evaluate the validity of test results)
Next, since the function of evaluating the validity of the inspection result requires the result of past defect inspection, an inspection result database (hereinafter referred to as inspection result DB) 27 having past inspection data is provided. Further, after referring to the inspection result stored in the inspection result DB 27, the number of detected defects when inspecting with each inspection pattern is calculated, and the out-of-standard at the time of all-column inspection is signal component S, and the inside of the standard is noise component N A standard calculation unit 24 that calculates a standard value that maximizes the SN (difference value) or S / N ratio in each pattern is provided, and the standard value is set using the function of the standard calculation unit 24. It is composed.

  When setting the standard value, the following arithmetic processing is performed. That is, as shown in FIG. 5 (a), it is regarded as a true NG wafer if the number of defects exceeds the predetermined standard value and is determined to be a non-standard wafer as shown in FIG. 5 (b). ), As shown in (c), while it is determined that the wafers are within the standard in the all row inspection results, the thinning inspection pattern in which some rows are thinned out has more defects than the predetermined standard value and The determined one is regarded as an erroneous NG wafer. Then, for each thinning inspection pattern, an optimal standard value that can detect the maximum number of true NG wafers is calculated while minimizing the number of erroneous NG wafers. More specifically, first, based on the accumulated inspection results of the past all-column inspection, the number of detected defects when inspecting with each thinning inspection pattern is obtained. Then, the standard value for determining a non-standard wafer (that is, the threshold value between the standard (OK) wafer and the non-standard (NG) wafer) is increased in order from the smallest value (however, all-row inspection is performed) Because the standard value of NG is fixed, the number of NG in all row inspection = true NG is fixed), the number of false NG is subtracted from the number of true NG, and the standard value that maximizes the subtracted value (referred to as the difference value) is optimal Set to standard value. FIG. 5D is a diagram conceptually showing a state when obtaining the standard value. When the standard value is small, the number of false NGs is large, so the difference value is also a very low value (negative number). (For example, in the case shown in FIG. 5B, when the standard value is 1, in 22 wafers (wafer numbers 1 to 22), the true NG number is 3 and the false NG number is 19. Therefore, in this case, the difference value is −16). When the standard values are layered one by one, the threshold value that is the standard value moves upward on the graph, so the number of erroneous NGs decreases and the difference value increases. Since the overall number of NGs decreases and finally the NG number itself becomes 0, the difference value also becomes 0. In this way, the optimum standard value that maximizes the difference value is calculated for each thinning inspection pattern. Instead of the difference value, an optimum standard value with which the S / N ratio (the number of true NGs / the number of erroneous NGs) has the maximum difference value may be calculated.

  Then, as shown in FIG. 5D, among the standard values having the same number as the types of thinning inspection patterns, the one having the highest peak and the highest thinning rate is set as the optimum thinning inspection pattern. To do. In practice, the number of processed sheets per unit time is determined by the area of the semiconductor substrate 11 and the magnification (actual inspection range area) of the optical system at the time of inspection. The number of true NGs obtained per unit time can be increased.

  By the way, the above-described thinning inspection pattern optimization can be applied to the above method satisfactorily when there is no partial distribution. However, in practice, the pattern formed on the semiconductor substrate 11 often has a partial distribution. It is preferable to have a function to evaluate including the case where there is a partial distribution as follows. In this way, when there is a partial distribution, the normal optimized thinning-out inspection pattern alone is often insufficient, so the function for calculating the detection limit thinning rate for calculating the partial distribution abnormality (distribution abnormality) A detection limit thinning rate calculation unit 25) is provided. Then, the distribution abnormality detection limit thinning-out rate calculation unit 25 calculates a quantitative value of the defect distribution in the wafer surface when the inspection is performed with each inspection pattern while referring to the inspection result. Further, the result is used to determine a thinning limit for detecting all distribution anomalies at the time of all-row inspection.

This point will be described in detail with reference to FIG.
The uppermost figure in FIG. 6 shows various uneven distribution patterns (uppermost figure) in which defects are unevenly distributed in the semiconductor substrate 11. In the (N−1) × n thinning inspection patterns, This shows the evaluation of whether or not the chip in the shot can be covered without omission even when there is a partial distribution. More specifically, the partial distribution pattern of the defect is quantified by treating the partial distribution pattern as the index coordinate of the chip and comparing it with the index coordinate of the chip of the thinning inspection pattern. Then, based on the partial distribution state of the defect, the determination is made by calculating a good or defective state (the inspection effective shot stage / chip stage after thinning out has no shot stage / chip stage including the coordinates of the partial distribution. Would be NG). As shown in FIG. 6, in the embodiment of the present invention, since the scanning direction is the horizontal direction, the semiconductor substrate 11 having a partial distribution of defects in a pattern inclined in the scanning direction (close to horizontal) is higher. In the thinning rate, the detection accuracy is lowered, and the threshold value that is x with respect to the thinning rate is lowered. While reading such a trend, the thinning limit is determined.

  Then, by combining the thinning limit and the standard pattern obtained earlier, a thinning inspection pattern that maximizes the number of abnormality detections per unit time at a thinning rate smaller than the partial distribution abnormality detection limit is determined (see FIG. 7). In addition, in the case shown in FIG. 7, although the case where the peak of the number of abnormality detections per unit time is located in the portion where the thinning rate is lower than the uneven distribution abnormality detection limit, it is not limited to this. If the peak of the number of detected abnormalities per unit time is located in the part where the thinning rate is higher than the uneven distribution abnormality detection limit, the intersection of the uneven distribution abnormality detection limit and the number of detected abnormalities is the optimal thinning inspection pattern. Become.

  By using these three large functions in an integrated manner, the inspection recipe is further optimized, the inspection time per sheet in the defect inspection apparatus is shortened, and the relative throughput is improved. As a result, inspection costs can be reduced. In addition, since the coverage rate of varieties that can be applied even in factories that produce a variety of products in small quantities is improved, the accuracy of state management in the atmosphere of the production site is improved.

  In addition, the higher the thinning rate, the better the stability of the atmosphere in the field with low risk due to defects, so the optimum calculation result can also be used as a stability evaluation index for the atmosphere in the production line. . In other words, when the atmosphere of the field is stable (the processing apparatus is not noticeable), the disturbance that disturbs the state of each shot is reduced. It can also be used as an index for evaluating the stability of the atmosphere, and because there are few factors that cause partial distribution, the partial distribution abnormality detection limit does not go to the side where the thinning rate is lower than the peak of the thinning inspection pattern, and thinning is performed with a higher thinning rate. The inspection pattern is optimal.

Therefore, the optimized system as shown in the present invention is provided on the defect inspection apparatus and integrated to enable effective and efficient operation.
As described above, according to the present invention, the inspection time per sheet in the defect inspection apparatus is shortened, the relative throughput is improved, and the inspection cost can be reduced. The change in the thinning rate can also be used as an indicator for managing the state of the atmosphere at the production site.

  The present invention can be favorably applied as a defect inspection apparatus or a defect inspection process for inspecting a defect of a circuit pattern formed on a semiconductor substrate such as a silicon wafer.

DESCRIPTION OF SYMBOLS 11 Semiconductor substrate 12 Wafer stage 13 Stage control part 14 Inspection illumination system unit 15 Defect detection optical system unit 16 Image sensor 17 AD conversion part 18 Defect pattern comparison inspection part 19 CPU for apparatus control
DESCRIPTION OF SYMBOLS 20 Inspection recipe manager 21 Inspection time calculation part 22 Inspection area calculation part 23 Standard abnormality detection number calculation part 24 Standard calculation part 25 Distribution abnormality detection limit thinning-out rate calculation part 26 Reticle information database 27 Inspection result database 28 Abnormality detection capability calculation part 29 Evaluation apparatus

Claims (6)

  A reticle information database that accumulates reticle information, an inspection result database that accumulates defect inspection results, and a standard calculation unit that calculates an abnormality determination standard that is a threshold for determining that a semiconductor substrate has an abnormal defect from the defect inspection results And a standard abnormality detection number calculation unit that calculates the number of defects with frequent defects exceeding the abnormality determination standard by comparing the calculated abnormality determination standard and the defect inspection result, and an inspection that calculates the time required for inspection from the inspection conditions Time calculation unit, anomaly detection capability calculation unit that calculates the number of anomaly detections per unit time, and the occurrence of defects in the entire surface inspection from within the semiconductor substrate within the standards, uneven distribution in the semiconductor substrate surface A defect inspection apparatus comprising: a distribution abnormality detection limit thinning rate calculation unit that calculates a thinning rate at which a distribution abnormality to be detected can be detected at an arbitrary detection rate or higher.   The inspection area calculation unit according to claim 1, further comprising: an inspection area calculation unit that automatically sets an inspection area that maximizes the number of abnormality detections per unit inspection time based on the reticle information and the accumulated defect inspection results, and determines the inspection area. Defect inspection equipment.   There is provided an inspection area calculation unit for determining an inspection area at a thinning rate that exceeds a limit that allows detection of a distribution abnormality distributed within the surface of the semiconductor substrate exceeding a predetermined limit in a full-surface inspection at an arbitrary detection rate or higher. The defect inspection apparatus according to claim 2.   An inspection area calculation unit for determining an inspection area so as to cover all chips in a reticle used for forming a pattern on a semiconductor substrate at a thinning rate derived from a defect inspection apparatus and a defect inspection method. Item 3. The defect inspection apparatus according to Item 3. Based on the reticle information, create multiple types of thinned inspection patterns by thinning some measurement areas from the semiconductor substrate to be inspected,
Based on the defect inspection result information, the number of detected defects in each thinned inspection pattern is calculated. From the number of true NG defects that are out of specification even at the time of all row inspection, the number of false NG defects that are out of specification at the time of all row inspection is calculated. A threshold value for the number of defects with a large difference value or a threshold value for the number of defects with a large ratio of the number of true NG defects to the number of erroneous NG defects is set as a specified value for determining that the semiconductor substrate is not specified,
Defect inspection in which the maximum difference value among the standard values of each thinning inspection pattern or the ratio of true NG defects to the number of erroneous NG defects is large and the thinning rate is the highest is set as the optimum thinning inspection pattern Method. Based on the reticle information, create multiple types of thinned inspection patterns by thinning some measurement areas from the semiconductor substrate to be inspected,
Based on the defect inspection result information, the number of detected defects in each thinned inspection pattern is calculated. From the number of true NG defects that are out of specification even at the time of all row inspection, the number of false NG defects that are out of specification at the time of all row inspection is calculated. A threshold value for the number of defects with a large difference value or a threshold value for the number of defects with a large ratio of the number of true NG defects to the number of erroneous NG defects is set as a specified value for determining that the semiconductor substrate is not specified,
Based on the state of distribution abnormality that the occurrence of defects exceeds the predetermined limit and is distributed in the semiconductor substrate surface in the entire inspection, the detection limit decimation rate is calculated,
Among the standard values of each thinning inspection pattern, the maximum difference value or the ratio of the true NG defect number to the number of false NG defects is large, and the thinning rate is the highest thinning rate below the detection limit thinning rate. Defect inspection method set as an optimal thinning inspection pattern.

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