JP2011014028A - Method and apparatus for determining decoupling capacitance, and program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method and apparatus for determining decoupling capacitance of high precision with ease while taking the inductance of wiring into consideration.SOLUTION: The method for determining the decoupling capacitance of a semiconductor integrated circuit includes introducing design data including an operating frequency f, consumed power P, source voltage V, a permissible fluctuation ΔV in source voltage, package inductance L, and characteristic capacitance Cp (S201); computing a reference die capacitance Cv1 (S203); setting the difference between Cv1 and Cp as decoupling capacitance Cd if Cp is smaller than Cv1 (S205); setting Cd at zero if Cp is greater than Cv1 (S206); computing a resonant frequency Tr on the basis of an actual die capacitance Cv, i.e., the sum of Cp and Cd, and L (S208); determining if the ratio Tr/kT is greater than 1 (S209); maintaining Cd if the ratio is equal to or less than 1 (S212); maintaining Cd if the ratio is greater than 1 and if Cv is greater than Cv1Tr/kT; and if Cv is smaller than Cv1Tr/kT, determining Cd so that Cv is equal to or greater than Cv1Tr/kT.

Description

  The present invention relates to a decoupling capacitance determination method and apparatus for determining a decoupling capacitance to be arranged in a semiconductor integrated circuit device, and a program for causing a computer to perform a determination process.

  In recent years, semiconductor integrated circuit devices have been miniaturized and highly integrated, and accordingly, the operating voltage has been lowered and the operating frequency has been increased. For example, the process rule for manufacturing a semiconductor integrated circuit device is 0.1 μm or less, and accordingly, the operating voltage is 1.2 V or less and the operating frequency is several hundred MHz or more. With the increase in speed, power supply noise (noise) increases in a semiconductor integrated circuit device, and resistance to noise deteriorates with a reduction in voltage, so that circuit malfunction due to noise is likely to occur. The malfunction includes a logic malfunction due to a logic value error and a timing malfunction due to a timing error.

  In order to prevent malfunction of the circuit due to noise, it is conceivable to design the timing so as to shift the operation timing of the elements and reduce the number of simultaneously operating elements. However, at present, the technology is immature. Therefore, a decoupling capacitor is provided between the circuit power supplies to prevent malfunction of the circuit due to noise. Conventionally, the layout design of the decoupling capacitor at the design stage using CAD is performed by first arranging various functional cells in a die (semiconductor integrated circuit device chip) according to an appropriate rule, and thereafter no functional cells are arranged. A decoupling capacity cell is arranged in the empty area.

  The arrangement process of the decoupling capacitance element is performed using a decoupling capacitance determination device that determines the capacitance value of the decoupling capacitance to be arranged. The decoupling capacity determination device is realized as a part of the CAD device. To determine the decoupling capacity, an EDA (Electronic Design Automation) tool capable of analyzing power supply noise (DvD) is used to obtain dynamic power supply voltage fluctuations under various conditions, and the decoupling capacity is determined based on the analysis results. To decide. However, such analysis processing takes a long time. In view of this, a decoupling capacity determination device that determines a decoupling capacity in accordance with a predetermined arithmetic expression has been proposed.

  The capacitance value of the decoupling capacitor to be arranged is determined in consideration of the power supply noise component generated according to the Kirchhoff voltage law (KVL) by the resistance component and current consumption of the power supply network of the semiconductor integrated circuit device.

  FIG. 1 is a flowchart showing a decoupling capacity determination process in a general decoupling capacity determination apparatus.

  In step 101, design data including an operating frequency f, power consumption P, power supply voltage Vdd, allowable power supply voltage fluctuation amount ΔV, intrinsic capacitance Cp of a semiconductor integrated circuit, and the like necessary for determining a decoupling capacitor to be arranged is provided. To introduce. These design data are data that are input to the CAD device or generated internally in accordance with the design target semiconductor integrated circuit device when the semiconductor integrated circuit device is designed.

  In step 102, the die capacitance Cv is calculated according to the following equation (1).

Cv1 = P / (f · Vdd · ΔV) (1)
The die capacitance Cv1 is a capacitance between the high-potential side power supply and the low-potential side power supply that is necessary for suppressing fluctuations in the power supply voltage, that is, power supply noise to be equal to or less than the allowable power supply voltage fluctuation amount ΔV.

  In step 103, the decoupling capacitance Cd is calculated according to the formula Cd = Cv1-Cp.

  Since the semiconductor integrated circuit device has a specific capacitance Cp between the high-potential side power supply and the low-potential side power supply, Cv1−Cp is a shortage of capacitance, and a decoupling capacitance Cd is provided to provide this shortage. Complements Cv1-Cp. When Cp is larger than Cv1, Cd is zero and there is no need to provide a decoupling capacitor.

  The processing of FIG. 1 may be simply performed on the entire semiconductor integrated circuit device. However, in a highly integrated and large-scale semiconductor integrated circuit device, a decoupling capacitor is provided in the vicinity of the noise generation source. Need to be reduced. Therefore, it has been proposed to perform the processing of FIG. 1 for each functional region of the semiconductor integrated circuit device to determine the decoupling capacitance for each functional region, and to provide the decoupling capacitance determined accompanying each functional region. For example, the layout unit is a functional area, the required decoupling capacitance is determined for each layout unit, and the determined decoupling capacitance is arranged for each layout unit. In this case, the capacitance value of the decoupling capacitance is determined according to the number of synchronous cells such as clock buffers and flip-flops in each layout unit. The decoupling capacitance is realized in the form of a decoupling cell, and the decoupling cell is arranged in the vicinity of the synchronous cell.

  As the decoupling capacitance is increased, power supply noise can be reduced. However, if the decoupling capacitance is increased, the semiconductor integrated circuit device is correspondingly increased, resulting in an increase in cost. For this reason, the decoupling capacity is required to be determined so as to ensure a necessary amount but not to become larger than necessary.

  In addition, when it is determined by the decoupling capacitance determination process of FIG. 1 that the decoupling capacitance determined for each functional region is insufficient, all or part of the semiconductor integrated circuit device is redesigned. When such a situation occurs, the design time is greatly extended, which affects the lead time of the semiconductor integrated circuit device. Therefore, the determination of the decoupling capacity is required to be performed with high accuracy.

  In the decoupling capacity determination process of FIG. 1, the decoupling capacity is determined in consideration of the power supply noise component generated according to the Kirchhoff voltage law (KVL). However, noise components generated by changes in wiring inductance and current consumption are also affected by power supply noise. Therefore, the decoupling capacity determination process in FIG. 1 cannot determine the decoupling capacity with sufficient accuracy. Therefore, it has been proposed to determine the decoupling capacitance in consideration of noise components generated due to changes in wiring inductance and current consumption.

  The proposed processing is simulated in consideration of the wiring and package inductance in the semiconductor integrated circuit device, and the accuracy of the decoupling capacitance is improved, but there is a problem that the processing time becomes very long. .

JP 2006-40962 A JP-A-2005-196406 JP 2002-222230 A JP 2005-157801 A

  The embodiment describes a highly accurate decoupling capacitance determination process in consideration of wiring inductance that can be easily performed.

  A first aspect of an embodiment is a decoupling capacitance determination method for determining a decoupling capacitance to be arranged in a semiconductor integrated circuit device, and includes an operating frequency, power consumption, a power supply voltage, an allowable power supply voltage fluctuation amount, a package inductance amount, Integrated circuit design data including at least the intrinsic capacity of the integrated circuit, and calculating the reference die capacity from the operating frequency, power consumption, power supply voltage and allowable power supply voltage fluctuation amount according to a predetermined arithmetic expression, When the capacities are compared and the specific capacity is smaller than the reference die capacity, the difference between the reference die capacity and the specific capacity is defined as the decoupling capacity. When the specific capacity is greater than the reference die capacity, the decoupling capacity is set to zero, and the specific capacity and decoupling The resonance frequency is calculated from the actual die capacitance, which is the sum of the ring capacitance, and the package inductance, and the resonance frequency It is determined whether the ratio between the number and the value obtained by multiplying the operating frequency by a predetermined constant is greater than 1. When the ratio is less than 1, the decoupling capacity is maintained. When the ratio is greater than 1, the actual die capacity and the reference die capacity are further maintained. The capacity is compared with the threshold capacity obtained by multiplying the ratio, and the decoupling capacity is maintained when the actual die capacity is larger than the threshold capacity, and the actual die capacity is equal to or greater than the threshold capacity when the actual die capacity is smaller than the threshold capacity. Determine the decoupling capacity.

  A second aspect of the embodiment is a decoupling capacitance determination device that determines a decoupling capacitance to be arranged in a semiconductor integrated circuit device, and includes an operating frequency, power consumption, power supply voltage, allowable power supply voltage fluctuation amount, and package inductance. A design data introduction unit for introducing and storing design data of the integrated circuit including at least the amount and the intrinsic capacity of the integrated circuit, and a reference die according to a predetermined arithmetic expression from the operating frequency, power consumption, power supply voltage and allowable power supply voltage fluctuation amount A die capacitance calculation unit for calculating the capacitance, a resonance frequency calculation unit for calculating the resonance frequency from the actual die capacitance that is the sum of the specific capacitance and the decoupling capacitance, and the package inductance amount, and multiplying the resonance frequency and the operating frequency by a predetermined constant When the specific condition is smaller than the reference die capacity The decoupling capacitance is the difference between the reference die capacitance and the specific capacitance. When the specific capacitance is larger than the reference die capacitance, the decoupling capacitance is zero, and when the ratio is 1 or less and the ratio is greater than 1, the actual die capacitance Is greater than the threshold capacity obtained by multiplying the reference die capacity by the ratio, the decoupling capacity is maintained, and when the ratio is greater than 1 and the actual die capacity is less than the threshold capacity, the actual die capacity is greater than or equal to the threshold capacity. And a decoupling capacity calculator for determining the decoupling capacity.

  According to the embodiment, the decoupling capacitance can be determined with a practically sufficient accuracy by a simple process that can be performed in a short processing time.

FIG. 1 is a flowchart showing a decoupling capacitance determination process of a general semiconductor integrated circuit device. FIG. 2 is a diagram illustrating a hardware configuration in which the decoupling capacitance determination device of the semiconductor integrated circuit device according to the embodiment is realized. FIG. 3 is a diagram illustrating a functional block configuration of the decoupling capacity determination device according to the embodiment. FIG. 4 is a flowchart illustrating a decoupling capacity determination process in the decoupling capacity determination apparatus according to the embodiment. FIG. 5 is a diagram illustrating a simulation model for obtaining an arithmetic expression in the decoupling capacity determination process of the embodiment. FIG. 6 is a diagram illustrating a current consumption model in a simulation in which an arithmetic expression in the decoupling capacity determination process of the embodiment is obtained. FIG. 7 is a diagram illustrating a simulation result of obtaining an arithmetic expression in the decoupling capacity determination process of the embodiment. FIG. 8 is a diagram illustrating a simulation result of obtaining an arithmetic expression in the decoupling capacity determination process of the embodiment.

  FIG. 2 is a diagram illustrating a schematic configuration of computer hardware 10 in which the decoupling capacitance determination device of the semiconductor integrated circuit device of the embodiment is realized.

  The decoupling capacity determination device can be realized by an independent computer, or can be realized by using common hardware as part of a general CAD (Computer Aided Design) device.

  As widely known, a computer hardware 10 is connected to a central processing unit (hereinafter referred to as CPU) 11, a memory 12, a storage device 13, a display device 14, an input device 15, and an external device 17. Drive device 16, which are connected to each other via a bus 18. Since the configuration of the computer hardware 10 is widely known, detailed description thereof is omitted. The computer in which the decoupling capacity determination device is realized is not limited to the configuration shown in FIG. 2 and can realize necessary functions such as a terminal device connected to a host computer or the like using a communication line or the like. I just need it.

  FIG. 3 is a block diagram illustrating a functional configuration of the decoupling capacity determination device 20 according to the embodiment. As illustrated in FIG. 3, the decoupling capacitance determination device 20 according to the embodiment includes a design data introduction unit 21, a die capacitance (Cv1) calculation unit 22 that calculates a reference die capacitance Cv1, and a resonance frequency that calculates a resonance frequency Tr. (Tr) A calculation unit 23, an application condition determination unit 24, a decoupling capacitance (Cd) calculation unit 25 that calculates the decoupling capacitance Cd, and a target region selection unit 26 are provided.

  The design data introducing unit 21 introduces and holds design data necessary for determining the decoupling capacity. These design data are stored in the memory 12 or the storage device 13. As described above, when the decoupling capacity determination device is realized as a part of the CAD device, the design data used and generated by the CAD device is stored in the memory 12 or the storage device 13 and used as it is. Is possible. When the decoupling capacity determination device is realized by a computer different from the CAD device, design data necessary for determining the decoupling capacity is supplied from the CAD device to the storage device 13 via the input device 15 and the memory 12 Alternatively, the data is transferred to and stored in the storage device 13.

  The design data necessary for determining the decoupling capacitance includes circuit data indicating the circuit configuration, operating frequency f, power consumption P, power supply voltage Vdd, allowable power supply voltage fluctuation amount ΔV, inherent capacity Cp inherent in the circuit, package inductance L, And a constant k to be described later.

  The circuit data indicates the positions and ranges of a plurality of functional cells provided in the semiconductor integrated circuit device. A plurality of functional cells form one functional area, for example, a layout unit.

  The operating frequency f is a frequency at which the semiconductor integrated circuit device operates, and corresponds to the clock frequency in the case of a semiconductor integrated circuit device that operates in synchronization with the clock. The reciprocal of the operating frequency f is the operating cycle T. In some cases, the semiconductor integrated circuit device includes a plurality of functional areas, and some of the functional areas operate with a divided clock obtained by dividing the clock. In such a case, the operating frequency f varies depending on the functional region.

  The power consumption P is supplied power and varies depending on the operating state. Here, the power consumption P indicates the maximum power. As described above, when the semiconductor integrated circuit device includes a plurality of functional regions and the decoupling capacitance is determined for each functional region, the power consumption P indicates the power supplied to the functional region.

  The power supply voltage Vdd is a voltage supplied to the high potential power source and the low potential power source. In general, the power supply voltage Vdd is the same even when the semiconductor integrated circuit device includes a plurality of functional regions.

  The allowable power supply voltage fluctuation amount ΔV indicates a fluctuation range of the power supply voltage Vdd that can guarantee normal operation. When the semiconductor integrated circuit device has a plurality of functional areas and determines the decoupling capacitance for each functional area, the allowable power supply voltage fluctuation amount ΔV is different from the functional area because the allowable fluctuation range of the power supply voltage varies depending on the functional area. Different for each.

  The intrinsic capacitance Cp is a capacitance originally provided in the semiconductor integrated circuit device. When the semiconductor integrated circuit device includes a plurality of functional regions, a specific capacitance Cp exists for each functional region. Therefore, when determining the decoupling capacitance for each functional region, the specific capacitance Cp of each functional region is used.

  The package inductance L includes the inductance of the bonding wire that connects the package terminal and the die pad. As described above, in order to accurately analyze the power supply noise, it is desirable to consider the inductance of the wiring of the power supply network of the semiconductor integrated circuit device in addition to the package inductance L. However, as a result of the simulation, the influence of the change in the inductance of the power supply network of the semiconductor integrated circuit device and the consumption current is small. It turns out that power supply noise can be analyzed. Therefore, only the influence of the change in package inductance L and current consumption is considered here. When the semiconductor integrated circuit device includes a plurality of functional regions, the package inductance L may be considered only for the functional regions directly connected to the package terminals.

  The constant k is a predetermined value, and k = 4 here as will be described later.

  The die capacity (Cv1) calculation unit 22 reads the operating frequency f, power consumption P, power supply voltage Vdd, and allowable power supply voltage fluctuation amount ΔV from the design data introduction unit 21, and, as described above, the die capacity according to the equation (1). Cv1 is calculated.

Cv = P / (f · Vdd · ΔV) (1)
In the embodiment, the die capacitance Cv1 calculated according to the well-known formula (1) is referred to as a reference die capacitance, and the reference die capacitance Cv1 is changed when the condition considering the package inductance L is satisfied.

  Further, the sum of the specific capacitance Cp and the decoupling capacitance Cd is referred to as an actual die capacitance Cv.

  The resonance frequency (Tr) calculation unit 23 calculates the resonance frequency Tr according to the equation (2) using the package inductance L and the actual die capacitance Cv read from the design data introduction unit 21.

Tr = 2π (LCv) ^1/2 (2)
The application condition determination unit 24 determines whether the ratio Tr / (kT) between the resonance frequency Tr and the value obtained by multiplying the operating frequency T by a predetermined constant k is greater than 1 (Tr> kT). Details of this determination will be described later.

  When the specific capacitance Cp is smaller than the reference die capacitance Cv1, the decoupling capacitance calculation unit 25 sets the difference between the reference die capacitance Cv1 and the specific capacitance Cp as the decoupling capacitance Cd, and when the specific capacitance Cp is larger than the reference die capacitance Cv1, When the ring capacitance Cd is zero and the ratio Tr / (kT) is 1 or less, and when this ratio is greater than 1, the actual die capacitance Cv is obtained by multiplying the reference die capacitance Cv1 by the ratio Tr / (kT). When the ratio Tr / (kT) is larger, the decoupling capacity Cd is maintained. When the ratio Tr / (kT) is larger than 1 and the actual die capacity Cv is smaller than the threshold capacity Cv1 · Tr / (kT), the actual die capacity is maintained. The decoupling capacitance Cd is determined so that Cv is equal to or greater than the threshold capacitance Cv1 · Tr / (kT). The details of this calculation will be described later.

  The target area selection unit 26 selects a functional area to be calculated when the semiconductor integrated circuit device includes a plurality of functional areas and determines a decoupling capacitance for each functional area. The target area selection unit 26 sequentially selects the functional areas to be calculated so as to divide the semiconductor integrated circuit device into a plurality of functional areas based on the circuit data and determine the decoupling capacitance of all the functional areas.

  FIG. 4 is a flowchart illustrating a process of determining the decoupling capacitance Cd of a plurality of functional regions of the semiconductor integrated circuit device using the decoupling capacitance determining device 20 of the embodiment.

  In step 201, the design data introduction unit 21 uses circuit data, operating frequency f, power consumption P, power supply voltage Vdd, allowable power supply voltage fluctuation amount ΔV, specific capacity Cp, package, which are design data necessary for determining the decoupling capacity. An inductance L and a constant k are introduced.

  In step 202, the target area selection unit 26 selects a target functional area.

  In step 203, the reference die capacitance Cv1 = P / (f · Vdd · ΔV) is calculated.

  In step 204, it is determined whether the specific capacitance Cp is equal to or greater than the reference die capacitance Cv1, and if Cp <Cv1, the process proceeds to step 205, and if Cp ≧ Cv1, the process proceeds to step 206.

  In step 205, the difference Cv1-Cp between the reference die capacitance Cv1 and the specific capacitance Cp is set as a decoupling capacitance Cd.

  In step 206, the decoupling capacitance Cd is set to zero.

  In step 207, the actual die capacitance Cv is defined as the sum of the specific capacitance Cp and the decoupling capacitance Cd (Cv = Cp + Cd).

In step 208, Tr = 2π (L · Cv) ^1/2 is calculated.

  In step 209, it is determined whether Tr / kt> 1, and if Tr / kT ≦ 1, the process proceeds to step 212, and if Tr / kt> 1, the process proceeds to step 210.

  In Step 210, it is determined whether Cv ≧ Cv1 · Tr / (kT). If Cv ≧ Cv1 · Tr / (kT), the process proceeds to Step 212. If Cv <Cv1 · Tr / (kT), Step 211 is performed. Proceed to

  In step 211, Cv, that is, Cd is increased, and the process returns to step 207. By repeating steps 207 to 211, Cv satisfies the condition of step 210, and the process proceeds to step 212. The increase in Cd may be incremented by a unit amount, and steps 207 to 211 may be repeated until the condition of step 210 is satisfied. Cd may be increased by a large amount. If this is the case, the number of repetitions can be reduced.

  In step 212, Cd is determined as the decoupling capacity.

  In step 213, it is determined whether or not there remains a functional region for which the decoupling capacitance Cd has not been determined. If it remains, the process returns to step 202, and if not, the process ends.

  Next, it will be described based on simulation results that the decoupling capacity can be determined with sufficient practical accuracy by the decoupling capacity determination process of the embodiment.

  FIG. 5 is a diagram for explaining a simulation model. In order to quantify the amount of power supply noise, Spice simulation was performed here using the model shown in FIG.

  As shown in FIG. 5, the die area is equally divided into rectangular areas. The high-potential-side power supply 30 and the low-potential-side power supply 40 are equally divided so as to correspond to this rectangular area, and are represented by resistance networks including resistors 31 and 41, respectively. The power supply terminals 32 and 42 are evenly arranged on each side of the die region. The power supply terminals 32 and 42 are connected to connection points of corresponding resistor networks through package inductances (bonding wires) 33. The inductance of the package inductance 33 is L. Functional elements including a current source 51 and a specific capacitance 52 are connected between corresponding connection points of the resistance network of the high potential side power supply 30 and the resistance network of the low potential side power supply 40, respectively. The functional element expresses the function of the function cell in the region together, and the current source 51 passes a current i generated when the function cell in the region operates. The specific capacity 52 is a combination of the capacity of the functional cells in the region. The resistance values of the resistors 31 and 41 were set based on the number of power supply terminals, the average power consumption P, and the amount of static voltage drop that is a design constraint.

  FIG. 6 is a diagram illustrating modeling of the consumption current i. As shown in FIG. 6, the period T of the clock CK having the operating frequency f is 1 / f. It is assumed that the current consumption i for each cycle changes in the form of an isosceles triangle. The base of the isosceles triangle was set to the propagation time (clock skew Tskew) from the first stage to the last stage of the clock distribution system. A plurality of cycles of this consumption current waveform are applied, and a value in a cycle in which the amount of drop is maximum is defined as a voltage drop amount.

  Using the simulation model as described above, the maximum voltage drop amount was calculated by combining various values of the operating frequency f, power consumption P, package inductance L, and specific capacitance C.

FIG. 7 is a diagram showing simulation results, and shows results when the operating frequency is 500 MHz (period 2 ns) and the power consumption is 1000 mW. The horizontal axis represents the resonance frequency Tr = 2π (LCv) ^1/2 . The vertical axis represents the magnification of the maximum voltage drop amount ΔVA with respect to the voltage fluctuation amount obtained when the reference die capacitance Cv1 calculated according to the above equation (1) is added. Accordingly, when the value on the vertical axis is “1”, it indicates that the reference die capacitance Cv1 calculated according to the above-described equation (1) is appropriate. Note that the maximum voltage drop amount on the high potential power supply side is doubled in order to consider the drop amount of the ground side (low potential side) power supply.

  From the result of FIG. 7, it can be seen that the magnification is 1 when Tr is less than 4 times the operating frequency T. That is, in the range where Tr is less than four times the operating frequency T, it is understood that the die capacitance Cv may be the reference die capacitance Cv1 calculated according to the above equation (1). It can be seen that the magnification tends to increase linearly in the range where Tr is 4 times or more the operating frequency T. As a result, when k = 4 and the range of Tr> kT, the maximum voltage drop amount ΔVA can be approximated by the following equation.

ΔVA = ΔV0 + ΔV0 · β · (Tr−kT) / (kT) (3)
However, ΔV0 is a voltage fluctuation amount obtained when the reference die capacitance Cv1 calculated according to the above equation (1) is added.

  Consider this range change in more detail.

  FIG. 8 shows data obtained by extracting data in which Tr in FIG. 7 is at least four times the operating frequency T, and transforming the maximum voltage drop ΔVA based on Expression (3).

ΔV0 + ΔV0 · β · (Tr−kT) / (kT) =
ΔV0 (1-β) + ΔV0 · β · Tr / (kT)
ΔV0 · β · Tr / (kT) =
(2π · β / k) · (P / (f · Cv / V)) · (LC) ^1/2 / T =
(2π · β / k) · (P / V) · (L / Cv) ^1/2 ∝ (2π / k) · (P / V) · (L / Cv) ^1/2 (4)
From FIG. 8, since the upper limit of the maximum voltage drop amount ΔVA is given when β = 1, it is as follows.

ΔVA≈ΔV0 + ΔV0 · β · (Tr−kT) / (kT) = ΔV0 · Tr / (kT)
In the range of Tr> kT, the maximum voltage drop amount ΔVA increases as described above compared to the voltage fluctuation amount obtained when the reference die capacitance Cv1 calculated according to the above-described equation (1) is added. In consideration of the die capacity, that is, the decoupling capacity Cd is determined. According to the operation of the embodiment shown in FIG. 4, the decoupling capacitance Cd is determined so as to satisfy this condition.

  As described above, according to the embodiment, the process of determining the decoupling capacitance of a semiconductor integrated circuit device that operates at a high frequency affected by the package inductance with sufficient practical accuracy can be performed in a short time. .

  Although the embodiment has been described above, all examples and conditions described herein are described for the purpose of helping understanding of the concept of the invention applied to the invention and the technology. It is not intended to limit the scope of the invention, and the construction of such examples in the specification does not indicate the advantages and disadvantages of the invention. Although embodiments of the invention have been described in detail, it should be understood that various changes, substitutions and modifications can be made without departing from the spirit and scope of the invention.

10 Computer 11 CPU
12 Memory 13 Storage Device 20 Decoupling Capacity Determination Device 20
DESCRIPTION OF SYMBOLS 21 Design data introduction part 22 Die capacity | capacitance (Cv1) calculating part 23 Resonance frequency (Tr) calculating part 24 Applicable condition determination part 25 Decoupling capacity | capacitance (Cd) calculating part 26 Target area | region selection part

Claims (5)

A decoupling capacitance determination method for determining a decoupling capacitance to be arranged in a semiconductor integrated circuit device,
Introduce integrated circuit design data that includes at least the operating frequency, power consumption, power supply voltage, allowable power supply voltage fluctuation, package inductance, and integrated circuit specific capacitance,
Calculate a reference die capacity according to a predetermined arithmetic expression from the operating frequency, the power consumption, the power supply voltage and the allowable power supply voltage fluctuation amount,
Comparing the specific capacitance with the reference die capacitance;
When the specific capacity is smaller than the reference die capacity, the difference between the reference die capacity and the specific capacity is the decoupling capacity, and when the specific capacity is larger than the reference die capacity, the decoupling capacity is zero.
Resonance frequency is calculated from the actual die capacitance that is the sum of the specific capacitance and the decoupling capacitance and the package inductance amount,
Determining whether the ratio of the resonant frequency and the value obtained by multiplying the operating frequency by a predetermined constant is greater than 1,
When the ratio is 1 or less, the decoupling capacity is maintained,
When the ratio is greater than 1, the actual die capacity is further compared with a threshold capacity obtained by multiplying the reference die capacity by the ratio,
When the actual die capacity is greater than the threshold capacity, the decoupling capacity is maintained,
The decoupling capacity determining method, wherein when the actual die capacity is smaller than the threshold capacity, the decoupling capacity is determined such that the actual die capacity is equal to or greater than the threshold capacity. The semiconductor integrated circuit device includes a plurality of functional regions,
The decoupling capacity determination method according to claim 1, wherein the decoupling capacity determination method is executed for each functional region.   The decoupling capacity determination method according to claim 1, wherein the predetermined constant is four. A decoupling capacitance determination device for determining a decoupling capacitance to be arranged in a semiconductor integrated circuit device,
A design data introduction section for introducing and storing integrated circuit design data including at least an operating frequency, power consumption, power supply voltage, allowable power supply voltage fluctuation amount, package inductance amount, and intrinsic capacitance of the integrated circuit;
A die capacity calculation unit that calculates a reference die capacity according to a predetermined calculation formula from the operating frequency, the power consumption, the power supply voltage, and the allowable power supply voltage fluctuation amount;
A resonance frequency calculation unit for calculating a resonance frequency from an actual die capacitance that is the sum of the specific capacitance and the decoupling capacitance and the package inductance amount;
An application condition determination unit that determines whether a ratio between the resonance frequency and a value obtained by multiplying the operating frequency by a predetermined constant is greater than 1,
When the specific capacity is smaller than the reference die capacity, the difference between the reference die capacity and the specific capacity is the decoupling capacity, and when the specific capacity is greater than the reference die capacity, the decoupling capacity is zero. When the ratio is less than 1 and when the ratio is greater than 1 and the actual die capacity is greater than a threshold capacity obtained by multiplying the reference die capacity by the ratio, the decoupling capacity is maintained and the ratio is greater than 1. And a decoupling capacity calculating unit that determines the decoupling capacity so that the actual die capacity is equal to or greater than the threshold capacity when the actual die capacity is smaller than the threshold capacity. Capacity determination device. A computer program for causing a computer to execute processing for determining a decoupling capacitance to be arranged in a semiconductor integrated circuit device,
Introduce integrated circuit design data that includes at least the operating frequency, power consumption, power supply voltage, allowable power supply voltage fluctuation, package inductance, and integrated circuit specific capacitance,
Calculate a reference die capacity according to a predetermined arithmetic expression from the operating frequency, the power consumption, the power supply voltage and the allowable power supply voltage fluctuation amount,
Comparing the specific capacitance with the reference die capacitance;
When the specific capacity is smaller than the reference die capacity, the difference between the reference die capacity and the specific capacity is the decoupling capacity, and when the specific capacity is larger than the reference die capacity, the decoupling capacity is zero.
Resonance frequency is calculated from the actual die capacitance that is the sum of the specific capacitance and the decoupling capacitance and the package inductance amount,
Determining whether the ratio of the resonant frequency and the value obtained by multiplying the operating frequency by a predetermined constant is greater than 1,
When the ratio is 1 or less, the decoupling capacity is maintained,
When the ratio is greater than 1, the actual die capacity is further compared with a threshold capacity obtained by multiplying the reference die capacity by the ratio,
When the actual die capacity is greater than the threshold capacity, the decoupling capacity is maintained,
When the actual die capacity is smaller than the threshold capacity, the computer program is operated to determine the decoupling capacity so that the actual die capacity is equal to or greater than the threshold capacity.

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