JP2011009642A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device that achieves good adhesion with respect to a barrier metal insulating film and Cu, and prevents diffusion of Cu at the same time, and to provide a method of manufacturing the same.SOLUTION: A seal insulating film is formed on a sidewall of a recess in an insulating film, and a Cu-based buried electrode is formed through a barrier layer of a three-layer structure including a first conductive barrier layer having an superior adhesion with the seal insulating film, a second conductive barrier layer having a high Cu diffusion preventing capability and a third conductive barrier layer having an superior adhesion with the Cu-based buried electrode, which are arranged sequentially inside the seal insulating film.

Description

  The present invention relates to a semiconductor device and a method for manufacturing the same, for example, a configuration of a barrier layer when forming an embedded wiring.

  In recent years, aluminum has been widely used as an electrode material or wiring material for semiconductor devices. However, with recent demands for miniaturization of semiconductor devices and higher processing speeds, it has become difficult to handle electrodes and wiring with aluminum. For this reason, attempts have been made to use copper that is resistant to electromigration and has a smaller specific resistance than aluminum.

  On the other hand, in order to increase the speed of the semiconductor device, it is necessary to lower the dielectric constant of the interlayer insulating film in order to reduce the resistance of the electrodes and wirings and reduce the parasitic capacitance that causes signal delay. As such an insulating film, a so-called low-k material having a low k value is used.

  However, since the low-k material generally has a hole to lower the k value, there is a problem that the metal as the wiring material is likely to diffuse into the low-k material because of the presence of the hole. Therefore, in a copper multilayer wiring having a damascene structure, the side walls of wiring trenches provided in an interlayer insulating film made of a low-k material are sealed with an insulating film (see, for example, Patent Document 1).

  Further, by avoiding an increase in wiring resistance value due to the miniaturization of the copper embedded wiring and forming a metal oxide film layer such as ruthenium oxide around the copper region, a TDDB (Time Dependent Dielectric Darkdown) life Wiring reliability such as prolonging the service life is ensured (see, for example, Patent Document 2).

In particular, copper easily diffuses into the insulating film containing Si—O, and a barrier metal layer is formed on the wiring and via hole sidewalls before the copper film is formed in order to prevent diffusion. As the barrier metal layer, Ta, Ti, TaN or the like is generally used, but has a feature that the resistance value is higher than Cu. For example, while the specific resistance value of copper is 1.7 × 10 ⁻⁶ Ω · cm, Ta is 15 × 10 ⁻⁶ Ω · cm, and Ti is 80 × 10 ⁻⁶ Ω · cm.

As the wiring becomes finer, the ratio of the resistance value to the barrier metal film occupying the wiring resistance increases, so that the total resistance value of copper and barrier metal increases. For example, according to the technology roadmap indicated by ITRS 2006 (International Technology Roadmap of Semiconductors 2006 Edition), the specific resistance value of copper wiring of the hp (harf pitch) 32 nm generation (wiring pitch 64 nm) is 4.83 × 10 ⁻⁶ Ω · cm.

  In order to ensure the TDDB life reliability of the wiring, it is effective to improve the adhesion at the Cu interface. For example, crystalline Ru is known as a barrier metal having a low specific resistance and good adhesion to Cu.

JP 2005-236285 A JP 2008-159720 A

  However, in the case of crystalline Ru, there is a problem that Cu diffuses to the outside through crystal defects because of the crystallinity. Therefore, the diffusion of Cu can be avoided by forming a film of amorphous Ru containing nitrogen as a base material that hardly diffuses out of Cu.

  However, since such amorphous Ru has low adhesion to the insulating film on the side wall, there is a problem that peeling occurs due to shear stress during the CMP process. On the other hand, the above-mentioned ruthenium oxide has good adhesion to the insulating film, but there is a problem that when it is in direct contact with the porous insulating film, it diffuses into the porous insulating film due to the influence of moisture in the film.

  Therefore, an object of the present invention is to achieve both the adhesion of the barrier metal to the insulating film and Cu and the prevention of Cu diffusion.

  From one aspect of the present invention, an insulating film, a concave portion provided in the insulating film, a seal insulating film formed on a side wall of the concave portion, and the inside of the concave portion inside the seal insulating film in order. A semiconductor device comprising a provided first conductive barrier layer, a second conductive barrier layer, and a Cu-based embedded electrode formed via a third conductive barrier layer, wherein The conductive barrier layer 3 has better adhesion to the Cu-based embedded electrode than the second conductive barrier layer, and the second conductive barrier layer is better than the third conductive barrier layer. A semiconductor device characterized in that Cu diffusion prevention capability is high, and the first conductive barrier layer has better adhesion to the insulating film that seals the side wall than the second conductive barrier layer. Is provided.

  According to another aspect of the present invention, a step of forming a recess in the insulating film, a step of forming a seal insulating film on the sidewall of the recess, and a first inside the recess and inside the seal insulating film. Forming a conductive barrier layer, and forming a second conductive barrier layer on the first conductive barrier layer, the second conductive barrier layer having a Cu diffusion prevention capability higher than that of the first conductive barrier layer. Forming a third conductive barrier layer having better adhesion to Cu than the second conductive barrier layer on the second conductive barrier layer; and forming a third conductive barrier layer on the third conductive barrier layer. A step of depositing a Cu-based electrode material so as to fill the recess, the Cu-based electrode material, the third conductive barrier layer, the second conductive barrier layer, and the first conductive barrier. Until the surface of the insulating film in which the recess is formed is exposed. And polishing the first conductive barrier layer, wherein the first conductive barrier layer has better adhesion to the seal insulating film than the second conductive barrier layer. A manufacturing method is provided.

  According to the disclosed semiconductor device and the manufacturing method thereof, since the barrier metal has a three-layer structure, it is possible to achieve both adhesion of the barrier metal to the insulating film and Cu and prevention of Cu diffusion.

It is a conceptual sectional view of the wiring structure of an embodiment of the invention. It is explanatory drawing to the middle of the formation process of the wiring structure of embodiment of this invention. It is explanatory drawing to the middle after FIG. 2 of the formation process of the wiring structure of embodiment of this invention. It is explanatory drawing to the middle after FIG. 3 of the formation process of the wiring structure of embodiment of this invention. FIG. 5 is an explanatory diagram of FIG. 4 and subsequent drawings showing a wiring structure forming process according to an embodiment of the present invention. It is a schematic sectional drawing of the electromigration test pattern in this invention. 1 is a schematic cross-sectional view of a semiconductor device of the present invention and Example 1. FIG.

  Here, with reference to FIG. 1 thru | or FIG. 6, embodiment of this invention is described. FIG. 1 is a conceptual cross-sectional view of a wiring structure according to an embodiment of the present invention. A recess is formed in the interlayer insulating film 3 formed on the base insulating film 1 in which the plug 2 is embedded, and the sidewalls of the recess are sealed with the insulating film 4 for sealing, and the first barrier metal film 5 to the third barrier metal. A Cu wiring 8 is embedded through a film 7.

  As such an interlayer insulating film 3, a so-called Low-k material is suitable. For example, as an insulating material, for example, Black Diamond (trade name, manufactured by AMAT), Coral (trade name, manufactured by Novellus System) or Aurora UKL (ASM) Company name).

  In addition, as the insulating film 4 for sealing the sidewall of the recess, at least one of silicon carbide, silicon oxycarbide, silicon nitride, silicon oxynitride, silicon oxide, and the like is used. Silicon oxycarbide is more preferable from the viewpoint of barrier properties.

  The first barrier metal film 5 is preferably made of a material having good adhesion to the insulating film 4 that seals the side wall of the recess, and for example, ruthenium oxide is suitable. In the case of forming this ruthenium oxide film, ruthenium may be formed using a physical vapor deposition method such as a sputtering method in an atmosphere containing oxygen, for example, in an oxygen atmosphere.

  Further, as the second barrier metal film, although the adhesion to the insulating film 4 is inferior to that of ruthenium oxide, amorphous Ru containing 0.5 atom% to 15.0 atom% of nitrogen having a high Cu diffusion preventing ability is used. Is preferred. In the case of depositing this amorphous Ru, ruthenium may be deposited using a physical vapor deposition method such as a sputtering method in an atmosphere containing nitrogen, for example, in a nitrogen atmosphere.

  Further, as the third barrier metal film, crystalline Ru having good adhesion to Cu is preferable, although Cu diffusion prevention ability is inferior to amorphous Ru. In the case of forming this crystalline Ru, ruthenium may be formed using a physical vapor deposition method such as a sputtering method in an atmosphere containing no nitrogen and oxygen, for example, in a vacuum. Note that the Cu wiring 8 does not need to be pure Cu, and Al or Si of 3.0 wt% or less may be added in order to increase electromigration resistance.

  Next, with reference to FIG. 2 to FIG. 5, a description will be given of a process for forming a wiring structure according to the embodiment of the present invention. First, as shown in FIG. 2A, after a plug 12 made of W or the like is embedded in a base insulating film 11 made of PSG (phosphorus glass) or the like, an etching stopper film 13, an interlayer insulating film 14, and a cap film 15 are sequentially deposited. In this case, the etching stopper film 13 uses, for example, silicon oxycarbide (SiOC) having a relative dielectric constant of 3.6 and a thickness of 10 nm to 40 nm.

The interlayer insulating film 14 is preferably a CVD-based SiOC film, which is a porous low-k material made of a low dielectric constant insulating material having a k value of 2.6 or less. Examples of such a material include the above-mentioned Black Diamond (trade name, manufactured by AMAT), Coral (trade name, manufactured by Novellus System), Aurora UKL (trade name, manufactured by ASM), and the like. The thickness is 60 nm to 120 nm. The cap film 15 is preferably SiO ₂ and has a thickness of 30 nm to 70 nm.

  Next, as shown in FIG. 2B, etching is performed using a resist pattern (not shown) as a mask, thereby sequentially etching the cap film 15 to the etching stopper film 13 to form a wiring recess 16.

  Next, as shown in FIG. 2C, a seal insulating film 17 having a thickness of, for example, 3 nm is deposited. As the seal insulating film 17 in this case, silicon carbide, silicon oxycarbide, silicon nitride, silicon oxynitride, silicon oxide, or the like is used.

  Next, as shown in FIG. 3D, the seal insulating film 17 deposited on the surface of the cap film 15 and the bottom surface of the wiring recess 16 is removed by dry etching, and the seal insulating film is formed only on the side wall of the wiring recess 16. 17 remains.

  Next, as shown in FIG. 3E, the inner surface of the wiring recess 16 is covered with an oxide barrier film 18 having a thickness of 0.5 nm to 10 nm. In this case, the oxide barrier film 18 is preferably a ruthenium oxide film formed by sputtering Ru in an oxygen atmosphere from the viewpoint of adhesion to the seal insulating film 17.

  Next, as shown in FIG. 3F, the surface of the oxide barrier film 18 is covered with an amorphous barrier metal film 19 having a thickness of 2 nm to 10 nm. The amorphous barrier metal film 19 in this case is preferably an amorphous ruthenium film containing nitrogen formed by sputtering Ru in a nitrogen atmosphere from the viewpoint of Cu diffusion prevention capability.

  Next, as shown in FIG. 4G, the surface of the amorphous barrier metal film 19 is covered with a crystalline barrier metal film 20 having a thickness of 3 nm to 10 nm. The crystalline barrier metal film 20 in this case is preferably a crystalline ruthenium film formed by sputtering Ru in a vacuum from the viewpoint of adhesion with Cu.

  Next, as shown in FIG. 4H, a Cu plating seed layer 21 having a thickness of, for example, 30 nm is formed on the surface of the crystalline barrier metal film 20 by an electroless plating method. The seed layer may be formed using a stopper. In that case, it is desirable that the barrier metal layer be formed continuously in vacuum after the barrier metal layer is formed. Next, a Cu plating film 22 is formed so as to completely fill the concave portion by using an electrolytic plating method.

  Next, as shown in FIG. 5I, by performing a CMP process, polishing is performed until the cap film 15 is exposed, and the Cu embedded wiring 23 is formed by flattening. In this CMP process, when the relatively hard crystalline barrier metal film 20 and amorphous barrier metal film 19 are polished, for example, high pressure polishing of about 2.5 psi is performed.

  On the other hand, when the relatively fragile oxide barrier film 18 is polished, low pressure polishing of about 1 psi is performed with an acid or alkaline slurry in order to suppress generation of scratches on the polished wiring surface. By suppressing the occurrence of scratches, it is possible to form a wiring without a leak path during the TDDB test. Note that, when the barrier film is polished, the etching is performed by about 20 nm to 40 nm in order to avoid polishing residue.

Next, after planarization, it is desirable to remove the residual metal after polishing by washing the surface with an acidic or alkaline solution. In this case, it is desirable to perform cleaning until the metal concentration of the insulating film portion on the wiring surface after cleaning becomes 5 × 10 ¹¹ atoms / cm ² or less. In addition, in order to remove foreign substances, such as a grinding | polishing residue of a surface, it does not interfere even if it processes with a two-fluid spray.

  Next, as shown in FIG. 5J, an etching stopper film 24 made of silicon oxycarbide having a thickness of, for example, 30 nm is formed again on the planarized surface. Thereafter, a multilayer structure requiring an interlayer insulating film and cap film deposition process, a wiring recess or via hole formation process, a seal insulating film formation process, a multilayer barrier layer formation process, a Cu deposition process, and a planarization process. This is performed sequentially according to the number of stacked layers.

  As described above, in the embodiment of the present invention, since the barrier layer having the three-layer structure is provided after the sidewall of the wiring recess is covered with the seal insulating film, the adhesion of the barrier layer to the interlayer insulating film and Cu is provided. And Cu diffusion prevention can be achieved at the same time. In addition, since the barrier layer has good adhesion to the interlayer insulating film and Cu, peeling due to shear stress does not occur in the CMP process.

  With respect to the wiring structure of this embodiment, a TDDB test was performed by applying a voltage of 30 V at a temperature of 150 ° C. using a comb-tooth pattern having a width / space = 70 nm / 70 nm and a length of 1 mm. As a result, there were no defects in 100 chips at a test time of 100 hours, whereas there were 90 defects when only crystalline ruthenium was deposited as a barrier metal.

  Next, an electromigration resistance test was performed. FIG. 6 is a schematic cross-sectional view of the electromigration test pattern in the present invention. The first-layer Cu embedded wiring 41 and the second-layer Cu embedded wiring 43 have a width of 70 nm, a thickness of 100 nm, and a length of 200 μm, respectively. The via 42 has a diameter of 70 nm and a height of 100 μm.

  Using the electromigration evaluation pattern shown in FIG. 6, a test was performed by passing a current of 0.2 mA at a temperature of 300.degree. As a result, in the test time of 50 hours, there were 0 defects in 100 chips, whereas when only crystalline ruthenium was deposited as a barrier metal, 84 defects were generated.

Further, in order to confirm the effect, Comparative Examples 1 to 3 were prepared, and a TDDB test and an electromigration resistance test were performed under the same conditions as in the embodiment of the present invention.
Comparative Example 1 has a structure in which only the ruthenium oxide film is formed on the side wall of the wiring recess without forming the seal insulating film. In the TDDB test, 100 defects occurred in 100 chips in a test time of 100 hours. In the electromigration resistance test, 20 defects occurred in 100 chips in a test time of 50 hours.

  Comparative Example 2 has a structure in which only ruthenium oxide is formed as a barrier film. In the TDDB test, 20 defects occurred in 100 chips in a test time of 100 hours. In the electromigration resistance test, 100 defects occurred in 100 chips in a test time of 50 hours.

  Comparative Example 3 has a structure in which only amorphous ruthenium is formed as a barrier film. In the TDDB test, 100 defects occurred in 100 chips in a test time of 100 hours. In the electromigration resistance test, 100 defects occurred in 100 chips in a test time of 50 hours.

  Thus, in the embodiment of the present invention, a barrier layer having a three-layer structure is used, and the oxide barrier layer has better adhesion to the insulating film than Ru alone or nitrogen-containing Ru. It functions as an adhesion layer between an insulating film such as an amorphous barrier metal film.

  Further, since the oxide barrier film has a structure sandwiched between the amorphous barrier metal film and the seal insulating film, Ru does not diffuse to the outside and the Cu embedded wiring side. Furthermore, metal implantation on the trench side wall that occurs during the formation of the amorphous barrier metal film can be mitigated. Further, by forming a crystalline barrier metal film on the amorphous barrier metal film, it is possible to form a barrier metal layer having good adhesion to the Cu embedded wiring.

  Based on the above, next, the manufacturing process of the semiconductor device according to the first embodiment of the present invention will be described with reference to FIG. FIG. 3 is a schematic cross-sectional view of a semiconductor device manufactured by the manufacturing method according to Embodiment 1 of the present invention. First, for example, element isolation by shallow trench isolation (STI) is performed on the surface of a silicon substrate 51 having a diameter of 300 mm. An insulating film 52 is formed, and a MOSFET 53 is formed in the active region surrounded by the element isolation insulating film 52.

  The MOSFET 53 includes a gate insulating film 54, a gate electrode 55, a source region 57, and a drain region 58. Sidewalls 56 are provided on the side walls of the gate electrode 55, and extension regions are formed near the gate electrodes of the source region 57 and the drain region 58.

  Next, for example, a 1.5 μm-thick interlayer insulating film 59 made of phosphorus glass (PSG) is deposited on the entire surface by using, for example, a CVD method, and then penetrates the interlayer insulating film 59 and is formed in the source region 57 and the drain region 58. Two via holes are formed. The via hole is filled with conductive plugs 60 and 61 made of tungsten (W) through a TiN film using a CMP method.

Next, the SiOC film 62 having a relative dielectric constant of 3.6 serving as an etching stopper is formed on the interlayer insulating film 59 by, for example, CVD using tetramethylsilane and carbon dioxide as source gases. The film forming conditions are as follows.
Tetramethylsilane flow rate: 500 sccm
Carbon dioxide gas flow rate: 150sccm
Pressure: about 600 Pa (4.5 Torr)
13.56 MHz RF power: 600 W
400 kHz RF power: 10 W
Substrate temperature: 400 ° C
It was.
Note that the area of the parallel plate electrode for supplying RF power is substantially equal to the area of the silicon substrate 51.

Next, on the SiOC film 62, for example, a low dielectric constant insulating material having a k value of 2.6 or less, for example, Black Diamond (trade name, manufactured by AMAT), which is a porous low-k material, is formed to have a thickness. For example, a 100 nm porous silica film 63 is formed. Next, a SiO ₂ cap film 64 having a thickness of 60 nm, for example, is formed on the entire surface.

Next, after the inner surface of the wiring trench is covered with the SiOC film having a thickness of 3 nm, the SiOC film deposited on the bottom surface of the wiring trench and the surface of the SiO ₂ cap film 64 is removed by dry etching, so that the sidewall of the wiring trench is removed. A sealing insulating film 66 is formed to cover it.

  Next, using a sputtering method, an oxidized Ru film 67 having a thickness of 1 nm, an amorphous Ru film 68 containing nitrogen having a thickness of 3 nm, and a crystal not containing nitrogen having a thickness of 5 nm are formed on the inner surface of the wiring trench. A barrier film 65 having a three-layer structure is formed by sequentially forming a functional Ru film 69.

Next, after forming a Cu plating seed layer 71 having a thickness of 30 nm by an electroless plating method, a Cu plating film 72 is formed by an electrolytic plating method. Next, a CMP process is performed until the SiO ₂ cap film 64 is exposed to form a Cu embedded wiring 70.

Next, the thickness that again becomes an etching stopper on the entire surface is, for example, a 30 nm SiOC film 73, the thickness is, for example, 150 nm of porous silica film 74, and the thickness that becomes the middle stopper is, for example, a 30 nm SiOC film 75, thickness However, for example, a porous silica film 76 having a thickness of 150 nm and a SiO ₂ cap film 77 having a thickness of, for example, 100 nm are sequentially deposited.

Next, wiring trenches are formed in the SiO ₂ cap film 77 to the SiOC film 75, and via holes reaching the Cu embedded wiring 70 are formed in the porous silica film 74 and the SiOC film 73.

  Next, an oxide Ru film having a thickness of 1 nm, an amorphous Ru film containing nitrogen having a thickness of 3 nm, and a crystal not containing nitrogen having a thickness of 5 nm are formed on the inner surfaces of the wiring trench and the via hole by sputtering. A barrier film 78 having a three-layer structure is formed by sequentially forming a reactive Ru film.

Next, after forming a Cu plating seed layer having a thickness of 30 nm by an electroless plating method, a Cu plating film is formed by an electrolytic plating method. Next, a CMP process is performed until the SiO ₂ cap film 77 is exposed to form a Cu buried wiring 80 and a Cu plug 79.

  Next, after the dual damascene process is repeated according to the number of multilayer wiring structures required, a thickness that becomes an etching stopper is again formed on the wiring layer including the uppermost Cu embedded wiring 81, for example, a 30 nm SiOC film. 82 and a porous silica film 83 having a thickness of, for example, 150 nm is formed.

  Next, after forming a via hole that penetrates the porous silica film 83 and the SiOC film 82 and reaches the Cu buried wiring 81, a W plug 84 is formed by embedding W through the TiN film and performing CMP treatment.

  Next, after a pad 85 made of aluminum connected to the W plug 84 is formed on the porous silica film 83, the pad 85 and the porous silica film 83 are covered with a SiN protective film 86. Finally, an opening for exposing the surface of the pad 85 is formed in the SiN protective film 86, whereby the basic configuration of the semiconductor device according to the first embodiment of the present invention is completed.

  In the description of the above embodiment, the Cu embedded wiring 70 is connected to the W plug 61 via the barrier film 65. However, the barrier film 65 may be formed under the condition that the barrier film 65 is not deposited on the bottom of the wiring trench by adjusting the sputtering conditions when forming the barrier film 65. As a result, since the relatively high resistance barrier film 65 does not exist between the Cu embedded wiring 70 and the W plug 61, the series resistance becomes lower.

Here, regarding the embodiment of the present invention including Example 1, the following additional notes are disclosed.
(Additional remark 1) The insulating film, the recessed part provided in the said insulating film, the sealing insulating film formed in the side wall of the said recessed part, and the inside of the said recessed part, Comprising: A semiconductor device provided with a Cu-based embedded electrode formed through one conductive barrier layer, a second conductive barrier layer, and a third conductive barrier layer, wherein the third conductive The barrier layer has better adhesion to the Cu-based embedded electrode than the second conductive barrier layer, and the second conductive barrier layer is more capable of preventing Cu diffusion than the third conductive barrier layer. The semiconductor device is characterized in that the first conductive barrier layer has higher adhesion to the insulating film that seals the side wall than the second conductive barrier layer.
(Supplementary note 2) The semiconductor device according to supplementary note 1, wherein the seal insulating film is any one of silicon carbide, silicon oxycarbide, silicon nitride, silicon oxynitride, and silicon oxide.
(Supplementary Note 3) The semiconductor device according to Supplementary Note 1 or 2, wherein the first conductive barrier layer is ruthenium oxide.
(Supplementary note 4) The semiconductor device according to any one of supplementary notes 1 to 3, wherein the second conductive barrier layer is amorphous ruthenium containing nitrogen.
(Supplementary note 5) The semiconductor device according to any one of supplementary notes 1 to 4, wherein the third conductive barrier layer is crystalline ruthenium containing no nitrogen.
(Supplementary note 6) The metal concentration of the surface of the insulating film embedded with the Cu-based embedded electrode at the same height as the upper surface of the Cu-based embedded electrode is 5 × 10 ¹¹ atoms / cm ² or less. The semiconductor device according to any one of appendix 1 to appendix 5, wherein:
(Appendix 7) A step of forming a recess in the insulating film, a step of forming a seal insulating film on the side wall of the recess, and a first conductive barrier layer in the recess and inside the seal insulating film. A step of forming a film, a step of forming a second conductive barrier layer having a higher Cu diffusion prevention capability than the first conductive barrier layer on the first conductive barrier layer, and the second conductive property. Forming a third conductive barrier layer having better adhesion to Cu than the second conductive barrier layer on the barrier layer, and Cu so as to embed the recesses on the third conductive barrier layer. A step of depositing a system electrode material, the Cu system electrode material, the third conductive barrier layer, the second conductive barrier layer, and the first conductive barrier layer forming the recess Polishing is performed by chemical mechanical polishing until the surface of the insulating film is exposed. A method of manufacturing a semiconductor device, wherein the first conductive barrier layer has better adhesion to the seal insulating film than the second conductive barrier layer.
(Supplementary Note 8) After the planarization step, the surface of the exposed insulating film with an acidic or alkaline solution until the metal concentration on the surface of the exposed insulating film is 5 × 10 ¹¹ atoms / cm ² or less. The method for manufacturing a semiconductor device according to appendix 7, further comprising a step of cleaning the substrate.
(Supplementary note 9) The supplementary note 7 or the supplementary note 8, wherein the film forming step of the first conductive barrier layer is a step of forming a film of ruthenium by a physical vapor deposition method in an atmosphere containing oxygen. Semiconductor device manufacturing method.
(Appendix 10) Any one of appendix 7 to appendix 9, wherein the film forming step of the second conductive barrier layer is a step of forming ruthenium by a physical vapor deposition method in an atmosphere containing nitrogen. A method for manufacturing a semiconductor device according to claim 1.
(Supplementary Note 11) The supplementary note 7 to the supplementary note, wherein the film forming step of the third conductive barrier layer is a step of forming a ruthenium film by a physical vapor deposition method in an atmosphere not containing nitrogen and nitrogen. 10. A method for manufacturing a semiconductor device according to any one of 10 above.

DESCRIPTION OF SYMBOLS 1 Base insulating film 2 Plug 3 Interlayer insulating film 4 Insulating film 5 1st barrier metal film 6 2nd barrier metal film 7 3rd barrier metal film 8 Cu wiring 11 Base insulating film 12 Plug 13 Etching stopper film 14 Interlayer insulation Film 15 Cap film 16 Recess 17 for wiring 17 Seal insulating film 18 Oxide barrier film 19 Amorphous barrier metal film 20 Crystalline barrier metal film 21 Cu plating seed layer 22 Cu plating film 23 Cu embedded wiring 24 Etching stopper film 41 1 Layer Cu embedded wiring 42 Via 43 Second layer Cu embedded wiring 51 Silicon substrate 52 Element isolation insulating film 53 MOSFET
54 Gate insulating film 55 Gate electrode 56 Side wall 57 Source region 58 Drain region 59 Interlayer insulating films 60, 61, 84 W plugs 62, 73, 75, 82 SiOC films 63, 74, 76, 83 Porous silica films 64, 77 SiO ₂ Cap films 65, 78 Barrier film 66 Seal insulating film 67 Ru oxide film 68 Amorphous Ru film 69 Crystalline Ru film 70, 80, 81 Cu embedded wiring 71 Cu plating seed layer 72 Cu plating film 79 Cu plug 85 Al Pad 86 SiN protective film

Claims (5)

An insulating film;
A recess provided in the insulating film;
A seal insulating film formed on the sidewall of the recess;
Cu formed in the recess through the first conductive barrier layer, the second conductive barrier layer, and the third conductive barrier layer provided in order inside the seal insulating film. A semiconductor device provided with a system embedded electrode,
The third conductive barrier layer has better adhesion to the Cu-based embedded electrode than the second conductive barrier layer,
The second conductive barrier layer has a higher Cu diffusion blocking capability than the third conductive barrier layer, and
The semiconductor device according to claim 1, wherein the first conductive barrier layer has better adhesion to the insulating film that seals the side wall than the second conductive barrier layer.   The semiconductor device according to claim 1, wherein the first conductive barrier layer is ruthenium oxide.   The semiconductor device according to claim 1, wherein the second conductive barrier layer is amorphous ruthenium containing nitrogen.   4. The semiconductor device according to claim 1, wherein the third conductive barrier layer is crystalline ruthenium that does not contain nitrogen. 5. Forming a recess in the insulating film;
Forming a seal insulating film on the side wall of the recess;
Forming a first conductive barrier layer in the recess and inside the seal insulating film;
Forming a second conductive barrier layer on the first conductive barrier layer, the second conductive barrier layer having a higher Cu diffusion blocking ability than the first conductive barrier layer;
Forming a third conductive barrier layer having better adhesion to Cu than the second conductive barrier layer on the second conductive barrier layer;
Depositing a Cu-based electrode material on the third conductive barrier layer so as to embed the recess;
The Cu-based electrode material, the third conductive barrier layer, the second conductive barrier layer, and the first conductive barrier layer are exposed until the surface of the insulating film in which the recess is formed is exposed. The first conductive barrier layer has better adhesion to the seal insulating film than the second conductive barrier layer. A method for manufacturing a semiconductor device.

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