JP2011008888A - Memory device testing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten total testing time by restricting data to be calculated.SOLUTION: The memory device testing device equipped with a fail memory for storing a plurality of pieces of fail data of a memory device, having a plurality of pins and a buffer memory 5 provided corresponding to the fail memory 3 includes a fail-flag generating unit 22 for generating a fail flag, indicating the presence or the absence of fail for each pin of the fail data; a data-erasing unit 42 for generating erase data in which a pin part where fail is not present is erased from the fail data, on the basis of the fail flag; a data-coupling unit 47 for generating coupled data in which the plurality of erase data are coupled, to be made equal to or less than the bit number of the fail data and storing the coupled data in the buffer memory 5; and a calculation unit 6 for calculating with respect to the coupled data stored in the buffer memory 5, on the basis of the fail flag.

Description

  The present invention relates to a memory device testing apparatus for testing a memory device, and more particularly to a memory device testing apparatus including a fail memory and a buffer memory.

  Memory devices such as DRAM and SRAM are defective as a whole when even one memory cell is defective. For this reason, the memory device is tested to detect a defective cell. The memory device is provided with a spare memory cell, and when a defective cell is detected, the signal line connection is switched to the spare memory cell to repair the memory device. An operation for performing this relief is generally called a redundancy operation. The redundancy calculation is performed by dedicated calculation means, and based on the result, switching from the defective memory cell to the spare memory cell is performed by the laser means or the like.

  FIG. 6 shows a conventional memory device testing apparatus that performs redundancy calculation. This memory device test apparatus is schematically configured to include a comparator unit 101, an interface unit 102, a fail memory 103, a memory control unit 104, a buffer memory 105, and a calculation unit 106.

  The comparator unit 101 receives an output signal from a memory device (not shown) and compares it with a reference value held by itself to generate a 1-bit pass / fail signal consisting of pass (normal) or fail (abnormal). This is the memory device pass / fail determination. The memory device includes a plurality of input / output pins (hereinafter simply referred to as “pin”), and generates a pass / fail signal simultaneously output from the plurality of pins as one fail data. When the number of pins is M (M is an integer), the fail data has an information amount of M bits. Hereinafter, description will be made assuming that M = 8.

  The interface unit 102 serves as an interface for inputting to the fail memory 103 output from the comparator unit 101. The fail memory 103 is storage means for accumulating fail data. When a predetermined amount of fail data is accumulated in the fail memory 103, the memory control unit 104 copies the fail data to the buffer memory 105 (dead copy). The calculation unit 106 is a means for performing the redundancy calculation, and reads the fail data stored in the buffer memory 105 to perform the redundancy calculation.

  The comparator unit 101 sequentially generates fail data, and the fail data is accumulated in the fail memory 103. The fail memory 103 is provided with N addresses (N is an integer) from addresses Add1 to AddN, and the fail data output from the comparator unit 101 is accumulated in order from the top address.

  When a predetermined amount (N) of fail data is accumulated in the fail memory 103, the contents of the fail memory 103 are copied to the buffer memory 105 by the memory control unit 104. As shown in FIG. 7, the addresses Add1 to AddN are also assigned to the buffer memory 105, and the same contents as the fail memory 103 are stored in the same address. In FIG. 7, P1 to P8 indicate pins of the memory device.

  Then, a redundancy calculation is performed on the fail data in the buffer memory 105 by the calculation unit 106. FIG. 8 shows a state where the redundancy calculation is performed on the fail data in the buffer memory 105. A redundancy operation is performed on fail data from the fail data at the head address Add1 of the buffer memory 105 to the Nth address AddN in order. Performing this redundancy calculation is referred to as scanning. Therefore, the redundancy calculation is completed by scanning the fail data from the head address to the Nth address.

  For example, Patent Document 1 discloses a semiconductor memory test apparatus including a fail memory and a buffer memory for performing the above redundancy calculation.

JP 2008-59688 A

  In recent years, memory devices tend to have a large capacity, and the amount of information of fail data becomes enormous. As the amount of fail data information increases, the buffer memory 105 tends to increase in capacity. The arithmetic unit 106 sequentially scans from the head address of the buffer memory 105, and since the amount of information stored in the buffer memory 105 is enormous, a large calculation time is required for the redundancy calculation.

  On the other hand, memory devices in recent years are manufactured with high precision, and so many failures do not occur. For this reason, the failure to be relieved is only a part of the large-capacity fail data, and scanning data that does not have fail data causes a significant time loss. Shortening the test time of the memory device is an essential proposition, and this time loss greatly affects the test time.

  Therefore, an object of the present invention is to shorten the entire test time by limiting the data to be calculated.

  In order to solve the above problems, a memory device test apparatus according to claim 1 of the present invention includes a fail memory for storing a plurality of fail data of a memory device having a plurality of input / output pins and a buffer provided corresponding to the fail memory. A memory device test apparatus including a memory, a fail flag generation unit configured to generate a fail flag indicating whether or not a failure exists for each fail data input / output pin, and the fail data based on the fail flag A data deletion unit that generates deletion data by deleting a portion of the input / output pin where no fail exists, and a combination of a plurality of deletion data to generate combined data that is equal to or less than the number of bits of the fail data to generate the buffer memory A data combining unit to be stored in the buffer memory and the buffer memory based on the fail flag. Characterized in that and a calculation unit for performing an operation on said stored coupling data.

  According to this memory device test apparatus, a plurality of deletion data are stored in one address of the buffer memory. The deletion data is data obtained by deleting unnecessary information from the fail data, and has all the information necessary for the calculation. Thus, an operation can be performed based on combined data obtained by combining a plurality of deletion data, and a plurality of deletion data is stored at one address of the buffer memory, so that the amount of information stored in the buffer memory Can be greatly reduced, and the calculation time can be shortened. Since the calculation unit calculates the combined data based on the fail flag, the calculation unit can perform the calculation because the information of the deleted input / output pins is obtained.

  According to the present invention, the combined data obtained by combining a plurality of deletion data is stored in the buffer memory, so that the amount of information to be calculated can be greatly reduced. Thereby, since calculation time can be shortened, shortening of test time can be achieved. Since the deletion data is generated by deleting the information of the input / output pins without fail, the necessary information is not lost from the fail data. The calculation unit can normally calculate based on the deletion data of the combined data and the fail flag.

It is a block diagram which shows schematic structure of the memory device test apparatus of this invention. It is a figure which shows fail data and a fail flag. It is a figure explaining a buffer and a selector. It is a figure explaining deletion data and combined data. It is a figure explaining a fail memory and a buffer memory. It is a block diagram which shows schematic structure of the conventional memory device test apparatus. It is a figure which shows the structure of the conventional buffer memory. It shows conventional fail data.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a schematic configuration of a memory device test apparatus. This memory device test apparatus is schematically configured to include a comparator unit 1, an interface unit 2, a fail memory 3, a memory control unit 4, a buffer memory 5, and a calculation unit 6. The comparator unit 1 is connected to a memory device (not shown), and compares the reference value held by itself with the output data from the memory device to perform pass / fail judgment (pass / fail judgment). The result of pass / fail judgment is pass / fail information expressed by 1 bit of pass (normal) or fail (abnormal). In the following, it is assumed that the path is expressed by “0” and the failure is expressed by “1”.

  The memory device has M (M is an integer) input / output pins (hereinafter simply referred to as pins), and the comparator unit 1 simultaneously performs pass / fail judgment on the output data transferred from each pin, M pieces of pass / fail information are generated simultaneously. Data composed of M pieces of pass / fail information is defined as fail data. Therefore, the fail data has an information amount of M bits. Output data is continuously transferred from the memory device, and the comparator unit 1 sequentially generates fail data.

  The interface unit 2 includes an I / F 21 and a fail flag generation unit 22. The I / F 21 is an interface for outputting fail data input from the comparator unit 1 to the fail memory 3. The fail flag generation unit 22 generates a fail flag indicating whether or not a failure exists for each pin based on the fail data. A fail flag is generated with “1” when there is a failure and “0” when there is no failure. Fail data is sequentially input to the fail flag generator 22 and a logical sum is taken for each pin of the fail data. As a result, a fail flag that can recognize whether or not at least one fail exists for each pin for all the fail data is generated.

  The fail memory 3 is storage means for sequentially storing fail data output from the I / F 21 of the interface unit 2. The fail memory 3 can store N (N is an integer) pieces of fail data, and N addresses from Add 1 to Add N are attached. Fail data sequentially output from the I / F 21 is accumulated in order from the head address. One address stores M-bit data. Therefore, the fail memory 3 has a capacity capable of storing M × N-bit information.

  The memory control unit 4 includes a data fetch unit 41, a data deletion unit 42, a buffer 43, a selector 44, a pin number storage unit 45, and a selector control unit 46. The data take-in unit 41 takes out all the fail data when N pieces of fail data are accumulated in the fail memory 3. The extracted fail data is output to the data deleting unit 42 and the selector 44.

  The data deleting unit 42 receives fail data from the data fetching unit 41 and receives a fail flag from the fail flag generating unit 22. The data deleting unit 42 refers to the fail flag, and deletes the part of the pin where no fail exists (the pin whose fail flag is “1”) from each fail data. This deleted data is referred to as deleted data.

  The buffer 43 is a buffer for accumulating deletion data generated by the data deletion unit 42. This buffer has a capacity capable of storing at least N deletion data. However, since the deleted data is data obtained by deleting a part of the fail data, the deleted data has a smaller capacity than the fail memory 3. The selector 44 selects either the fail data output from the data fetch unit 41 or the deletion data stored in the buffer 43. At this time, the selector 44 selects one fail data from the data fetch unit 41, but selects a plurality of deletion data from the buffer 43.

  The pin number storage unit 45 stores the pin number M of the memory device. This number of pins is preset as a prescribed value by the user or the like. The selector control unit 46 inputs the number of pins of the memory device from the pin number storage unit 45 and inputs the fail flag from the fail flag generation unit 22. The selector control unit 46 refers to the fail flag and counts the number of faces (the number of pins that are “1” in each bit of the fail flag). The counted value is set as the failure number C and compared with the number M of pins of the memory device. Then, M is divided by C. This divided value is defined as a division value D.

  The selector control unit 46 determines whether or not the division value D is 2 or more, and outputs a selection signal indicating whether the mode is the normal mode or the deletion mode to the selector 44. When the division value D is less than 2, the normal mode is selected, and when it is 2 or more, the deletion mode is selected. The normal mode is a mode in which one fail data is selected as it is from the data fetch unit 41 and is output to the buffer memory 5. The deletion mode is a mode in which a plurality of deletion data is selected from the buffer 43, and the selected deletion data is combined and output to the buffer memory 5. When the deletion mode is selected, the selector control unit 46 sets the value obtained by truncating the division value D after the decimal point as the maximum integer value V, and outputs the value of V to the selector 44. Since the number of bits of the fail flag is the number of pins M of the memory device, M may be recognized from the number of bits of the fail flag without providing the pin number storage unit 45.

  The selector 44 selects a plurality of deletion data in the deletion mode. The number of deleted data to be selected is the maximum integer value V described above. N pieces of deleted data are stored in the buffer 43 in order from the top. Among the deleted data, V pieces of deleted data are extracted and combined in order from the top to generate one combined data. The number of bits of the combined data is set to be equal to or less than the number of bits of fail data. There are N pieces of deleted data, but the combined data is a combination of V deleted data. For this reason, the number of combined data is N / V. The buffer 43 and the selector 44 constitute a data combining unit 47 that generates combined data.

  The buffer memory 5 inputs either the fail data or the combined data from the selector 44 and performs accumulation. Like the fail memory 3, the buffer memory 5 has N addresses from Add1 to AddN, and each address stores fail data or combined data. Since which mode is selected between the normal mode and the deletion mode depends on the fail data, the buffer memory 5 has an information amount of M × N bits in advance.

  When the normal mode is selected, the selector 44 selects fail data one by one. Therefore, N pieces of fail data are stored in the buffer memory 5 in the order of addresses. On the other hand, when the deletion mode is selected, N / V pieces of combined data are stored in the buffer memory 5. Therefore, the buffer memory 5 stores an information amount of M × N bits in the normal mode, and stores an information amount of M × (N / V) bits in the deletion mode.

  The computing unit 6 performs redundancy computation on the data stored in the buffer memory 5 in order from the top address. Scanning is to perform redundancy calculation in the order of addresses (from Add1 to AddN). The arithmetic unit 6 receives the fail flag from the fail flag generation unit 22 and receives the selection signal and the maximum integer value V from the selector control unit 46. When the selection signal indicates the normal mode, the calculation unit 6 performs a redundancy calculation on the fail data in all the buffer memory 5 (from Add1 to AddN). When the selection signal indicates the deletion mode, the calculation unit 6 performs a redundancy calculation on the fail data at the addresses from Add1 to Add (N / V). Further, the calculation is performed by specifying a pin to be calculated with reference to the fail flag. Note that as the calculation performed by the calculation unit 6, any calculation other than the redundancy calculation can be applied.

  The operation in the above configuration will be described. In the following description, the number of pins M of the memory device is described as M = 8 for the sake of explanation.

  The comparator unit 1 performs pass / fail judgment of output data from a memory device (not shown) and generates 1-bit pass / fail information. Since the number of pins is 8, fail data composed of 8-bit pass / fail information is generated. The fail data is sequentially stored in the fail memory 3 via the I / F 21 and is output to the fail flag generation unit 22.

  The fail flag generation unit 22 generates a fail flag as shown in FIG. FIG. 2 shows an example of fail data and a fail flag, and the fail flag generation unit 22 calculates a logical sum for each pin for the fail data that is sequentially input. In the case of FIG. 2, P3, P4, P5, and P7 have no failure, so even if the logical sum is calculated, the result is “0” (in FIG. 2, a frame is displayed in the portion where the fail flag is “1”). ) On the other hand, since there is a failure in at least one fail data in P1, P2, P6, and P8, the result becomes “1” when the logical sum is calculated. By performing the above logical sum operation in the order of addresses, the 8-bit fail flag shown in FIG. 2 is generated. Of these 8 bits, the 1st to 8th bits correspond to the pins P1 to P8, respectively.

  The data deletion unit 42 deletes the pass / fail information of a pin for which no failure exists from the fail data. For this purpose, the data deleting unit 42 reads the fail flag from the fail flag generating unit 22. The third, fourth, fifth and seventh bits of the fail flag are “0”, and it can be recognized that the pins where no fail exists are P3, P4, P5 and P7. Then, the data deletion unit 42 deletes the pass fail information of the four pins, that is, the third, fourth, fifth, and seventh bit portions from all (N) pieces of fail data to generate deletion data. Thus, the deletion data becomes 4-bit information having only the information of the pins P1, P2, P6, and P8, that is, the first, second, sixth, and eighth bits in the fail data.

  The generated deletion data is stored in the buffer 43 in the order of addresses. In the deletion data, information of four pins is deleted from the fail data, and the information amount is half. The deletion data stored in the buffer 43 is shown in FIG. As shown in the figure, the buffer 43 can store N pieces of deletion data from Add1 to AddN, and each piece of deletion data includes a total of four pieces of pass-fail information of P1, P2, P6, and P8. ing. However, each deleted data is 4-bit information.

  Here, the selector control unit 46 acquires the pin number M stored in the pin number storage unit 45. Further, the fail number C is obtained by referring to the 8-bit fail data and counting the number of bits that are “1”. Then, the pin number M is divided by the fail number C to obtain a division value D, and the decimal part is rounded down to obtain the maximum integer value V. Here, since M = 8 and C = 4, the division value D and the maximum integer value V are V = 2. In order to recognize that V is 2 or more, the selector control unit 46 outputs a selection signal indicating the deletion mode to the selector 44 and simultaneously outputs the maximum integer value V (V = 2) to the selector 44.

  The selector 44 recognizes the deletion mode by inputting the selection signal and the maximum integer value V. For this reason, a plurality of deletion data are selected from the buffer 43. Since the maximum integer value V = 2, the buffer 43 selects two pieces of data in order from the top and combines these deleted data. For example, the deletion data of Add2 selected next is combined with the deletion data of Add1 selected first. As a result, the combined data shown in FIG. 4 is generated. This combined data is obtained by combining two pieces of 4-bit deletion data, and has a total of 8 bits, so it is equal to the amount of information of fail data. Thereafter, the deletion data of the two addresses before and after are selected and combined to generate combined data. In FIG. 3, the selected deletion data is indicated by “*”.

  The combined data generated by the selector 44 is output to the buffer memory 5. The buffer memory 5 sequentially stores the combined data in the order of addresses. FIG. 5 shows a fail memory 3 and a buffer memory 5. The buffer memory 5 can store not only the combined data but also fail data, so that information of 8 bits per address can be stored. Since the combined data is also 8-bit information, it can be stored.

  One combination data, that is, two deletion data is stored in one address of the buffer memory 5. In FIG. 5, 8 bits of one address of the buffer memory 5 are divided into a lower bit group from the 1st bit to the 4th bit and an upper bit group from the 5th bit to the 8th bit. The lower bit group is the reduced data of the address Add2, and the upper bit group is the reduced data of the address Add1. The combined data obtained by combining these occupies one address Add1 of the buffer memory 5. At this time, the number of deleted data is N, but since the combined data is a combination of two deleted data, the number of combined data is N / 2. That is, the addresses up to address Add (N / 2) are used, and the subsequent addresses are not used. For this reason, the amount of data stored in the buffer memory 5 is substantially halved.

  The calculation unit 6 reads the contents of Add (N / 2) from the address Add1 of the buffer memory 5 and performs a redundancy calculation. However, not the fail data but the combined data is stored in the buffer memory 5, and the pin to be calculated cannot be specified. In the redundancy calculation, if the pin of the memory device is not specified, the memory cell in which the failure has occurred cannot be specified. Therefore, the calculation unit 6 inputs the fail flag from the fail flag generation unit 22 and the pin of the memory device To identify.

  Since the calculation unit 6 receives the selection signal indicating the deletion mode from the selector control unit 46, the calculation unit 6 recognizes that the data stored in the buffer memory 5 is combined data. Then, the fail flag is read to check the bit where the fail exists. This is done by recognizing a bit that is “1” in the fail flag. Here, the first, second, sixth, and eighth bits are “1”. As a result, it is recognized that it is necessary to perform a redundancy operation on these pins. In other words, since the third, fourth, fifth and seventh bits are “0”, it is recognized that these bits do not need to be operated.

  That is, even if the combined data is a combination of deletion data obtained by deleting some information from the fail data, by referring to the fail flag, the pin to be repaired can be identified. It becomes possible to do.

  By the way, since the fail memory can also be stored in the buffer memory 5, it has the same capacity (M × N bits) as the fail memory 3. However, in the delete mode, the buffer memory 5 stores the combined data from Add1 to Add (N / 2). For this reason, it is not necessary to scan the redundancy calculation for all addresses. At this time, since the arithmetic unit 6 obtains information of the maximum integer value V = 2 from the selector control unit 46, it can be recognized that it is sufficient to scan addresses from the head to half (N / 2). As a result, only half of the buffer memory 5 is scanned, so that the computation time can be substantially halved.

  As described above, the present invention generates a fail flag indicating whether or not a fail exists for each pin of each fail data, and deletes pass / fail information of a pin that does not have a fail. As a result, the amount of data stored in the buffer memory 5 can be made very small, and the amount of calculation can be reduced. Thereby, shortening of the test time can be achieved. Note that the information of the deleted fail data is information in which no failure exists, and even if it is deleted, there is no particular problem.

  The maximum integer value V = 2 has been described above, but V may be 3 or more. As described above, when the deletion mode is selected, the amount of information stored in the buffer memory 5 is M × (N / V) bits, and the larger the value of V, the smaller the amount of calculation and the higher the amount. The test time can be shortened. For example, when the memory device is M = 8 and the number of pins in which a fail exists, that is, the number of fail flags C is C = 2, the division value D is D = M / C = 4, and the maximum integer value V V = 4. Thereby, the calculation time can be substantially reduced to ¼.

  Further, although the case where the division value D is an integer has been described, D may include a decimal. For example, when the number of pins M = 8 and the number of failures C = 3, D = 2.66... In this case, the maximum integer value V is a value obtained by discarding the decimal part of D, and V = 2. That is, the combined data is composed of two deleted data. Since the number of failures C is C = 3, the deletion data is also 3 bits, and the combined data is composed of two 3-bit deletion data. For this reason, the combined data is 6 bits. On the other hand, since the fail data and the buffer memory 5 have an 8-bit configuration, the number of bits differs. In this case, the number of bits is made consistent by inserting dummy bits into the upper 2 bits (7th and 8th bits) or the lower 2 bits (1st and 2nd bits).

  Of course, even if the number of failures C is 3, when the number of pins M is 9, D = 3 and the computation time can be reduced to about 1/3. However, in any case, D must be 2 or more. This is because memory access is normally performed for all bits of one address, and only some of these bits cannot be accessed. When D is less than 2, a plurality of deletion data cannot be stored in one address of the buffer memory 5, so that the effect of shortening the calculation time cannot be obtained.

  On the other hand, it is possible to access a part of the N addresses of the buffer memory 5, and when D is 2 or more, the number of addresses to be accessed is half or less. For this reason, it is possible to obtain a significant reduction in calculation time.

DESCRIPTION OF SYMBOLS 3 Fail memory 4 Memory control part 5 Buffer memory 6 Operation part 22 Fail flag production | generation part 41 Data acquisition part 42 Data deletion part 43 Buffer 44 Selector 45 Pin number memory | storage part 46 Selector control part 47 Data coupling | bond part

Claims (1)

A memory device test apparatus comprising a fail memory for storing a plurality of fail data of a memory device having a plurality of input / output pins and a buffer memory provided corresponding to the fail memory,
A fail flag generating unit that generates a fail flag indicating whether or not a fail exists for each input / output pin of each fail data;
A data deletion unit that generates deletion data by deleting a part of an input / output pin where the failure does not exist from the fail data based on the fail flag;
A data combining unit that combines a plurality of deletion data to generate combined data that is equal to or less than the number of bits of the fail data and stores the combined data in the buffer memory;
An arithmetic unit that performs an operation on the combined data stored in the buffer memory based on the fail flag;
A memory device testing apparatus comprising:

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