JP2011008874A - Method for testing semiconductor memory device and semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To stably measure a current flowing during a writing operation in a memory cell without requiring fine voltage control.SOLUTION: The memory cell includes: first and second CMOS inverters each including a drive MOS transistor and a load MOS transistor and having input/output terminals thereof connected in an intersecting manner; and first and second transfer MOS transistors having gate terminals connected to word lines. The first and second CMOS inverters and first and second bit lines are connected via the first and second transfer MOS transistors. The power supply lines of the first and second CMOS inverters are separated from each other. The power supply line of one CMOS inverter is set to a power supply voltage, and the power supply line of the other CMOS inverter is set to a ground voltage. The first and second bit lines are set to ground voltages, and the word line is set to a power supply voltage. A write current flowing from the power supply line of one CMOS inverter via the load MOS transistor of one CMOS inverter, one transfer MOS transistor, and one bit line is measured.

Description

  The present invention relates to a semiconductor memory device testing method and a semiconductor memory device, and more particularly, to stably measure a current flowing in a memory cell included in a semiconductor memory device during a write operation to the semiconductor memory device, and to write in the memory cell. The present invention relates to a technique for detecting a defect in a path.

  One of the semiconductor memory devices is an SRAM (Static Random Access Memory). At the time of manufacturing the SRAM, various tests for detecting defects are performed at various stages.

  As a general example of an SRAM test method, there is a method of writing an arbitrary “0” or “1” test pattern to the SRAM and testing whether the written value can be read correctly from the SRAM.

  However, in recent years, the causes of failures have become complicated due to process miniaturization in SRAMs, and it has become difficult to detect potential defects in SRAMs by the test method based on the above test pattern.

  Therefore, recently, as an SRAM test method, there has been an increasing need for a method of measuring physical quantities such as a voltage value, a current value, and a delay margin, and determining whether a memory cell is good or bad based on the measured physical quantities. ing. Among these, the test method for measuring the current flowing in the memory cell is generally performed as a method capable of directly observing the characteristics of the memory cell.

  FIG. 5 is a diagram illustrating an example of a circuit configuration of a related SRAM memory cell (hereinafter referred to as an SRAM memory cell). This circuit configuration is a generally well-known circuit configuration.

  The SRAM memory cell 100 shown in FIG. 5 is composed of six general MOS transistors. That is, the SRAM memory cell 100 includes driving MOS transistors N1 and N2 that are N channel MOS transistors, transfer MOS transistors N3 and N4 that are N channel MOS transistors, load MOS transistors P1 and P2 that are P channel MOS transistors, It is composed of

  In FIG. 5, PL is a power line of the SRAM memory cell 100, GL is a ground line of the SRAM memory cell 100, BLT and BLB are bit lines of the SRAM memory cell 100, WL is a word line of the SRAM memory cell 100, ND1 and ND2 is a data holding node of the SRAM memory cell 100.

  Vdd is a voltage supplied from the power line PL, Vss is a voltage supplied from the ground line GL, Vwl is a voltage supplied from the word line WL, and Vblt and Vblb are voltages supplied from the bit lines BLT and BLB, respectively. , Vn1 and Vn2 are voltages of the data holding nodes ND1 and ND2, respectively.

  The driving MOS transistor N1 and the load MOS transistor P1, and the driving MOS transistor N2 and the load MOS transistor P2 constitute a CMOS inverter, respectively. The driving MOS transistors N1 and N2 and the load MOS transistors P1 and P2 constitute a coupling of a CMOS inverter, so that data can be stably held.

  The voltages Vn1 and Vn2 of the data holding nodes ND1 and ND2 are either “1” or “0”, respectively, and are opposite to each other. The definition of 1-bit data held in one SRAM memory cell 100 is, for example, defined as Vn1 = “1” and Vn2 = “0” in the case of data “1”, and in the case of data “0”. Vn1 = "0" and Vn2 = "1" are defined.

  Here, “1” in digital notation corresponds to the power supply voltage (Vdd), and Vdd is usually 1.0 V in a 90 nm generation LSI (Large Scale Integration) manufacturing process. Also, “0” in digital notation corresponds to the ground voltage (Vss), and Vss is usually 0V.

  The SRAM operation includes a read operation and a write operation.

  In the read operation, the bit lines BLT and BLB are precharged to “1” and the word line WL is set to “1”. As a result, a current through path is formed from either one of the bit lines BLT or BLB through the transfer MOS transistor and the driving MOS transistor to the ground line GL, a read current flows through the path, and the voltage of the bit line decreases. At this time, if the data held in the SRAM memory cell 100 is “0”, the voltage of the bit line BLT decreases, and if it is “1”, the voltage of the bit line BLB decreases. Therefore, the data held in the SRAM memory cell 100 can be read from the outside of the SRAM memory cell 100 by detecting which voltage of the bit line BLT or BLB has decreased.

  As described above, in the read operation, since the data is held in the SRAM memory cell 100, the read current flowing in the SRAM memory cell 100 can be measured stably.

  On the other hand, in the write operation, the voltage of one bit line is set to “0” and the word line WL is set to “1” in accordance with the write data. Thereby, a current through path (hereinafter referred to as a write path) is generated from the power supply line PL to the bit line through the load MOS transistor and the transfer MOS transistor, and a write current flows through the path. When the write current flows, the voltages Vn1 and Vn2 of the data holding nodes ND1 and ND2 are inverted, so that data can be written into the SRAM memory cell 100.

  Thus, in the write operation, the data held in the SRAM memory cell 100 is inverted. Therefore, when data “0” is written while data “1” is held, the write current flowing through the SRAM memory cell 100 cannot be measured stably. The reason will be explained. In this case, when the write operation is completed, the voltages Vn1 and Vn2 of the data holding nodes ND1 and ND2 are inverted, Vn1 = “0” and Vn2 = “1”, and the load MOS transistor P1 is turned off. At this time, the above-described write path does not exist and a write current cannot be obtained. For this reason, the write current does not flow constantly, and the write current cannot be measured stably.

  Incidentally, in recent years, various related technologies relating to SRAM memory cells have been disclosed.

  For example, Non-Patent Document 1 discloses a technique for measuring a current flowing in an SRAM memory cell while maintaining the circuit configuration shown in FIG. In this technology, in the SRAM memory cell, the terminals of the word line WL, the bit lines BLT and BLB, and the power supply line PL are connected to the outside through pads. Then, the current flowing in the SRAM memory cell is measured by supplying various voltages to each terminal from the outside. At this time, an overdrive voltage (voltage higher than the power supply voltage Vdd) VH is prepared separately from the power supply voltage Vdd and the ground voltage Vss, and the supply voltage to each terminal is optimized. For example, in FIG. 5, when the MOS transistor to be measured is the drive MOS transistor N1, the transfer MOS transistors N3 and N4 are turned on. In this case, the voltage of the word line WL is set to VH and the transfer is performed. The resistance value between the drain and source of the MOS transistors N3 and N4 is drastically reduced, and the voltage drop in the transfer MOS transistors N3 and N4 is suppressed. As a result, the power line PL and the bit line BLT play the role of the drain voltage of N1, and the bit line BLB plays the role of the gate voltage of N1, respectively. Therefore, the current characteristics of the current flowing through the drive MOS transistor N1 (for example, It is possible to measure (drain current-gate-source voltage characteristics).

  Non-Patent Document 2 discloses a technique for measuring read characteristics and write characteristics of an SRAM memory cell having a circuit configuration different from that shown in FIG. In the SRAM memory cell to which this technology is applied, the ground lines GL of the left and right CMOS inverters are separated in advance. In this technique, in the read operation, the voltages of the two ground lines are controlled independently, and the voltage of one of the ground lines is finely changed to a high voltage of 0 V or higher. However, in this read operation, since one of the ground lines is set to 0 V or more, the potential of the data holding node that holds the voltage “0” rises, and data is not normally held, and finally held. Data is inverted. On the other hand, in the write operation, one bit line voltage is finely changed and set to a voltage lower than the power supply voltage Vdd. However, in this write operation, one bit line voltage is set not to 0V but to a voltage of 0V or more. Therefore, when data is written, the potential of the data holding node that holds the voltage “0” becomes 0 V or higher in accordance with the bit line potential, so that the holding data is not normally inverted. That is, this technique acts in a direction that inhibits the read operation and the write operation in the SRAM memory cell. Therefore, in the case of the read operation, by observing the ground line voltage immediately before the retained data is inverted, it is possible to measure the voltage range in which the read operation is not hindered as the read characteristic. In the case of the write operation, by observing the bit line voltage immediately before the retained data is not inverted, a voltage range in which the write operation is not hindered can be measured as the write characteristic.

  Patent Document 1 discloses a technique for performing a reset operation of an SRAM memory cell having a circuit configuration different from that shown in FIG. In the SRAM memory cell to which this technique is applied, as shown in FIG. 6, the power supply lines PL of the left and right CMOS inverters are separated in advance, and the power supply voltage of one of the CMOS inverters is set to the ground voltage Vss. In FIG. 6, in the SRAM memory cell 110, the power lines of the first CMOS inverter 111 and the second CMOS inverter 112 are defined as PLT and PLB, respectively. In this technique, for example, when the voltage Vdt of the power supply line PLT of the first CMOS inverter 111 is set to Vdd and the voltage Vdb of the power supply line PLB of the second CMOS inverter 112 is set to Vss, the voltage Vn2 of ND2, that is, the first CMOS inverter 111 is set. Is forcibly set to Vss. Thereby, the voltage Vn1 of ND1, that is, the output voltage of the first CMOS inverter 111 is set to Vdd. That is, in this technique, regardless of the data held in the SRAM memory cell 110 before this operation, the voltage setting of the data holding nodes ND1 and ND2 is forcibly performed and the reset operation is possible. In this technique, voltage setting of the word line WL and the bit lines BLT and BLB is not necessary.

JP-A-5-74163

X. Deng, W. Kit Loh, B. Pious, TW Houston, L. Liu, B. Khan, D. Corum, J. Raval, J. Gertas, F. Rousey, J. Steck, C. Suwannakinthorn, and R McKee, “Characterization of bit transistors in a functional SRAM,” IEEE / JSAP 2008 Symposium on VLSI Circuits Digest of Technical Papers, pp.44-45, June 2008. A. Katayama, T. Yabe, O. Hirabayashi, Y. Takeyama, K. Kushida, T. Sasaki, and N. Otsuka, “Direct cell-stability test techniques for an SRAM macro with asymmetric cell-bias-voltage modulation,” Proceeding of the IEEE International Test Conference, paper 25.1, Nov. 2008.

  As described above, the SRAM memory cell has a problem that the write current flowing in the SRAM memory cell cannot be stably measured in the write operation.

  In order to solve this problem, it is conceivable to apply the techniques disclosed in Non-Patent Documents 1 and 2 and Patent Document 1 described above.

  However, in the techniques disclosed in Non-Patent Documents 1 and 2, an overdrive voltage VH different from the power supply voltage and the ground voltage is required for measuring one MOS transistor, or it is supplied to the SRAM memory cell. There is a problem that the evaluation time increases because the voltage must be finely changed, and the cost for evaluation increases.

  Here, when the write current flowing in the SRAM memory cell having the circuit configuration shown in FIG. 5 is measured, if both power lines of the two CMOS inverters are set to Vdd, defect detection by measuring the write current is performed. Explain that it is difficult. In the SRAM memory cell having the circuit configuration shown in FIG. 5, the voltage of the power line PL of the two CMOS inverters is set to Vdd, the two bit lines BLT and BLB are set to Vss, and the voltage of the word line WL is set to “ It is set to 1 ″ (see FIG. 7A). Then, the voltages Vn1 and Vn2 of the data holding nodes ND1 and ND2 rise from Vss. FIG. 7B is a so-called butterfly plot, where the horizontal curve shows the voltage of Vn2 when the voltage of Vn1 is forcibly controlled from 0 V to Vdd from the outside, and the vertical curve shows the voltage of Vn2. The voltage of Vn1 when the voltage is forcibly controlled from 0 V to Vdd from the outside is shown. In FIG. 5, since the input / output terminals of the two CMOS inverters are cross-connected, the voltage value at the intersection P of the two curves is a voltage that can exist as Vn1 and Vn2. Since the curve of this butterfly plot is also determined by MOS transistors other than the write path to be measured, the voltages Vn1 and Vn2 of the data holding nodes ND1 and ND2 can be determined by characteristics other than the write path. That is, since the write current may vary due to a part other than the write path, even if the write current of the SRAM memory cell varies, it is difficult to specify that the cause of the variation is in the write path.

  Further, as in Non-Patent Document 2, a technique of controlling the voltage of the ground line by separating the ground line of the SRAM memory cell with the left and right CMOS inverters is not suitable for measuring the write current. The reason will be explained. In order to flow the write current stably, at least the load MOS transistor needs to be in the ON state. For this purpose, the gate voltage of the load MOS transistor constituted by the P-channel MOS transistor, that is, the input voltage of the CMOS inverter Needs to be 0V. However, when the ground line voltage is set to a voltage higher than 0V by the voltage control of the ground line, the input / output voltage of the CMOS inverter inevitably becomes a voltage higher than 0V. In other words, it does not satisfy the condition that the write current flows stably, and cannot be said to be a configuration for measuring the write current.

  In addition, as in Patent Document 1, the technique of separating the power supply line by the left and right CMOS inverters of the SRAM memory cell and setting the voltage of the power supply line of one CMOS inverter to Vss cannot measure the target write current. it is obvious. The reason will be explained. In this technique, since the voltage of the word line and the bit line is not set, the voltage of the word line is “0”. Therefore, the transfer MOS transistor is not turned on, a write path is not generated from the CMOS inverter toward the bit line, and a write current to be measured does not flow.

  In view of the above problems, an object of the present invention is to test a semiconductor memory device capable of stably measuring a write current flowing in a memory cell and detecting a defect in a write path of the memory cell without finely controlling a voltage. A method and a semiconductor memory device are provided.

In order to achieve the above object, a test method for a semiconductor memory device of the present invention includes:
First and second CMOS inverters, each of which is composed of an N-channel driving MOS transistor and a P-channel load MOS transistor and whose input / output terminals are cross-connected to each other, and first and second CMOS inverters each having a gate terminal connected to a word line. An N-channel transfer MOS transistor, wherein the first CMOS inverter and the first bit line are connected via the first N-channel transfer MOS transistor, and the second CMOS inverter and the first bit line are connected to each other. A test method for a semiconductor memory device comprising a memory cell connected to the second bit line via the second N-channel transfer MOS transistor, and the power lines of the first and second CMOS inverters are separated Because
A voltage of a power line of one of the first and second CMOS inverters is set to a power voltage;
Setting the voltage of the power line of the other CMOS inverter of the first and second CMOS inverters to a ground voltage;
Setting the voltage of the first and second bit lines to a ground voltage;
Set the voltage of the word line to the power supply voltage,
A write current flowing from the power source line of the one CMOS inverter through the P-channel load MOS transistor of the one CMOS inverter, the one N-channel transfer MOS transistor, and the one bit line is measured.

In order to achieve the above object, a semiconductor memory device of the present invention includes:
First and second CMOS inverters, each of which is composed of an N-channel driving MOS transistor and a P-channel load MOS transistor and whose input / output terminals are cross-connected to each other, and first and second CMOS inverters each having a gate terminal connected to a word line. An N-channel transfer MOS transistor, wherein the first CMOS inverter and the first bit line are connected via the first N-channel transfer MOS transistor, and the second CMOS inverter and the first bit line are connected to each other. A semiconductor memory device comprising a memory cell connected to the second bit line via the second N-channel transfer MOS transistor, and wherein the power lines of the first and second CMOS inverters are separated ,
The voltage of the power line of one of the first and second CMOS inverters is set to the power voltage,
The voltage of the power line of the other CMOS inverter of the first and second CMOS inverters is set to the ground voltage,
The voltages of the first and second bit lines are set to a ground voltage;
The voltage of the word line is set to the power supply voltage,
A write current flowing from the power source line of the one CMOS inverter through the load MOS transistor of the one CMOS inverter, the one transfer MOS transistor, and the one bit line is measured.

  According to the present invention, when measuring the write current flowing in the memory cell, the voltages of the power supply lines of the two CMOS inverters constituting the memory cell are independently controlled, and the voltage of the power supply line of one CMOS inverter through which the write current flows. Is set to the power supply voltage, and the voltage of the power supply line of the other CMOS inverter is set to the ground voltage. Then, since the input voltage of one CMOS inverter, that is, the gate voltage of the load MOS transistor constituting the one CMOS inverter is always the ground voltage, this load MOS transistor is turned on.

  If the word line voltage is set to the power supply voltage in this state, the transfer MOS transistor is turned on, and a write path is generated from one CMOS inverter to the bit line, so that the write current to be measured flows stably. Is possible.

  Therefore, the write current flowing in the memory cell can be stably measured, and the cause of fluctuation of the write current is only a defect in the write path of the memory cell. The effect that the defect in can be detected is obtained.

  In addition, there are only two types of supply voltages supplied to the memory cell when measuring the write current, that is, a power supply voltage and a ground voltage, and an effect that no other special supply voltage is required is obtained.

  In addition, the power supply line voltage, word line voltage, and bit line voltage of the memory cell CMOS inverter need only be switched between the power supply voltage and the ground voltage, so there is no need to change the voltage finely and the current measurement time can be shortened. The effect of becoming.

1 is a circuit diagram showing a configuration of an SRAM memory cell according to an embodiment of the present invention. FIG. 2 is a diagram for explaining voltage setting when measuring a write current flowing through a first CMOS inverter in the SRAM memory cell shown in FIG. 1. FIG. 2 is a diagram for explaining voltage setting when measuring a write current flowing through a second CMOS inverter in the SRAM memory cell shown in FIG. 1. FIG. 2 is a circuit diagram showing an overall configuration of an SRAM including the SRAM memory cell shown in FIG. 1. It is a figure explaining the setting of the switch selection signal of each control circuit shown in FIG. It is a figure which shows an example of the circuit structure of a related SRAM memory cell. It is a figure which shows the other example of the circuit structure of a related SRAM memory cell. FIG. 6 is a diagram showing a state in which both power supply lines of two CMOS inverters are set to a power supply voltage in the SRAM memory cell shown in FIG. 5. FIG. 7B is a diagram showing a butterfly plot of the voltage of the data holding node in the SRAM memory cell in the state shown in FIG. 7A.

  EMBODIMENT OF THE INVENTION Below, the form for implementing this invention is demonstrated with reference to drawings.

In the embodiments described below, the case where the semiconductor memory device of the present invention is an SRAM will be described as an example. However, the present invention is not limited to this, and any semiconductor memory device including a memory cell may be used. .
(1) SRAM Memory Cell (1-1) Configuration of SRAM Memory Cell FIG. 1 is a circuit diagram showing a configuration of an SRAM memory cell according to an embodiment of the present invention.

  As shown in FIG. 1, the SRAM memory cell 10 in this embodiment is composed of six general MOS transistors. That is, the SRAM memory cell 10 includes a first CMOS inverter 11 composed of a driving MOS transistor N1 and a load MOS transistor P1, a second CMOS inverter 12 composed of a driving MOS transistor N2 and a load MOS transistor P2, a first CMOS inverter 11 and a second CMOS inverter. 12, transfer MOS transistors N3 and N4 connected to the circuit 12, respectively.

  The driving MOS transistors N1, N2 and the transfer MOS transistors N3, N4 are N channel MOS transistors. Load MOS transistors P1, P2 are P-channel MOS transistors.

  The input / output terminals of the first CMOS inverter 11 and the second CMOS inverter 12 are cross-connected.

  Bit lines BLT and BLB and a word line WL are connected to the SRAM memory cell 10 as signal lines. Among these, the word line WL is connected to the gate terminals of the transfer MOS transistors N3 and N4. The bit line BLT is connected to the first CMOS inverter 11 via the transfer MOS transistor N3, and the bit line BLB is connected to the second CMOS inverter 12 via the transfer MOS transistor N4.

  Further, a ground line GL common to the first CMOS inverter 11 and the second CMOS inverter 12 is connected to the SRAM memory cell 10. The SRAM memory cell 10 includes two power lines separated by the first CMOS inverter 11 and the second CMOS inverter 12, that is, a power line PLT for the first CMOS inverter 11 and a power line PLB for the second CMOS inverter 12. It is connected.

  The 1-bit data held in the SRAM memory cell 10 is defined by the voltages of the data holding nodes ND1 and ND2.

A write current measuring unit 20 is connected to the bit lines BLT and BLB of the SRAM memory cell 10.
(1-2) Voltage Setting of SRAM Memory Cell FIG. 2A is a diagram for explaining voltage setting when the write current flowing through the first CMOS inverter 11 is measured in the SRAM memory cell shown in FIG.

  As shown in FIG. 2A, when measuring the write current flowing through the first CMOS inverter 11, the voltage of the power line PLT of the first CMOS inverter 11 is set to Vdd, and the voltage of the power line PLB of the second CMOS inverter 12 is set to Vss. Then, the voltages of the bit lines BLT and BLB are set to “0” (Vss), and the voltage of the word line WL is set to “1” (Vdd). In this case, the write current to be measured is Iwrite1 indicated by the arrow in FIG. 2A.

  FIG. 2B is a diagram for explaining voltage setting when measuring the write current flowing through the second CMOS inverter 12 in the SRAM memory cell shown in FIG. 1.

As shown in FIG. 2B, when measuring the write current flowing through the second CMOS inverter 12, the voltage of the power line PLT of the first CMOS inverter 11 is set to Vss, and the voltage of the power line PLB of the second CMOS inverter 12 is set to Vdd. Is done. The other voltage settings are the same as in FIG. 2A. The voltages of the bit lines BLT and BLB are set to “0” (Vss), and the voltage of the word line WL is set to “1” (Vdd). In this case, the write current to be measured is Iwrite2 indicated by the arrow in FIG. 2B.
(1-3) Operation of SRAM Memory Cell The operation of the SRAM memory cell shown in FIG. 1 will be described below.

  As shown in FIG. 2A, when measuring the write current Iwrite1 flowing through the first CMOS inverter 11, first, the voltage of the power line PLT of the first CMOS inverter 11 is set to Vdd, and the voltage of the power line PLB of the second CMOS inverter 12 is set. Vss is set, and the voltages of the bit lines BLT and BLB are set to “0” (Vss).

  As described above, the voltage of the power supply line PLB of the second CMOS inverter 12 is set to Vss, so that the voltage of the data holding node ND2 is forcibly set to Vss. As a result, the input voltage of the first CMOS inverter 11 becomes Vss, the drive MOS transistor N1 is turned off, and the load MOS transistor P1 is turned on.

  When the word line WL is set to “1” in this state, the transfer MOS transistor N3 is turned on, and a current through path, that is, a write path from the power supply line PLT to the bit line PLT through the load MOS transistor P1 and the transfer MOS transistor N3. Occurs. Since this write path is steadily generated as long as the above voltage setting is kept constant, the write current Iwrite1 flows stably.

  Similarly, as shown in FIG. 2B, when measuring the write current Iwrite2 flowing through the second CMOS inverter 12, first, the voltage of the power line PLT of the first CMOS inverter 11 is set to Vss, and the power line PLB of the second CMOS inverter 12 is set. Is set to Vdd, and the voltages of the bit lines BLT and BLB are set to “0” (Vss).

  Thus, the voltage of the power supply line PLT of the first CMOS inverter 11 is set to Vss, so that the voltage of the data holding node ND1 is forcibly set to Vss. As a result, the drive MOS transistor N2 of the second CMOS inverter 12 is turned off and the load MOS transistor P2 is turned on.

When the word line WL is set to “1” in this state, the transfer MOS transistor N4 is turned on, and a write path is generated from the power supply line PLB to the bit line BLB through the load MOS transistor P2 and the transfer MOS transistor N4. Therefore, the write current Iwrite2 flows stably.
(2) Write Current Measurement Unit In FIGS. 1, 2A, and 2B, the write current measurement unit 20 is connected to two bit lines (BLT and BLB), but the present invention is not limited to this. . That is, since the write current flows only in one bit line at the time of measurement, the write current measuring unit 20 may be connected to either one of the two bit lines. In addition, since the write current is supplied from the power supply lines PLT and PLB, the write current measuring unit 20 may be connected to at least one of the power supply lines PLT and PLB instead of being connected to the bit lines BLT and BLB. .

In FIG. 1, FIG. 2A, and FIG. 2B, for the sake of simplification, one write current measuring unit 20 is connected to one SRAM memory cell 10, but the present invention is not limited to this. Not. That is, a plurality of SRAM memory cells 10 (m rows × n columns memory cell array arranged in a matrix, where m and n are natural numbers) may be connected to one write current measuring unit 20. That is, the write currents of the plurality of SRAM memory cells 10 may be measured collectively.
(3) SRAM
(3-1) Overall Configuration of SRAM FIG. 3 is a circuit diagram showing the overall configuration of the SRAM including the SRAM memory cell 10 shown in FIG.

  As shown in FIG. 3, the SRAM in the present embodiment includes an SRAM macro 60 including the SRAM memory cell 10 shown in FIG. 1, a first CMOS inverter power supply line voltage control circuit 30, and a second CMOS inverter power supply line voltage control circuit 31. And bit line voltage control circuits 40 and 41.

  The SRAM macro 60 selectively switches the voltage of the word line WL to “0” (Vss) or “1” (Vdd) in addition to the SRAM memory cell 10 and the I / O circuit 61 that inputs and outputs the bit line voltage. A word line (WL) driver 62.

  The first CMOS inverter power supply line voltage control circuit 30 and the second CMOS inverter power supply line voltage control circuit 31 are examples of the first power supply control circuit, and the bit line voltage control circuits 40 and 41 are the second power supply control circuit. The word line driver 62 is an example of a third power supply control circuit.

  Each control circuit 30, 31, 40, 41 is provided with a voltage changeover switch for switching the voltage, supplied with the power supply voltage Vdd and the ground voltage Vss, and supplied with switch selection signals (SEL_PLT, SEL_PLB, SEL_BLT, SEL_BLB). Is done. Then, the voltage is selectively switched to Vdd or Vss by switching the voltage switch according to the value of the switch selection signal. Specifically, when the switch selection signal is “1”, Vdd is selected, and when the switch selection signal is “0”, Vss is selected.

  The bit line voltage control circuits 40 and 41 include an N-channel MOS transistor connected in series with the voltage changeover switch in addition to the voltage changeover switch. A control signal CTRL is supplied to the gate terminal of the N channel MOS transistor. When CTRL is “1”, the N channel MOS transistor is turned on, and when CTRL is “0”, the N channel MOS transistor is cut off.

Furthermore, the Vdd line and the Vss line are connected to the outside of the LSI chip on which the SRAM is mounted via a pad (PAD). The Vdd line is connected to the power supply device 70 outside the LSI chip, and the power supply voltage Vdd is supplied from the power supply device 70. The Vss line is connected to the power supply device with current measurement function 71 outside the LSI chip, and the ground voltage Vss is supplied from the power supply device with current measurement function 71. The write current measuring unit 20 shown in FIGS. 1, 2A, and 2B is incorporated in the power supply device 71 with a current measuring function.
(3-2) Operation of SRAM The operation of the SRAM shown in FIG. 3 will be described below.

  FIG. 4 is a diagram showing the setting of the switch selection signal of each control circuit shown in FIG.

  The operation mode of the SRAM macro 60 includes a write current measurement mode and a normal operation mode.

  In the write current measurement mode, the control signal CTRL is set to “1”, and the bit lines BLT and BLB can be set by the bit line voltage control circuits 40 and 41. Further, the switch selection signals SEL_BLT and SEL_BLB are set to “0”, and the voltages of the bit lines BLT and BLB are set to Vss. Further, the set values of the switch selection signals SEL_PLT and SEL_PLB are changed depending on the type of the write current. When measuring Iwrite1, SEL_PLT is set to “1”, SEL_PLB is set to “0”, the voltage of the power supply line PLT is set to Vdd, the voltage of the power supply line PLB is set to Vss, and the bit line BLT is set. Iwrite1 is measured via On the other hand, when measuring Iwrite2, SEL_PLT is set to “0”, SEL_PLB is set to “1”, the voltage of the power supply line PLT is set to Vss, and the voltage of the power supply line PLB is set to Vdd. Measurement of Iwrite2 is performed via line BLB. Note that the word line driver 62 sets the word line voltage to “1”.

  In the normal operation mode, SEL_PLT and SEL_PLB are both set to “1”, Vdd is supplied to both the first CMOS inverter 11 and the second CMOS inverter 12, and the operation as the SRAM memory cell 10 is compensated. Further, the control signal CTRL is set to “0”, and the bit line voltage setting by the bit line voltage control circuits 40 and 41 is cut off. As a result, an operation as a normal SRAM macro 60 becomes possible.

  In addition, the connection destination of the power supply device 71 with a current measurement function is not limited to the Vss terminal, and may be connected to the Vdd side. In this case, the power supply voltage Vdd is supplied from the power supply device 71 with a current measurement function. On the other hand, the power supply 70 is connected to the Vss terminal, and the ground voltage Vss is supplied from the power supply 70. Thus, the write current flowing through the power supply line PLT or PLB is measured by the power supply device 71 with a current measurement function.

  The present invention can be applied to various tests performed for detecting defects during the manufacture of a semiconductor memory device.

DESCRIPTION OF SYMBOLS 10 SRAM memory cell 11 1st CMOS inverter 12 2nd CMOS inverter 20 Write current measurement part 30 1st CMOS inverter power supply line voltage control circuit 31 2nd CMOS inverter power supply line voltage control circuit 40, 41 Bit line voltage control circuit 60 SRAM macro 61 I / O Circuit 62 Word line driver 70 Power supply 71 Power supply with current measurement function

Claims (7)

First and second CMOS inverters, each of which is composed of an N-channel driving MOS transistor and a P-channel load MOS transistor and whose input / output terminals are cross-connected to each other, and first and second CMOS inverters each having a gate terminal connected to a word line. An N-channel transfer MOS transistor, wherein the first CMOS inverter and the first bit line are connected via the first N-channel transfer MOS transistor, and the second CMOS inverter and the first bit line are connected to each other. A test method for a semiconductor memory device comprising a memory cell connected to the second bit line via the second N-channel transfer MOS transistor, and the power lines of the first and second CMOS inverters are separated Because
A voltage of a power line of one of the first and second CMOS inverters is set to a power voltage;
Setting the voltage of the power line of the other CMOS inverter of the first and second CMOS inverters to a ground voltage;
Setting the voltage of the first and second bit lines to a ground voltage;
Set the voltage of the word line to the power supply voltage,
A test method for measuring a write current flowing from the power line of the one CMOS inverter through the P-channel load MOS transistor of the one CMOS inverter, the one N-channel transfer MOS transistor, and the one bit line . First and second CMOS inverters, each of which is composed of an N-channel driving MOS transistor and a P-channel load MOS transistor and whose input / output terminals are cross-connected to each other, and first and second CMOS inverters having a gate terminal connected to a word line An N-channel transfer MOS transistor, wherein the first CMOS inverter and the first bit line are connected via the first N-channel transfer MOS transistor, and the second CMOS inverter and the first bit line are connected to each other. A semiconductor memory device comprising a memory cell connected to the second bit line via the second N-channel transfer MOS transistor, and wherein the power lines of the first and second CMOS inverters are separated ,
The voltage of the power line of one of the first and second CMOS inverters is set to the power voltage,
The voltage of the power line of the other CMOS inverter of the first and second CMOS inverters is set to the ground voltage,
The voltages of the first and second bit lines are set to a ground voltage;
The voltage of the word line is set to the power supply voltage,
A semiconductor memory device in which a write current flowing from a power source line of the one CMOS inverter through a load MOS transistor of the one CMOS inverter, the one transfer MOS transistor, and the one bit line is measured.   3. The semiconductor memory device according to claim 2, further comprising: a first voltage control circuit that selectively switches a voltage of a power supply line of the first and second CMOS inverters to a power supply voltage or a ground voltage.   4. The semiconductor memory device according to claim 2, further comprising: a second voltage control circuit that selectively switches a voltage of the first and second bit lines to a power supply voltage or a ground voltage. 5.   5. The semiconductor memory device according to claim 2, further comprising a third voltage control circuit that selectively switches a voltage of the word line to a power supply voltage or a ground voltage. 6.   3. A write current measuring unit that connects to at least one of the first and second bit lines, sets the connected bit line to a ground voltage, and measures the write current. 6. The semiconductor memory device according to any one of items 1 to 5.   And a write current measuring unit that is connected to one of the power lines of the first and second CMOS inverters, sets the connected power line to a power supply voltage, and measures the write current. Item 6. The semiconductor memory device according to any one of Items 2 to 5.

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