JP2011008485A - Data processing apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data processing apparatus efficiently transferring data between a plurality of primary caches.SOLUTION: The data processing apparatus 1 includes: a plurality of computing units 11, 21, 31, and 41: the plurality of primary caches 12, 22, 32 and 42; a secondary cache 50; and a plurality of successively and continuously connected buffer caches 13, 23, 33, and 43. Data from the secondary cache 50 are transferred to the buffer cache 13 in the first stage, and the plurality of buffer caches 13, 23, 33, and 43 successively transfer a part of data of those respective buffer caches 13, 23, 33, and 43 to the post stage side, and transfers a part of the data of each buffer cache 13, 23, 33, and 43 to primary caches 12, 22, 32, and 42 corresponding to those respective buffer caches 13, 23, 33, and 43.

Description

  The present invention relates to a cache system suitable for a multiprocessor system in which a plurality of processors are connected and processing by each of the plurality of processors can be performed synchronously. In particular, the present invention relates to a data processing apparatus that processes data by supplying data using this cache system.

  In recent years, the amount of information handled by embedded devices has increased, and the demand for processors with low power consumption and guaranteed minimum performance has increased rapidly. Until now, the guarantee of minimum performance has been generally realized by using dedicated hardware.

  Recently, time and economic costs are required to follow new standards such as image and wireless, which are being developed one after another, and to fine-tune filters for product differentiation and to update functions after shipment. Adopting large dedicated hardware is becoming difficult.

  Meanwhile, the demand for high-resolution image processing used in digital cinema and the like has been increasing in recent years. The amount of calculation of filter processing for correcting high-resolution images such as digital cinema is enormous, and real-time processing by an existing processor is impossible. In addition, a high-performance and flexible architecture that has a performance comparable to that of dedicated hardware that can generate one pixel per cycle on a regular basis and that can execute general-purpose machine language instructions. There is nothing at present.

  In consideration of such a situation, multi-cores and many-cores (for example, see Non-Patent Documents 1 to 3) and reconfigurable data paths (for example, see Non-Patent Document 4) are currently promising. Yes.

  Multi-core and many-core are architectures in which application programs divided into various granularities are executed in parallel by a plurality of cores. These multi-cores and many-cores have the advantage of being able to use common parallel programming techniques.

  In addition, by providing a local memory that can be controlled by software, performance degradation due to an unpredictable cache miss can be suppressed to some extent. For this reason, not only is it excellent in flexibility and expandability, but it is also possible to consider the minimum performance guarantee by increasing the number of cores.

  On the other hand, the reconfigurable data path is an architecture in which a large number of arithmetic units having a smaller granularity than the processor core are arranged to achieve both functional flexibility and high speed. This reconfigurable data path has the advantage that, by arranging a large number of arithmetic units, a performance comparable to that of a high-performance processor can be achieved even at a relatively low operating frequency, as in the case of dedicated hardware.

  By the way, a sparse scalar type or a VLIW (Very Long Instruction Word) type is generally adopted as a processor in any of the above-described multi-core, many-core, and reconfigurable data path architectures.

  In such a processor, the adoption of the cache method greatly contributes to the performance improvement. As the cache system, there is a system in which a primary cache is built in each of a plurality of processors and at the same time a secondary cache is provided between the external main memory. In this method, the hit rate of the secondary cache is increased, access to the main memory is reduced, and the performance of the processor is improved.

Vangal, S. et al .: An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS, ISSCC, pp. 98-99 (2007). Bell, S. et al .: Tile64 Processor: A 64-Core SoC with Mesh Interconnect, ISSCC, pp.88-89 (2008). Kyo, S., Okazaki, S. and Arai, T .: An Integrated Memory Array Processor for Embedded Image Recognition Systems, IEEE Transactions on Computers, Vol.56, No.5, pp.622-634 (2007). Becker, J. and Hubner, M .: Run-time reconfigurabilility and other future trends, the 19th annual symposium on Integrated circuits and systems design, pp. 9-11 (2006).

  In the case of adopting the cache method described above, in order to supply data to a large number of processors at the same time, it is necessary to transfer contents between primary caches provided in each of the plurality of processors.

  However, in any of the above-described architectures, there is a problem that it is difficult to efficiently transfer contents between the plurality of primary caches.

  In view of the above problems, an object of the present invention is to provide a data processing apparatus that can efficiently perform data transfer between a plurality of primary caches.

  In order to achieve the above object, a data processing apparatus according to the present invention includes a plurality of arithmetic units, a plurality of first caches provided in each of the plurality of arithmetic units and transferring data to the corresponding arithmetic units, A second cache that is shared by the plurality of computing units and stores data used for each processing of the plurality of computing units, and a data that is provided in each of the plurality of first caches and that corresponds to the first cache. A plurality of buffer caches, wherein the plurality of buffer caches are connected to the second cache and include a first-stage buffer cache to which data is transferred from the second cache, and the plurality of buffers Each of the caches is sequentially connected sequentially from the first stage buffer cache, and each of the plurality of buffer caches is connected to the second key cache. A part of the data transferred from the cache to the first stage buffer cache is sequentially transferred to the subsequent stage of each buffer cache, and a part of the data stored in each buffer cache is transferred to each buffer cache. Transfer to the corresponding first cache.

  In the above data processing apparatus, each buffer cache sequentially transfers a part of the data transferred from the second cache to the first stage buffer cache to the subsequent stage side of each buffer cache, and stores it in each buffer cache. A part of the stored data is transferred to the first cache corresponding to each buffer cache.

  For this reason, each first cache transfers the data stored in the second cache to the computing unit corresponding to each first cache without transferring the data stored in each first cache to each other. Can be transferred.

  Therefore, it is possible to realize a data processing apparatus that can efficiently transfer data between a plurality of first caches.

  Each of the plurality of buffer caches preferably transfers data necessary for processing of an arithmetic unit corresponding to each buffer cache to a first cache corresponding to each buffer cache.

  In this case, each buffer cache can efficiently transfer data necessary for processing of each arithmetic unit to each arithmetic unit.

  For this reason, unnecessary data transfer between each buffer cache and each arithmetic unit is reduced, so that the power consumption of the data processing apparatus can be reduced.

  Each of the plurality of first caches preferably stops a storage operation of a storage unnecessary area that is unnecessary for storing data transferred from the corresponding buffer cache among the storage areas of each first cache.

  In this case, it is possible to stop the storage operation of a storage area that does not store data among the storage areas of each first cache.

  Therefore, it is possible to reduce the power consumption due to the storage operation of the unnecessary storage area of each first cache, and as a result, the power consumption of the data processing device is reduced.

  Each of the plurality of buffer caches preferably transfers data necessary for processing of an arithmetic unit corresponding to the buffer cache on the subsequent stage of each buffer cache to the buffer cache on the subsequent stage of each buffer cache.

  In this case, each buffer cache can efficiently transfer data necessary for processing of the arithmetic unit corresponding to the buffer cache on the subsequent stage of each buffer cache to the buffer cache on the subsequent stage.

  For this reason, unnecessary data transfer between each buffer cache and another buffer cache is reduced, so that the power consumption of the data processing apparatus can be reduced.

  Each of the plurality of buffer caches preferably stops a storage operation of a storage unnecessary area that is unnecessary for storing data transferred from the preceding buffer cache among the storage areas of each buffer cache.

  In this case, it is possible to stop the storage operation of a storage area that does not store data among the storage areas of each buffer cache.

  For this reason, it is possible to reduce the power consumption due to the storage operation of the unnecessary storage area of each buffer cache, and as a result, the power consumption of the data processing device is reduced.

  The data processing device analyzes a data access pattern based on execution of a program to be processed by itself, processes the program using the analysis result, and data necessary for each processing of the plurality of arithmetic units is: Preferably, the data processing device is specified based on the analysis result of the data access pattern of the program processed by the data processing device.

  In this case, even when the data access pattern of the program processed by the data processing device has not been analyzed in advance, the above effect can be realized.

  Provided in each of the plurality of first caches, a specifying unit for specifying data necessary for each processing of the plurality of arithmetic units based on the analysis result of the data access pattern of the program, Based on the first execution unit for stopping the storage operation of the storage unnecessary area of the corresponding first cache, and each of the plurality of buffer caches, and based on the identification result by the identification unit, It is preferable to further include a second execution unit that stops the storage operation of the storage unnecessary area.

  In this case, it is possible to simply stop the storage operation of the storage area that does not store data among the storage areas of each first cache and stop the storage operation of the storage area that does not store data among the storage areas of each buffer cache. It can be controlled by the device configuration.

  For this reason, the manufacturing cost of a data processor can be reduced.

  The program processed by the data processing apparatus is analyzed in advance for data access patterns, and the data required for each processing of the plurality of computing units is specified in advance based on the analysis contents of the data access patterns of the programs. In each of the plurality of first caches, a storage area of each first cache is set in advance in order to store data necessary for each process of the plurality of arithmetic units. It is preferable that a storage area of each buffer cache is preset in order to transfer data necessary for each process of the plurality of arithmetic units to the corresponding first cache.

  In this case, since the data necessary for the processing of each computing unit can be specified in advance, the storage area required for each first cache and the storage area required for each buffer cache can be set in advance. it can.

  For this reason, the apparatus configuration of the data processing apparatus can be further simplified, and the power consumption can be further reduced.

  As described above, the data processing device of the present invention includes a plurality of arithmetic units, a plurality of first caches that are provided in each of the plurality of arithmetic units and transfer data to the corresponding arithmetic units, and the plurality of arithmetic units. A second cache that stores data used for each process of the plurality of computing units and a plurality of first caches that are provided in each of the plurality of first caches and that transfer data to the corresponding first cache A plurality of buffer caches, wherein the plurality of buffer caches are connected to the second cache and include a first-stage buffer cache to which data is transferred from the second cache, each of the plurality of buffer caches being , Sequentially connected from the first stage buffer cache, and each of the plurality of buffer caches is connected to the second cache from the second cache. A part of the data transferred to the first-stage buffer cache is sequentially transferred to the subsequent stage side of each buffer cache, and a part of the data stored in each buffer cache is transferred to the first corresponding to each buffer cache. Transfer to cache.

  Therefore, there is an effect that data transfer between a plurality of primary caches can be performed efficiently.

It is a block diagram which shows schematic structure of the data processor which concerns on Embodiment 1 of this invention. It is explanatory drawing for demonstrating the program for performing a general blurring process. It is explanatory drawing for demonstrating the procedure of the conventional parallel processing using the program of FIG. 2 (the 1). It is explanatory drawing for demonstrating the procedure of the conventional parallel processing using the program of FIG. 2 (the 2). FIG. 3 is an explanatory diagram for explaining a procedure of conventional parallel processing using the program of FIG. 2 (part 3); FIG. 3 is an explanatory diagram for explaining a procedure of parallel processing according to the first embodiment of the present invention using the program of FIG. 2 (part 1); FIG. 6 is an explanatory diagram for explaining a procedure of parallel processing according to the first embodiment of the present invention using the program of FIG. 2 (part 2); FIG. 6 is an explanatory diagram for explaining a parallel processing procedure according to the first embodiment of the present invention using the program of FIG. 2 (part 3); FIG. 6 is an explanatory diagram for explaining a procedure of parallel processing according to the first embodiment of the present invention using the program of FIG. 2 (part 4); It is a block diagram which shows schematic structure of the data processor which concerns on Embodiment 2 of this invention. It is explanatory drawing for demonstrating the cache system of FIG.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings used for the following description, the same parts are denoted by the same reference numerals. Their names and functions are also the same. Therefore, detailed description thereof will not be repeated.

(Embodiment 1)
FIG. 1 is a block diagram showing a schematic configuration of a data processing apparatus according to Embodiment 1 of the present invention.

  As shown in FIG. 1, the data processing apparatus 1 according to the first embodiment of the present invention includes a first stage computing unit 10, a second stage computing unit 20, a third stage computing unit 30, and a fourth stage computing. Unit 40, a secondary cache (second cache) 50, and a main memory 60.

  The first stage arithmetic unit 10 includes an arithmetic unit 11, a primary cache (first cache) 12, a buffer cache 13, a transfer control unit (specification unit) 14, and a first transfer execution unit (first An execution unit) 15 and a second transfer execution unit (second execution unit) 16. Similarly, the second stage arithmetic unit 20 includes an arithmetic unit 21, a primary cache 22, a buffer cache 23, a transfer control unit 24, a first transfer execution unit 25, and a second transfer execution unit 26. ,have. The third-stage arithmetic unit 30 includes an arithmetic unit 31, a primary cache 32, a buffer cache 33, a transfer control unit 34, a first transfer execution unit 35, and a second transfer execution unit 36. is doing. The fourth-stage arithmetic unit 40 includes an arithmetic unit 41, a primary cache 42, a buffer cache 43, a transfer control unit 44, a first transfer execution unit 45, and a second transfer execution unit 46. is doing.

  The data processing apparatus 1 according to the present embodiment stores a program (instruction) and data processed by itself (hereinafter, the program (instruction) and data may be simply referred to as “data”) for a long time. Main memory 60, secondary cache 50 for storing a part of programs (instructions) and data stored in main memory 60 in the short term, and programs (instructions) and data stored in secondary cache 50 It has a memory system composed of a plurality of primary caches 12, 22, 32, 42 and a plurality of buffer caches 13, 23, 33, 43 for temporarily storing a part.

  The main memory 60 stores programs (instructions) and data used by the first to fourth stage arithmetic units 10, 20, 30 and 40. The main memory 60 stores any programs (instructions) and data that the first to fourth stage arithmetic units 10, 20, 30, and 40 are actually in use and not in use for a long time. For this reason, the main memory 60 emphasizes the storage function rather than the access function, and is required to have a large capacity even at a low speed.

  The main memory 60 can be a known magnetic disk, magneto-optical disk, or magnetic tape.

  Furthermore, the main memory 60 is positioned as a kind of input / output device from the first to fourth stage arithmetic units 10, 20, 30, and 40. Therefore, in the data processing device 1 according to the present embodiment, instead of the main memory 60, an input device that collects programs (commands) and data necessary for the data processing device 1 to perform data processing, and a data processing device An external I / O comprising an output device for enabling the user to use the result of data processing by 1 may be used.

  The secondary cache 50 stores programs (instructions) and data that are actually used by the first to fourth stage arithmetic units 10, 20, 30, and 40. The secondary cache 50 can be directly accessed by the arithmetic units 11, 21, 31, 41 of the first to fourth stage arithmetic units 10, 20, 30, 40. That is, the secondary cache 50 is shared by the computing units 11, 21, 31, and 41.

  For this reason, the secondary cache 50 places more importance on the access function than the storage function for the main memory 60 where the storage function is more important than the access function. The secondary cache 50 is required to have high speed even with a small capacity.

  As the secondary cache 50, a known semiconductor memory such as DRAM or SRAM can be used.

  The primary caches 12, 22, 32, and 42 and the buffer caches 13, 23, 33, and 43 directly transfer data to and from the calculators 11, 21, 31, and 41. The primary caches 12, 22, 32, 42 and the buffer caches 13, 23, 33, 43 are actually used by the respective computing units 11, 21, 31, 41 stored in the secondary cache 50. Are sequentially acquired from the secondary cache 50 and transferred to the computing units 11, 21, 31, 41.

  The buffer cache (first stage buffer cache) 13 of the first stage arithmetic unit 10 is arranged so as to be connected to the secondary cache 50, and performs direct data transfer with the secondary cache 50. The buffer cache 13 of the first stage arithmetic unit 10 has a capacity capable of storing the minimum unit of data exchanged between itself and the secondary cache 50 (hereinafter also referred to as “block”). Data transfer between the buffer cache 13 and the secondary cache 50 of the first stage arithmetic unit 10 is performed in units of blocks.

  On the other hand, the buffer cache 23 of the second stage computing unit 20, the buffer cache 33 of the third stage computing unit 30, and the buffer cache 43 of the fourth stage computing unit 40 perform direct data transfer with the secondary cache 50. Don't do it.

  That is, the buffer caches 13, 23, 33, and 43 have an arrangement configuration in which the buffer cache 13 is the first stage and the buffer caches 13 are sequentially connected sequentially. The buffer caches 13, 23, 33, and 43 can sequentially transfer the data transferred from the secondary cache 50 to the buffer cache 13 to each subsequent stage.

  Specifically, the buffer cache 23 of the second stage arithmetic unit 20 is disposed so as to be connected to the buffer cache 13 of the first stage arithmetic unit 10, and is connected to the buffer cache 13 of the first stage arithmetic unit 10. Direct data transfer is performed at. The buffer cache 33 of the third stage arithmetic unit 30 is arranged so as to be connected to the buffer cache 23 of the second stage arithmetic unit 20, and direct data transfer with the buffer cache 23 of the second stage arithmetic unit 20 To do. The buffer cache 43 of the fourth stage arithmetic unit 40 is arranged so as to be connected to the buffer cache 33 of the third stage arithmetic unit 30, and is directly connected to the buffer cache 33 of the third stage arithmetic unit 30. Perform data transfer. Any of the above data transfers is performed in units of the blocks.

  When one block of data is transferred from the secondary cache 50 to the buffer cache 13 of the first stage arithmetic unit 10, the data stored immediately before the data transfer is performed is stored in the buffer cache 13 of the first stage arithmetic unit 10. Transfer to next cache 12. The primary cache 12 updates the data of several blocks stored by itself every time the data for each block is transferred from the buffer cache 13.

  The buffer cache 13 transfers the same data as the data transferred to the primary cache 12 to the buffer cache 23 of the second stage arithmetic unit 20 in accordance with the data transfer to the primary cache 12.

  In the data transfer from the buffer cache 13 to the primary cache 12 and the data transfer from the buffer cache 13 to the buffer cache 23 of the second stage arithmetic unit 20, all of one block stored in the buffer cache 13 is stored. Data is not subject to data transfer. Only the data requested by the primary cache 12 and the buffer cache 23 that receive the data transfer may be transferred.

  When one block of data is transferred from the buffer cache 13 of the first stage arithmetic unit 10, the buffer cache 23 of the second stage arithmetic unit 20 stores the data stored immediately before the data transfer is performed for the second time. Transfer to the primary cache 22 of the stage operation unit 20. The primary cache 22 updates several blocks of data stored by itself every time the data for each block is transferred from the buffer cache 23.

  In the data transfer from the buffer cache 23 to the primary cache 22 and the data transfer from the buffer cache 23 to the buffer cache 33 of the third stage arithmetic unit 30, all of one block stored in the buffer cache 23 is stored. Data is not subject to data transfer. Only the data requested by the primary cache 22 and the buffer cache 33 that receive data transfer may be transferred.

  When one block of data is transferred from the buffer cache 23 of the second stage arithmetic unit 20, the buffer cache 33 of the third stage arithmetic unit 30 stores the data stored immediately before the data transfer is performed in the third state. Transfer to the primary cache 32 of the stage operation unit 30. The primary cache 32 updates several blocks of data stored by itself every time data of each block is transferred from the buffer cache 33.

  In the data transfer from the buffer cache 33 to the primary cache 32 and the data transfer from the buffer cache 33 to the buffer cache 43 of the fourth stage arithmetic unit 40, all of one block stored in the buffer cache 33 is stored. Data is not subject to data transfer. Only the data requested by the primary cache 32 and the buffer cache 43 that receive data transfer may be transferred.

  When one block of data is transferred from the buffer cache 33 of the third-stage arithmetic unit 30 to the buffer cache 43 of the fourth-stage arithmetic unit 40, the data stored until immediately before the data transfer is transferred to the fourth state. The data is transferred to the primary cache 42 of the stage calculation unit 40. The primary cache 42 updates several blocks of data stored therein each time the data for each block is transferred from the buffer cache 43.

  In the data transfer from the buffer cache 43 to the primary cache 42, not all the data of one block stored in the buffer cache 43 is a target for data transfer. Only the data requested by the primary cache 42 that receives the data transfer may be transferred.

  The primary caches 12, 22, 32, and 42 and the buffer caches 13, 23, 33, and 43 all use a high-speed SRAM such as a well-known ECL / BiCMOS SRAM or ECL, which is a high-speed semiconductor memory with a low capacity. Can be realized.

  The transfer control unit 14 of the first stage calculation unit 10 controls each data transfer execution process of the first transfer execution unit 15 and the second transfer execution unit 16. The first transfer execution unit 15 executes data transfer between the buffer cache 13 and the primary cache 12 in accordance with the control content from the transfer control unit 14. The second transfer execution unit 16 executes data transfer between the buffer cache 13 and the buffer cache 23 according to the control content from the transfer control unit 14.

  The transfer control unit 24 of the second stage calculation unit 20 controls each data transfer execution process of the first transfer execution unit 25 and the second transfer execution unit 26. The first transfer execution unit 25 executes data transfer between the buffer cache 23 and the primary cache 22 in accordance with the control content from the transfer control unit 24. The second transfer execution unit 26 executes data transfer between the buffer cache 23 and the buffer cache 33 in accordance with the control content from the transfer control unit 24.

  The transfer control unit 34 of the third stage arithmetic unit 30 controls each data transfer execution process of the first transfer execution unit 35 and the second transfer execution unit 36. The first transfer execution unit 35 executes data transfer between the buffer cache 33 and the primary cache 32 in accordance with the control content from the transfer control unit 34. The second transfer execution unit 36 executes data transfer between the buffer cache 33 and the buffer cache 43 in accordance with the control content from the transfer control unit 34.

  The transfer control unit 44 of the fourth stage calculation unit 40 controls each data transfer execution process of the first transfer execution unit 45 and the second transfer execution unit 46. The first transfer execution unit 45 executes data transfer between the buffer cache 43 and the primary cache 42 according to the control content from the transfer control unit 44. The second transfer execution unit 46 executes data transfer between the buffer cache 43 and a subsequent buffer cache (not shown) according to the control content from the transfer control unit 44.

  Next, the cache method of the data processing apparatus 1 according to the present embodiment will be described. Hereinafter, the cache method of the data processing device 1 will be described using an example of performing blurring processing from 3 × 3 pixels. FIG. 2 shows a program for performing this blurring process.

  The program (instruction) 2 in FIG. 2 is a program (instruction) for executing the blurring process on the 3 × 3 pixels to be subjected to the blurring process using the upper, lower, left, and right pixels of the center pixel. When blurring processing is performed from 3 × 3 pixels as described above, it is common to use the pixel values of all nine pixels constituting the 3 × 3 pixels. Here, in order to facilitate the description of the cache method of the data processing apparatus 1, a blurring process using four pixels, top, bottom, left, and right as described above is taken as an example. Of course, it goes without saying that the present invention can also be applied to blurring processing using the pixel values of all nine pixels constituting a 3 × 3 pixel.

  In general, in image processing, there are many processes in which calculation is performed for each row while a target pixel group is gradually shifted in a certain direction. For this reason, the data required for the next process can be predicted. In the blurring process using the program (instruction) 2 described above, the blurring process is repeated for 3 × 3 pixels. For example, if the target pixel group moves, for example, by one pixel in the horizontal direction, two vertical rows can be reused, and only one vertical row is required. is there.

  Therefore, in the cache system of the data processing apparatus 1, the buffer cache 13 of the first stage arithmetic unit 10 stores 2 pieces of data for one line in the vertical direction newly required by the arithmetic unit 11 of the first stage arithmetic unit 10. Supplied from the next cache 50.

  Data for one line in the vertical direction newly required by the computing unit 21 of the second stage computing unit 20 is supplied from the buffer cache 13 of the first stage computing unit 10 to the buffer cache 23 of the second stage computing unit 20. The

  Data for one line in the vertical direction newly required by the computing unit 31 of the third stage computing unit 30 is supplied from the buffer cache 23 of the second stage computing unit 20 to the buffer cache 33 of the third stage computing unit 30. The

  Data for one line in the vertical direction newly required by the computing unit 41 of the fourth stage computing unit 40 is supplied from the buffer cache 33 of the third stage computing unit 30 to the buffer cache 43 of the fourth stage computing unit 40. The

  As a result of such data transfer, for example, the buffer cache 23 of the second stage arithmetic unit 20 stores data one generation before the buffer cache 13 of the first stage arithmetic unit 10, and the third stage arithmetic unit 30 The buffer cache 33 stores data one generation before the buffer cache 23 of the second stage arithmetic unit 20.

  Here, it is not realistic that each of the first to fourth stage arithmetic units 10, 20, 30, and 40 of the data processing device 1 directly refers to the contents of the secondary cache 50. This is because the number of ports required for the secondary cache 50 is significantly increased.

  Therefore, in the data processing device 1, each of the first to fourth stage arithmetic units 10, 20, 30, and 40 does not directly refer to the contents of the secondary cache 50, and the first to fourth stage arithmetic units 10, 20, 30, A configuration in which the primary caches 12, 22, 32, and 42 and the buffer caches 13, 23, 33, and 43 corresponding to the respective 40 are directly referred to is employed.

  As described above, in the data processing device 1, each of the first to fourth stage arithmetic units 10, 20, 30, and 40 uses the program (instruction) 2, and the first to fourth stage arithmetic units 10, 20, 30, and 40 Each computing unit 11, 21, 31, 41 performs blurring processing in parallel. Then, the data processing apparatus 1 executes the blurring process for one entire screen using the processing results of the first to fourth stage arithmetic units 10, 20, 30, and 40.

  Next, the operation of the cache method of the data processing apparatus 1 will be described.

  First, with reference to FIG. 3, the processing procedure expected when the conventional method is used for the parallel processing of the program (instruction) 2 in FIG. 2 will be described. In FIG. 3, it is assumed that each of the four arithmetic units 11a, 21a, 31a, and 41a has primary caches 12a, 22a, 32a, and 42a.

  In this case, the computing unit 11a executes processing using data of pixels located above the center pixel in the same 3 × 3 pixel group A. The computing unit 21a executes processing using data of a pixel located below the center pixel. The computing unit 31a executes processing using data of a pixel located on the right side of the central pixel. The computing unit 41a executes processing using data of a pixel located on the left side of the central pixel.

  More specifically, as shown in FIG. 4, at time t = 1, data supplied from the outside is stored in the primary cache 12a. Then, using the data stored in the primary cache 12a, the computing unit 11a executes processing using data of pixels located above the center pixel in the same 3 × 3 pixel group A.

  Next, at time t = 2, using the data stored in the primary cache 22a, the computing unit 21a executes processing using data of a pixel located below the central pixel. At this time, in principle, all of the data stored in the primary cache 12a needs to be transferred to the primary cache 22a.

  Similarly, at time t = 3, using the data stored in the primary cache 32a, the arithmetic unit 31a executes processing using data of a pixel located on the right side of the central pixel. Also at this time, in principle, all of the data stored in the primary cache 22a needs to be transferred to the primary cache 32a.

  Further, similarly, at time t = 4, using the data stored in the primary cache 42a, the computing unit 41a executes processing using the data of the pixel located on the left side of the central pixel. Also at this time, in principle, all of the data stored in the primary cache 32a needs to be transferred to the primary cache 42a.

  Here, the state of each process of the computing units 11a, 21a, and 31a at the time t = 4 will be described.

  As shown in FIG. 5, the processing target of the computing unit 31a is a 3 × 3 pixel group B obtained by shifting the 3 × 3 pixel group A, which is the processing target of the computing unit 41a, by one pixel in the horizontal direction.

  The processing target of the computing unit 31a is a 3 × 3 pixel group B obtained by shifting the 3 × 3 pixel group A, which is the processing target of the computing unit 41a, by one pixel in the horizontal direction.

  Similarly, the processing target of the computing unit 21a is a 3 × 3 pixel group C obtained by shifting the 3 × 3 pixel group A, which is the processing target of the computing unit 41a, by two pixels in the horizontal direction. In other words, the processing target of the computing unit 21a is a 3 × 3 pixel group C obtained by shifting the 3 × 3 pixel group B, which is the processing target of the computing unit 31a, by one pixel in the horizontal direction.

  Similarly, the processing target of the computing unit 11a is a 3 × 3 pixel group D obtained by shifting the 3 × 3 pixel group A, which is the processing target of the computing unit 41a, by three pixels in the horizontal direction. In other words, the processing target of the computing unit 11a is a 3 × 3 pixel group D obtained by shifting the 3 × 3 pixel group C, which is the processing target of the computing unit 21a, by one pixel in the horizontal direction.

  As can be seen from this, the data updated every cycle in the primary cache 12a is only the data sent from the secondary cache 50a. Therefore, in practice, it is not necessary to transfer all of the data stored in the primary cache 12a to the primary cache 22a. That is, the primary cache 12a may transfer only the data sent from the secondary cache 50a to the primary cache 22a.

  This also applies to data transfer from the primary cache 22a to the primary cache 32a and data transfer from the primary cache 32a to the primary cache 42a.

  Therefore, in the data processing apparatus 1 according to the present embodiment, as shown in FIG. 6, the primary cache 12 and the buffer cache 13 serve as the original primary cache for the computing unit 11. Similarly, the primary cache 22 and the buffer cache 23 serve as the original primary cache for the computing unit 21, and the primary cache 32 and the buffer cache 33 serve as the original primary cache for the computing unit 31. The primary cache 42 and the buffer cache 43 each have a role as an original primary cache for the computing unit 41.

  As shown in FIG. 1, data transfer from the first stage arithmetic unit 10 to the second stage arithmetic unit 20 is executed between the buffer cache 13 and the buffer cache 23. Similarly, the data transfer from the second stage computing unit 20 to the third stage computing unit 30 is executed between the buffer cache 23 and the buffer cache 33, and the data is transferred from the third stage computing unit 30 to the fourth stage computing unit 40. Data transfer is executed between the buffer cache 33 and the buffer cache 43.

  Specifically, as shown in FIG. 6, for example, pixel data “17, 27, 37” for one line in the vertical direction in 3 × 3 pixels is transferred from the secondary cache 50 to the first stage arithmetic unit 10. When sent to the buffer cache 13, the pixel data “16, 26, 36” of one line in the vertical direction stored in the buffer cache 13 until then is transferred to the primary cache 12 of the first stage arithmetic unit 10. And transferred to the buffer cache 23 of the second stage arithmetic unit 20.

  Similarly, when pixel data “16, 26, 36” for one line in the vertical direction is sent from the buffer cache 13 of the first stage arithmetic unit 10 to the buffer cache 23 of the second stage arithmetic unit 20, the buffer up to that point The pixel data “15, 25, 35” for one line in the vertical direction stored in the cache 23 is transferred to the primary cache 22 of the second stage arithmetic unit 20 and the buffer cache of the third stage arithmetic unit 30 33.

  Further, when pixel data “15, 25, 35” for one line in the vertical direction is sent from the buffer cache 23 of the second stage arithmetic unit 20 to the buffer cache 33 of the third stage arithmetic unit 30, the buffer cache up to that point The pixel data “14, 24, 34” for one line in the vertical direction stored in 33 is transferred to the primary cache 32 of the third stage arithmetic unit 30 and the buffer cache 43 of the fourth stage arithmetic unit 40. Forwarded to

  Further, when pixel data “14, 24, 34” for one line in the vertical direction is sent from the buffer cache 33 of the third stage arithmetic unit 30 to the buffer cache 43 of the fourth stage arithmetic unit 40, the buffer cache up to that point The pixel data “13, 23, 33” for one line in the vertical direction stored in 43 is transferred to the primary cache 42 of the fourth-stage arithmetic unit 40 and, for example, in a subsequent arithmetic unit (not shown). It is transferred to a buffer cache (not shown).

  Next, a characteristic part of the operation of the cache method of the data processing apparatus 1 according to the embodiment of the present invention will be described.

  As described above, in the data processing apparatus 1, each of the first to fourth stage arithmetic units 10, 20, 30, and 40 includes the transfer control units 14, 24, 34, 44, and the first transfer execution units 15, 25, 35. , 45 and second transfer execution units 16, 26, 36, 46. In the data processing device 1, the buffer caches 13, 23, 33, 43 and the primary are transferred by the operations of the transfer control units 14, 24, 34, 44 and the first transfer execution units 15, 25, 35, 45. Controls data transfer to and from the caches 12, 22, 32, and 42. The data transfer between the buffer caches 13, 23, 33, and 43 is controlled by the operations of the transfer control units 14, 24, 34, and 44 and the second transfer execution units 16, 26, 36, and 46, respectively.

  Hereinafter, this operation will be described in detail using three examples.

Example 1
In the first embodiment, data transfer between the buffer caches 13, 23, 33, and 43 and the primary caches 12, 22, 32, and 42 is controlled.

  In FIG. 7, the computing unit 11 executes processing using data of pixels located above the center pixel in the same 3 × 3 pixel group. The computing unit 21 executes processing using data of a pixel located below the center pixel. The computing unit 31 executes processing using data of a pixel located on the right side of the central pixel. The computing unit 41 executes processing using data of a pixel located on the left side of the central pixel.

  In this case, in the first stage arithmetic unit 10, among the data to be stored in the primary cache 12, the data required by the arithmetic unit 11 is the pixel data “12, 13, 14 for one line in the horizontal direction. , 15, 16, 17 ". On the other hand, the other pixel data “22, 23, 24, 25, 26, 27, 32, 33, 34, 35, 36, 37” shown in FIG.

  For this reason, the transfer control unit 14 stores, in the primary cache 12, only the data of the pixels located above the center pixel in the 3 × 3 pixel group among the pixel data for one block sent from the buffer cache 13. As a result, the first transfer execution unit 15 is controlled.

  The first transfer execution unit 15 stops the storage operation of unnecessary storage areas (storage unnecessary areas) among all the storage areas of the primary cache 12 according to the control contents from the transfer control unit 14.

  By doing so, only the data required by the computing unit 11 among the pixel data for one block sent from the buffer cache 13 is stored in the primary cache 12.

  Similarly, in the second stage arithmetic unit 20, the data required by the arithmetic unit 21 among the data to be stored in the primary cache 22 is the pixel data “32, 33, 34 for one line in the horizontal direction. , 35, 36 ”. On the other hand, the other pixel data “12, 13, 14, 15, 16, 22, 23, 24, 25, 26” shown in FIG.

  For this reason, the transfer control unit 24 transfers only the data of the pixel located below the center pixel in the 3 × 3 pixel group to the primary cache 22 among the pixel data for one block sent from the buffer cache 23. The first transfer execution unit 25 is controlled so as to be stored.

  The first transfer execution unit 25 stops the storage operation of unnecessary storage areas (storage unnecessary areas) among all the storage areas of the primary cache 22 according to the control content from the transfer control unit 24.

  By doing so, only the data required by the calculator 21 is stored in the primary cache 22 among the pixel data for one block sent from the buffer cache 23.

  Further, in the third-stage arithmetic unit 30, among the data to be stored in the primary cache 32, the data required by the arithmetic unit 31 is the pixel data “22, 23, 24, 25 ". On the other hand, the other pixel data “12, 13, 14, 15, 32, 33, 34, 35” shown in FIG.

  For this reason, the transfer control unit 34 stores, in the primary cache 32, only the data of the pixel located on the right side of the central pixel in the 3 × 3 pixel group among the pixel data for one block sent from the buffer cache 33. As a result, the first transfer execution unit 35 is controlled.

  The first transfer execution unit 35 stops the storage operation of unnecessary storage areas (storage unnecessary areas) among all the storage areas of the primary cache 32 in accordance with the control content from the transfer control unit 34.

  By doing so, only the data required by the calculator 31 is stored in the primary cache 32 among the pixel data for one block sent from the buffer cache 33.

  Further, in the fourth-stage arithmetic unit 40, among the data to be stored in the primary cache 42, the data required by the arithmetic unit 41 is the pixel data “22, 23, 24” for one line in the horizontal direction. It is. On the other hand, the other pixel data “12, 13, 14, 32, 33, 34” shown in FIG.

  For this reason, the transfer control unit 44 stores, in the primary cache 42, only the data of the pixel located on the left side of the central pixel in the 3 × 3 pixel group among the pixel data for one block sent from the buffer cache 43. As a result, the first transfer execution unit 45 is controlled.

  The first transfer execution unit 45 stops the storage operation of unnecessary storage areas (storage unnecessary areas) among all the storage areas of the primary cache 42 according to the control content from the transfer control unit 44.

  By doing so, only the data necessary for the computing unit 41 among the pixel data for one block sent from the buffer cache 43 is stored in the primary cache 42.

  In this manner, the storage operation of unnecessary storage areas in each of the primary caches 12, 22, 32, and 42 can be stopped. For this reason, the power consumption of each of the primary caches 12, 22, 32, and 42 can be greatly reduced as compared with the case where all the storage areas are operated.

  In addition, the data transfer amount itself between the buffer caches 13, 23, 33, 43 and the primary caches 12, 22, 32, 42 can be reduced, and as a result, the power consumption required for each data transfer can be reduced. Can do.

  Therefore, according to the first embodiment, the power consumption of the data processing apparatus 1 can be greatly reduced.

(Example 2)
The second embodiment is another embodiment for controlling data transfer between the buffer caches 13, 23, 33, and 43 and the primary caches 12, 22, 32, and 42.

  In the second embodiment, as shown in FIG. 8, the storage area for stopping the storage operation in each of the primary caches 12, 22, 32, and 42 in the first embodiment is further increased.

  In the second embodiment, in FIG. 8, as in the first embodiment, the computing unit 11 executes processing using data of pixels located above the center pixel in the same 3 × 3 pixel group. . The computing unit 21 executes processing using data of a pixel located below the center pixel. The computing unit 31 executes processing using data of a pixel located on the right side of the central pixel. The computing unit 41 executes processing using data of a pixel located on the left side of the central pixel.

  Here, the second embodiment is different from the first embodiment in that, for example, in the case of the first stage arithmetic unit 10, the data actually used by the arithmetic unit 11 is the pixel data “16” in the primary cache 12. It is a point focused on.

  In this case, unlike the first embodiment, the first-stage arithmetic unit 10 only needs to store the pixel data “16” shown in FIG.

  For this reason, the transfer control unit 14 stores, in the primary cache 12, only the data of the pixels located above the center pixel in the 3 × 3 pixel group among the pixel data for one block sent from the buffer cache 13. As a result, the first transfer execution unit 15 is controlled.

  Furthermore, the transfer control unit 14 controls the first transfer execution unit 15 so that data sequentially sent from the buffer cache 13 is stored in the primary cache 12 only immediately after the data is sent.

  The first transfer execution unit 15 stops the storage operation of unnecessary storage areas (storage unnecessary areas) among all the storage areas of the primary cache 12 according to the control contents from the transfer control unit 14.

  By doing so, only the data actually used by the computing unit 11 among the pixel data for one block sent from the buffer cache 13 is stored in the primary cache 12.

  Similarly, in the case of the second stage arithmetic unit 20, the data actually used by the arithmetic unit 21 is limited to the pixel data “35” in the primary cache 22.

  In this case, unlike the first embodiment, only the pixel data “35” shown in FIG.

  For this reason, the transfer control unit 24 transfers only the data of the pixel located below the center pixel in the 3 × 3 pixel group to the primary cache 22 among the pixel data for one block sent from the buffer cache 23. The first transfer execution unit 25 is controlled so as to be stored.

  Furthermore, the transfer control unit 24 controls the first transfer execution unit 25 so that data sequentially sent from the buffer cache 23 is stored in the primary cache 22 only immediately after the data is sent.

  The first transfer execution unit 25 stops the storage operation of unnecessary storage areas (storage unnecessary areas) among all the storage areas of the primary cache 22 according to the control content from the transfer control unit 24.

  By doing so, only the data actually used by the computing unit 21 among the pixel data for one block sent from the buffer cache 23 is stored in the primary cache 22.

  In the third stage arithmetic unit 30, the data actually used by the arithmetic unit 31 is limited to the pixel data “25” in the buffer cache 33.

  In this case, unlike the first embodiment, the third-stage arithmetic unit 30 does not need to store pixel data in the primary cache 22.

  Therefore, the transfer control unit 34 controls the first transfer execution unit 35 so that the pixel data for one block sent from the buffer cache 33 is not stored in the primary cache 32.

  The first transfer execution unit 35 performs a storage operation (unnecessary storage area) of all the storage areas of the primary cache 32, that is, the storage operation of all the storage areas, according to the control content from the transfer control unit 34. Stop.

  None of the pixel data for one block sent from the buffer cache 33 is stored in the primary cache 32.

  In the case of the fourth stage computing unit 40, the data actually used by the computing unit 41 is limited to the pixel data “22” in the primary cache.

  In this case, unlike the first embodiment, only the pixel data “22, 23” shown in FIG.

  For this reason, the transfer control unit 44 stores, in the primary cache 42, only the data of the pixel located on the left side of the central pixel in the 3 × 3 pixel group among the pixel data for one block sent from the buffer cache 43. As a result, the first transfer execution unit 45 is controlled.

  Further, the transfer control unit 44 executes the first transfer so that the data sequentially sent from the buffer cache 43 is stored in the primary cache 42 from immediately after the data is sent until it is located on the left side of the central pixel. The unit 45 is controlled.

  The first transfer execution unit 45 stops the storage operation of unnecessary storage areas (storage unnecessary areas) among all the storage areas of the primary cache 42 according to the control content from the transfer control unit 44.

  By doing so, only the data actually used by the computing unit 41 among the pixel data for one block sent from the buffer cache 43 is stored in the primary cache 42.

  In this manner, the storage operation of unnecessary storage areas in each of the primary caches 12, 22, 32, and 42 can be stopped. For this reason, the power consumption of each of the primary caches 12, 22, 32, and 42 can be greatly reduced as compared with the case where all the storage areas are operated.

  In addition, the data transfer amount itself between the buffer caches 13, 23, 33, 43 and the primary caches 12, 22, 32, 42 can be reduced, and as a result, the power consumption required for each data transfer can be reduced. Can do.

  Therefore, according to the second embodiment, the power consumption of the data processing apparatus 1 can be significantly reduced.

(Example 3)
In the third embodiment, unlike the first and second embodiments, data transfer between the buffer caches 13, 23, 33, and 43 is controlled.

  In FIG. 9, the arithmetic unit 11 executes processing using data of pixels located above the center pixel in the same 3 × 3 pixel group. The computing unit 21 executes processing using data of a pixel located below the center pixel. The computing unit 31 executes processing using data of a pixel located on the right side of the central pixel. The computing unit 41 executes processing using data of a pixel located on the left side of the central pixel.

  Therefore, in the data transfer from the buffer cache 13 to the buffer cache 23, the data “17” of the pixel located above the center pixel in the 3 × 3 pixel group required by the arithmetic unit 11 is stored in the buffer cache 23. There is no need to transfer to. In other words, the data “27, 37” of the pixels located on the lower side and the left and right sides of the central pixel required by the arithmetic units 21, 31, 41 must be transferred.

  Therefore, the transfer control unit 14 sets the data excluding the data of the pixel located above the center pixel in the 3 × 3 pixel group as the data sent from the buffer cache 13 to the buffer cache 23. 2 transfer execution unit 16 is controlled.

  The second transfer execution unit 16 sets data that the buffer cache 13 should send to the buffer cache 23 among the data for one block sent to the buffer cache 13 in accordance with the control contents from the transfer control unit 14.

  By doing so, only the data required by the calculators 21, 31, 41 among the pixel data for one block sent to the buffer cache 13 is transferred to the buffer cache 23.

  Similarly, in the data transfer from the buffer cache 23 to the buffer cache 33, the data “36” of the pixel located below the center pixel in the 3 × 3 pixel group required by the arithmetic unit 21 is buffered. There is no need to transfer to the cache 33. In other words, the data “26” of the pixels located on the left and right sides of the central pixel required by the calculators 31 and 41 must be transferred.

  For this reason, the transfer control unit 24 sets data excluding data of pixels located above and below the center pixel in the 3 × 3 pixel group as data sent from the buffer cache 23 to the buffer cache 33. The second transfer execution unit 26 is controlled.

  The second transfer execution unit 26 sets data that the buffer cache 23 should send to the buffer cache 33 among the data sent to the buffer cache 23 according to the control content from the transfer control unit 24.

  By doing so, only the data required by the calculators 31 and 41 among the pixel data sent to the buffer cache 23 is transferred to the buffer cache 33.

  Further, in the data transfer from the buffer cache 33 to the buffer cache 43, the data “25” of the pixel located on the left side of the central pixel required by the arithmetic unit 41 must be transferred.

  For this reason, the transfer control unit 34 performs the second transfer so that the data of the pixel located on the left side of the center pixel in the 3 × 3 pixel group is set as the data sent from the buffer cache 33 to the buffer cache 43. The execution unit 36 is controlled.

  The second transfer execution unit 36 sets data to be sent to the buffer cache 43 by the buffer cache 33 among the data sent to the buffer cache 33 in accordance with the control contents from the transfer control unit 34.

  By doing so, only the data required by the arithmetic unit 41 among the pixel data sent to the buffer cache 33 is transferred to the buffer cache 43.

  In this way, the data transfer amount between the buffer caches 13, 23, 33, 43 can be reduced, and as a result, the power consumption required for each data transfer can be reduced.

  Therefore, according to the third embodiment, the power consumption of the data processing apparatus 1 can be greatly reduced.

  In the first to third embodiments, as described above, in each of the first to fourth stage arithmetic units 10, 20, 30, and 40, the transfer control units 14, 24, 34, and 44 and the first transfer execution are performed. Data transfer between the buffer caches 13, 23, 33, 43 and the primary caches 12, 22, 32, 42 is controlled by the operations of the units 15, 25, 35, 45. The data transfer between the buffer caches 13, 23, 33, and 43 is controlled by the operations of the transfer control units 14, 24, 34, and 44 and the second transfer execution units 16, 26, 36, and 46, respectively.

  Here, the control of each operation of the first transfer execution units 15, 25, 35, 45 and the second transfer execution units 16, 26, 36, 46 by the transfer control units 14, 24, 34, 44 is as follows: For example, the program (instruction) processed by the data processing apparatus 1 may be executed based on the result of data access pattern analysis used when performing known automatic parallelization. Here, this data access pattern analysis means analyzing the regularity of data access based on the program execution.

  In general, when processing of one program is to be performed in parallel, the tasks for parallelization are divided into program tasks, parallelism detection and instruction based on analysis of data access patterns between tasks, each task Need to be arranged in the processor and to insert a data communication code and a synchronization code between the processors.

  Of these operations, analysis of the data access pattern is automatically executed by the data processing device 1, for example. Analysis of a data access pattern of a programmed program is executed without being conscious of parallelism, and processing of the program is executed by the data processing apparatus 1 using the analysis result.

  The transfer control units 14, 24, 34, 44 detect the processing contents of each of the computing units 11, 21, 31, 41 by referring to the result of the program analysis after analyzing the program. Then, the transfer control units 14, 24, 34, and 44 specify data to be stored in each of the primary caches 12, 22, 32, and 42 and the buffer caches 13, 23, 33, and 43 using the detection results. To do.

  The transfer control units 14, 24, 34, 44 control the operations of the first transfer execution units 15, 25, 35, 45 and the second transfer execution units 16, 26, 36, 46 according to the identification result. To do.

  On the other hand, the above-described work for analyzing the access pattern may be executed in advance when a programmer performs programming. That is, this is a case where the programmer explicitly describes the access pattern by a description method defined for the data processing apparatus 1, for example. In other words, the data access pattern of the program processed by the data processing device 1 is analyzed in advance.

  In this case, since the analysis contents of the access pattern of the program can be acquired in advance, the storage areas of the primary caches 12, 22, 32, and 42 and the buffer caches 13, 23, 33, and 43 are based on the analysis contents. It can be reduced in advance.

  Furthermore, the transfer control units 14, 24, 34, 44, the first transfer execution units 15, 25, 35, 45, and the second transfer execution units 16, 26, 36, 46 are not necessary.

  For this reason, the apparatus configuration of the data processing apparatus 1 can be simplified and the power consumption can be further reduced.

  For the parallelization of the program including the analysis of the data access pattern described above, for example, Hiroki Honda, “System Software for Parallel Processing—3. Automatic Parallelizing Compiler”, Information Processing, Vol. 34, No. 9, pp. 1150-1157.

(Embodiment 2)
Next, a second embodiment of the present invention will be described. The second embodiment of the present invention is an embodiment according to a specific configuration of the data processing apparatus 1 according to the first embodiment.

  In the data processing apparatus according to the present embodiment, n VLIW processors that can execute known VLIW instructions are arranged in series, and a linear array that connects a register file, an arithmetic unit, and a cache to each of the n VLIW processors. Pipeline Processor.

  The data processing apparatus according to the present embodiment has two operation states, that is, a normal operation state (non-array operation state) and an array operation state. In normal operation, only the first stage operates so that the existing program assets can be used, and operates in the same manner as the existing VLIW processor. Therefore, the first-stage register includes feedback from the first-stage arithmetic unit and the LD / ST unit.

  On the other hand, during the array operation, the VLIW instruction is mapped to the entire n stages, and the same instruction sequence is repeatedly executed until the end condition is satisfied.

  In this way, a maximum of n times parallel processing can be executed as compared with a single arithmetic unit.

  FIG. 10 is a block diagram showing a schematic configuration of the data processing apparatus according to Embodiment 2 of the present invention.

As shown in FIG. 10, the data processing device 3 according to the present embodiment includes an instruction fetch unit 70, an instruction decode unit 80, reg (register file units) _{1 to} reg _n , and arithmetic units ₁ to _n. LD / ST (load / store unit) _{1 to} LD / ST _n , primary cache ₁ to primary cache _n , buffer cache ₁ to buffer cache _n , secondary cache 50, main memory 60, It has.

The instruction fetch unit 70 fetches a necessary instruction from an instruction memory unit (not shown), and the instruction decoding unit 80 decodes the fetched instruction. Based on the decoding result by the instruction decoding unit 80, the processing contents in the arithmetic units ₁ to _n are determined.

  This data processing apparatus 3 is premised on a known VLIW processor architecture. For example, four instructions having a width of 32 bits, for example, are simultaneously fetched by the instruction fetch unit 70, and the instructions fetched by the instruction decoding unit 80 are simultaneously fetched. Assume that it is decoded.

In the data processing device 3, the first stage arithmetic unit includes reg ₁ , arithmetic unit ₁ , LD / ST ₁ , primary cache _1, and buffer cache ₁ . The first-stage arithmetic unit also includes the transfer control unit, the first transfer execution unit, and the second transfer execution unit of the first embodiment. In order to make the drawing easier to see, FIG. 10 does not show the transfer control unit, the first transfer execution unit, and the second transfer execution unit. The same applies to other arithmetic units described below.

Similarly, the second stage computing unit includes reg ₂ , computing unit ₂ , LD / ST ₂ , primary cache _2, and buffer cache ₂ . The second-stage arithmetic unit also includes the transfer control unit, the first transfer execution unit, and the second transfer execution unit of the first embodiment.

The third stage computing unit includes reg ₃ , computing unit ₃ , LD / ST ₃ , primary cache _3, and buffer cache ₃ . The third-stage arithmetic unit also includes the transfer control unit, the first transfer execution unit, and the second transfer execution unit of the first embodiment.

The fourth stage computing unit includes reg ₄ , computing unit ₄ , LD / ST ₄ , primary cache _4, and buffer cache ₄ . The fourth-stage arithmetic unit also includes the transfer control unit, the first transfer execution unit, and the second transfer execution unit of the first embodiment.

The n-th stage arithmetic unit includes reg _n , arithmetic unit _n , LD / ST _n , primary cache _n, and buffer cache _n . The n-th stage arithmetic unit also includes the transfer control unit, the first transfer execution unit, and the second transfer execution unit of the first embodiment.

  For ease of viewing the drawing, FIG. 10 does not show the transfer control unit, the first transfer execution unit, and the second transfer execution unit of the first to n-th stage calculation units.

Reg _{1 to} reg _n hold data necessary for the arithmetic processing in the arithmetic units ₁ to _n corresponding to each of them. Each of reg _{1 to} reg _n includes a register group (not shown) including a plurality of registers, and a transfer unit (not shown) for transferring read data of each register of the register group to the outside. Yes.

  Reading and writing to each register of the register group is executed based on the decoding result by the instruction decoding unit 80. Each register in the register group is read or written using its own register number as an access key.

When the read register number is specified, the transfer units reg _{1 to} reg _n transfer the data held in the register with the specified number to the outside.

The registers in each register group of reg _{1 to} reg _n have a one-to-one correspondence. Specifically, registers having the same register number are associated with each other in each register group of reg _{1 to} reg _n .

Each of the arithmetic units ₁ to _n performs substantial processing in the data processing device 3. Each of the arithmetic units ₁ to _n corresponds to each of the arithmetic units in the first embodiment.

Each of the computing units ₁ to _n includes a computing unit group (not shown) composed of a plurality of computing units, a cage group (not shown) consisting of a plurality of cages, and a transfer unit (not shown). Have.

Each transfer unit of reg _{1 to} reg _n can transfer the read data of the registers of each register group to the corresponding calculation units ₁ to _n . Then, the arithmetic unit _{1 to} each calculator arithmetic unit group of the arithmetic unit _n gets the two read data from among the registers reg ₁ through REG _n, arithmetic and logical operations such as various using those data The calculation process is executed. The arithmetic processing of each arithmetic unit is executed simultaneously.

Each holder of the holder group of the calculators ₁ to _n stores the calculation results of the calculators corresponding to the holders. Each retainer has a one-to-one correspondence with each arithmetic unit.

The transfer units of the calculation units ₁ to _n transfer the calculation results of the calculation units stored in the corresponding holding units to the outside.

Each of LD / ST _{1 to} LD / ST _n includes a load unit group (not shown) composed of a plurality of LDs (load units) and a store unit group composed of a plurality of STs (store units). .

Each of the primary cache ₁ to primary cache _n is connected to the corresponding LD / ST ₁ to LD / ST _n , and reads and writes in accordance with load and store operations by LD / ST _{1 to} LD / ST _n Is executed at high speed. Each of the primary cache ₁ to primary cache _n is configured using a small-capacity cache memory different from the large-capacity secondary cache 50.

Each of the buffer cache ₁ to the buffer cache _n needs to have a very small capacity in order to propagate the entire contents to the next and subsequent stages at the maximum. For this reason, each of the buffer cache ₁ to the buffer cache _n is configured by using a small-capacity cache memory different from the large-capacity secondary cache 50, similarly to each of the primary cache ₁ to the primary cache _n. Yes.

The data processing device 3 is premised on a known VLIW processor architecture. Therefore, a machine language instruction in the VLIW format usually constitutes a first stage arithmetic unit, reg ₁ , arithmetic unit ₁ , LD / ST ₁ , executed by the primary cache ₁ and the buffer cache ₁ . That is, the operation processing (non-array operation) by the VLIW method is executed by the first stage arithmetic unit.

Accordingly, register information necessary for starting the simultaneous operation (array operation) of the arithmetic processing by the plurality of arithmetic units in the first embodiment is always stored in reg ₁ .

When the array operation start instruction is detected by the decoding result of the instruction decoding unit 80, with respect to the arithmetic unit _{1 to} arithmetic unit _n, and stores the data necessary for the arithmetic processing by the arithmetic unit _{1 to} arithmetic unit _n register A source register number representing the register number of each, a computation type of computation processing by each computing unit ₁ to computing unit _n , and a destination representing a register number of a register that is a storage destination of computation results of each computing unit ₁ to computing unit _n Control information A including a register number is set in each of the first to n-th stage arithmetic units.

  This control information A may be arranged as additional information of the array operation start command. In this case, the control information A can be obtained at a time when the array operation start instruction is decoded.

  The control information A may be supplied as a subsequent VLIW instruction sequence itself. In this case, after the array operation start instruction is decoded, the subsequent VLIW instructions are successively decoded in order, and the backward branch instruction meaning loop repetition, that is, the instruction corresponding to the final stage of the array operation is decoded. A forward branch instruction meaning exit from the loop, that is, an instruction corresponding to the termination condition of the array operation can be detected and set as a pause condition. For this reason, control information to be added to the existing instruction sequence can be reduced.

At this time, if it is assumed that the data necessary for the arithmetic processing by each of the arithmetic units ₁ to _n is sequentially transmitted from the previous stage, the control information for all of the arithmetic units ₁ to _n is simultaneously controlled. The control information can be configured to arrive at the same time as the first data arrives at each of the computing units ₁ to _n .

  After the array operation starts, for example, one iteration of the loop structure is mapped to the arithmetic unit network, and a large amount of data processing is performed by sequentially flowing data.

That is, after the array operation is started, it is not necessary to change the control information for each of the arithmetic units ₁ to _n until the end of the array operation, and the instruction decode unit 80 required at the time of the non-array operation. It is no longer necessary to execute the decoding operation by. For this reason, the instruction decoding unit 80 is stopped, and further, the fetch operation by the instruction fetch unit 70 can be similarly stopped.

In addition, an array operation termination condition for stopping the array operation of each of the arithmetic units ₁ to _n is added to the control information A, and when the conditions specified in advance during the array operation are satisfied, In this case, the non-array operation is restored.

The array operation termination condition is specifically the number of execution cycles of each of the arithmetic units ₁ to _n .

The secondary cache 50 is connected only to the buffer cache ₁ held by the LD / ST ₁ . In the second and subsequent stages, the data in the buffer cache ₁ is sequentially propagated.

The load instruction refers to the primary cache ₁ and the buffer cache ₁ according to the address obtained by adding / subtracting the address information stored in reg ₁ in the arithmetic unit ₁ , and the obtained data is stored in the store unit group of the LD / ST _1. Stored in the store.

The data stored in the store unit becomes the input of the subsequent arithmetic unit ₂ or reg _{2 in} the next cycle.

  Next, the operation of the cache method of the data processing device 3 will be described. FIG. 11 is an explanatory diagram for explaining a cache method of the data processing device 3.

  As shown in FIG. 11, in the cache method 4 of the data processing device 3, the first stage arithmetic unit includes the primary cache 103 and the buffer cache 104, and the second stage arithmetic unit includes the primary cache 203 and the buffer cache 204. The third stage arithmetic unit includes a primary cache 303 and a buffer cache 304, the fourth stage arithmetic unit includes a primary cache 403 and a buffer cache 404, and the fifth stage arithmetic unit includes a primary cache 503 and a buffer cache 504. The sixth stage arithmetic unit includes a primary cache 603 and a buffer cache 604, the seventh stage arithmetic unit includes a primary cache 703 and a buffer cache 704, and the eighth stage arithmetic unit includes a primary cache 803 and a buffer cache 804. And the ninth stage arithmetic unit includes a primary cache 903 and a buffer. It contains Yasshu 904.

  The primary cache 103 is connected to the LD / STs 101 and 102, the primary cache 203 is connected to the LD / STs 201 and 202, the primary cache 303 is connected to the LD / STs 301 and 302, and the primary cache 403 is LD. / ST 401 and 402, the primary cache 503 is connected to the LD / ST 501 and 502, the primary cache 603 is connected to the LD / ST 601 and 602, the primary cache 703 is connected to the LD / ST 701 and 702, A primary cache 803 is connected to the LD / STs 801 and 802, and a primary cache 903 is connected to the LD / STs 901 and 902.

  The number of banks of the secondary cache 50 is 4 ways (Way0, Way1, Way2, Way3), and blocks including Way0, Way1, and Way2 data are sent to the buffer cache 104.

  In this cache system 4, for example, when pixel data “06, 16, 26” for one row in the vertical direction in 3 × 3 pixels is sent from the secondary cache 50 to the buffer cache 104 of the first stage arithmetic unit, The pixel data “05, 15, 25” for one line in the vertical direction stored in the buffer cache 104 until then is transferred to the primary cache 103 of the first stage arithmetic unit, and also the second stage arithmetic unit It is transferred to the buffer cache 204.

  Similarly, when pixel data “05, 15, 25” for one line in the vertical direction is sent from the buffer cache 104 of the first stage arithmetic unit to the buffer cache 204 of the second stage arithmetic unit, the buffer cache 204 up to that point The pixel data “04, 14, 24” for one line in the vertical direction stored in is transferred to the primary cache 203 of the second stage arithmetic unit and also transferred to the buffer cache 304 of the third stage arithmetic unit. The

  When pixel data “04, 14, 24” for one line in the vertical direction is sent from the buffer cache 204 of the second-stage arithmetic unit to the buffer cache 304 of the third-stage arithmetic unit, it is stored in the buffer cache 304 until then. The pixel data “03, 13, 23” for one line in the vertical direction is transferred to the primary cache 303 of the third stage arithmetic unit and is also transferred to the buffer cache 404 of the fourth stage arithmetic unit.

  When pixel data “03, 13, 23” for one line in the vertical direction is sent from the buffer cache 304 of the third stage arithmetic unit to the buffer cache 404 of the fourth stage arithmetic unit, it is stored in the buffer cache 404 up to that point. The pixel data “02, 12, 22” for one row in the vertical direction is transferred to the primary cache 403 of the fourth stage arithmetic unit and also transferred to the buffer cache 504 of the fifth stage arithmetic unit.

  When pixel data “02, 12, 22” for one line in the vertical direction is sent from the buffer cache 404 of the fourth-stage arithmetic unit to the buffer cache 504 of the fifth-stage arithmetic unit, it is stored in the buffer cache 504 until then. The pixel data “01, 11, 21” for one line in the vertical direction is transferred to the primary cache 503 of the fifth-stage arithmetic unit and also transferred to the buffer cache 604 of the sixth-stage arithmetic unit.

  When pixel data “01, 11, 21” for one line in the vertical direction is sent from the buffer cache 504 of the fifth-stage arithmetic unit to the buffer cache 604 of the sixth-stage arithmetic unit, it is stored in the buffer cache 604 until then. The pixel data “00, 10, 20” for one line in the vertical direction is transferred to the primary cache 603 of the sixth stage arithmetic unit and is also transferred to the buffer cache 704 of the seventh stage arithmetic unit.

  Also in the second embodiment, as in the first embodiment, each operation of the transfer control unit, the first transfer execution unit, and the second transfer execution unit of the first to ninth stage arithmetic units performs buffering. Controls data transfer between the caches 104, 204, 304, 404, 504, 604, 704, 804, 904 and the primary caches 103, 203, 303, 403, 503, 603, 703, 803, 903, and buffers Controls data transfer between the caches 104, 204, 304, 404, 504, 604, 704, 804, 904.

  The present invention is not limited to the above-described embodiments, and various modifications are possible within the scope shown in the claims, and embodiments obtained by appropriately combining technical means disclosed in different embodiments. Is also included in the technical scope of the present invention.

  The present invention can be suitably used for a data processing apparatus that simultaneously executes a plurality of machine language instructions at high speed.

1, 3, Data processing device 2 Blur processing program 4 Cache method 10 First stage operation unit 11, 11a, 21, 21a, 31, 31a, 41, 41a Operation unit 12, 12a, 22, 22a, 32, 32a, 42, 42a, 103, 203, 303, 403, 503, 603, 703, 803, 903 Primary cache (first cache)
13, 23, 33, 43, 104, 204, 304, 404, 504, 604, 704, 804, 904 Buffer cache 14, 24, 34, 44 Transfer control unit (specification unit)
15, 25, 35, 45 First transfer execution unit (first execution unit)
16, 26, 36, 46 Second transfer execution unit (second execution unit)
20 Second stage arithmetic unit 30 Third stage arithmetic unit 40 Fourth stage arithmetic unit 50, 50a Secondary cache (second cache)
60 Main memory 70 Instruction fetch unit 80 Instruction decode unit 101, 102, 201, 202, 301, 302, 401, 402, 501, 502, 601, 602, 701, 702, 801, 802, 901, 902 LD / ST

Claims (8)

A plurality of arithmetic units;
A plurality of first caches provided in each of the plurality of computing units and transferring data to the corresponding computing units;
A second cache for storing data shared by the plurality of computing units and used for each processing of the plurality of computing units;
A plurality of buffer caches provided in each of the plurality of first caches for transferring data to the corresponding first caches;
The plurality of buffer caches include a first-stage buffer cache connected to the second cache and to which data is transferred from the second cache;
Each of the plurality of buffer caches is sequentially connected sequentially from the first stage buffer cache,
Each of the plurality of buffer caches sequentially transfers a part of the data transferred from the second cache to the first-stage buffer cache to the subsequent stage of each buffer cache and is stored in each buffer cache. A data processing apparatus for transferring a part of stored data to a first cache corresponding to each buffer cache.   2. The data processing according to claim 1, wherein each of the plurality of buffer caches transfers data necessary for processing of an arithmetic unit corresponding to each buffer cache to a first cache corresponding to each buffer cache. apparatus.   Each of the plurality of first caches stops a storage operation of a storage unnecessary area that is unnecessary for storing data transferred from a corresponding buffer cache among the storage areas of each first cache. Item 3. A data processing apparatus according to Item 2.   Each of the plurality of buffer caches transfers data necessary for processing of an arithmetic unit corresponding to a buffer cache on the subsequent stage of each buffer cache to the buffer cache on the subsequent stage of each buffer cache. The data processing device according to any one of 1 to 3.   5. Each of the plurality of buffer caches stops a storage operation of a storage unnecessary area that is unnecessary for storing data transferred from a preceding buffer cache among storage areas of each buffer cache. The data processing apparatus described in 1. The data processing apparatus analyzes a data access pattern based on execution of a program to be processed by itself, and processes the program using the analysis result.
6. The data processing according to claim 3, wherein data necessary for each processing of the plurality of computing units is specified based on an analysis result of a data access pattern of a program processed by the data processing device. apparatus. A specifying unit for specifying data necessary for each processing of the plurality of arithmetic units based on the analysis result of the data access pattern of the program;
A first execution unit that is provided in each of the plurality of first caches and stops a storage operation of a storage unnecessary area of the corresponding first cache based on a specification result by the specification unit;
And a second execution unit that is provided in each of the plurality of buffer caches and stops the storage operation of the storage unnecessary area of the corresponding buffer cache based on the identification result by the identification unit. The data processing apparatus according to claim 6. The program processed by the data processing device has been previously analyzed for data access patterns,
Data necessary for each processing of the plurality of arithmetic units is specified in advance based on the analysis contents of the data access pattern of the program,
In each of the plurality of first caches, a storage area of each first cache is set in advance in order to store data necessary for each processing of the plurality of arithmetic units.
In each of the plurality of buffer caches, a storage area of each buffer cache is set in advance so as to transfer data necessary for each process of the plurality of arithmetic units to a corresponding first cache. The data processing apparatus according to claim 1.

Images