JP2011008166A - Image forming apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image forming apparatus in which digital information in accordance with voltage to be applied is temporarily converted into analog control voltage and then voltage corresponding to the control voltage is applied to respective parts, and which detects and copes with abnormality of the control voltage.SOLUTION: The digital information outputted by a CPU 50 is converted into the analog control voltage by a D/A converter 51, and applied to an electrifier, a developing roller, a transfer roller and a drum cleaner as CHG output, DEV output, TRCC output and DCLN output, through a CHG high voltage circuit 53, a DEV high voltage circuit 54, a TRCC high voltage circuit 55, and a DCLN high voltage circuit 56. The control voltage converted by the D/A converter 51 is inputted in the CPU 50 through a multiplexer 58, and compared with the digital information, thereby detecting occurrence of abnormality by noise or the like in a process in which the digital information is converted into the control voltage.

Description

  The present invention relates to an image forming apparatus including an image forming unit that forms an image on a recording medium. Specifically, the image forming unit includes a plurality of voltage applying units to which a voltage is applied, and each voltage applying unit includes The present invention relates to an image forming apparatus capable of controlling individually applied voltages.

  2. Description of the Related Art Conventionally, in an image forming apparatus that forms an image on a recording medium by various methods such as an electrophotographic method, a bias voltage is applied to each part of image forming means such as a printer engine. This bias voltage must be controlled to an appropriate value. However, if an abnormality occurs in the power supply or the control system, the bias voltage cannot be accurately controlled. In view of this, there has been proposed an image forming apparatus that compares an A / D conversion value of a fed back bias voltage with a PWM signal to determine an abnormality such as a power failure (see, for example, Patent Document 1).

JP-A-5-316742

  However, the D / A converter that performs the D / A conversion is relatively weak against noise, and it is difficult to detect an abnormality even if an analog voltage or the like after D / A conversion occurs. On the other hand, in Patent Document 1, since the PWM signal before D / A conversion and the bias voltage finally applied to each part are compared, it is impossible to accurately specify where the abnormality has occurred. . For this reason, the apparatus of Patent Document 1 cannot detect that the analog voltage obtained by D / A conversion becomes an abnormal value due to noise or the like.

  Therefore, the present invention detects an abnormality of the control voltage in an image forming apparatus that converts digital information corresponding to the voltage to be applied into an analog control voltage and then applies a voltage corresponding to the control voltage to each unit. It was made for the purpose of being able to cope with it.

  The image forming apparatus according to the present invention made to achieve the above object includes a plurality of voltage application units, and an image is formed on a recording medium by individually applying a voltage to each voltage application unit. Means, digital information output means for individually outputting digital information corresponding to the voltage value to be applied to each voltage application section for each voltage application section, and each digital information output from the digital information output means Are individually converted into control voltages, and a voltage corresponding to each control voltage is output for each voltage application unit, and converted by the control voltage conversion output means corresponding to each digital information. The control voltage detection means for detecting the control voltages, the digital information output by the digital information output means, and the control voltages detected by the control voltage detection means And when the abnormality determination means determines any of the control voltage abnormalities, the control voltage is output via the digital information output means. And digital information re-output means for re-outputting the digital information corresponding to the above.

  In the image forming apparatus of the present invention configured as described above, the image forming unit forms an image on a recording medium by individually applying a voltage to a plurality of voltage applying units included in the image forming unit. The digital information output means outputs digital information corresponding to the voltage value to be applied to each voltage application section individually for each voltage application section, and the control voltage conversion output means outputs from the digital information output means. Each digital information thus converted is once individually converted into, for example, an analog control voltage, and a voltage corresponding to each control voltage is output for each voltage application unit. As a result, each voltage application unit is individually applied with a voltage corresponding to each digital information output to the voltage application unit.

  Further, the abnormality determining means converts each of the digital information output from the digital information output means and the control voltage converted by the control voltage conversion output means corresponding to each digital information and detected by the control voltage detecting means. The voltage is sequentially compared, and each control voltage abnormality is judged individually. This makes it possible to satisfactorily determine that an abnormality due to noise or the like has occurred in the process of converting digital information into a control voltage. When the abnormality determining means determines any abnormality in the control voltage, the digital information re-output means re-outputs the digital information corresponding to the control voltage via the digital information output means. Then, by re-outputting the digital information, the control voltage can be returned to a normal value, and further, the voltage applied to each voltage application unit can be accurately controlled.

  The present invention is not limited to the following configuration, but when the abnormality determination means determines any abnormality in the control voltage, the digital information converted into the control voltage is output as the digital information. You may further provide the frequency change means which raises the frequency which a means outputs. In this case, by increasing the output frequency of the digital information that is converted into the control voltage determined to be abnormal by the abnormality determining means, it is possible to quickly cope with the abnormality of the control voltage.

  In this case, the frequency changing means changes the order in which each of the digital information output means outputs the digital information, thereby outputting the digital information that is converted into the control voltage for which the abnormality is determined. The order may be changed more frequently than the order in which the digital information converted into the other control voltages is output.

  In any one of the above inventions, when the abnormality determination unit determines any abnormality in the control voltage during the image formation by the image forming unit, the image formation unit performs the image formation again. An image regenerating unit may be further provided. In this case, even when an abnormal image is formed due to an abnormality in the control voltage, the image can be automatically formed again. Note that, for example, when a part of the control voltage is abnormal, such as a control voltage that does not significantly affect the image quality, the image re-forming unit does not have to re-execute image formation.

  In any one of the above-described inventions, the control voltage conversion output means further includes storage means for individually storing the control voltages converted by the control voltage conversion output means, and the control voltage conversion output means sequentially stores the digital information. Each of the control voltages is converted, and the abnormality determination means is a process until the control voltage conversion output means converts one digital information into the one control voltage and then converts the next digital information into the next control voltage. In the meantime, an abnormality of the control voltage different from the one control voltage stored in the storage means may be determined.

  In this case, since abnormality is determined by the abnormality determination means during the process of converting each digital information to each control voltage, each of the above voltages is minimized while minimizing the processing load when the control voltage abnormality is determined. The voltage applied to the application unit can be accurately controlled.

It is explanatory drawing which represents roughly the structure of the laser printer to which this invention was applied. It is a block diagram showing the structure of the electric control part of the laser printer. It is a flowchart showing the process at the time of image formation performed with the electric control part. It is a flowchart showing the high voltage | pressure control of the process at the time of the image formation in detail. It is a flowchart showing in detail the DAC reading control of the above-mentioned image forming process. It is a flowchart showing the modification of the said image formation process. It is a flowchart showing the other modification of the said image formation process. It is a flowchart showing in detail the mode change process of the image forming process.

[Laser printer configuration]
Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is an explanatory diagram schematically showing the configuration of a laser printer 1 as an image forming apparatus to which the present invention is applied. As shown in FIG. 1, the laser printer 1 according to the present embodiment includes an image forming unit 10 as an example of an image forming unit that forms an image on a sheet P as an example of a recording medium by an electrophotographic method. .

  The image forming unit 10 forms a toner image on the sheet P while the sheet P is sandwiched between the photosensitive drum 11 and the transfer roller 12 and conveyed in the arrow direction. The photosensitive drum 11 is grounded and a positively charged photosensitive layer is formed on the surface thereof. The photosensitive drum 11 is supported by the laser printer 1 so as to be rotatable counterclockwise in FIG.

  Further, on the outer periphery of the photosensitive drum 11, a charger 13, a laser scanner unit 14, and a developing unit 15 are sequentially disposed along the rotation direction of the photosensitive drum 11 from a portion facing the transfer roller 12. . The charger 13 is a scorotron charger for positive charging that generates a corona discharge when a high voltage is applied to the charging wire 13 </ b> A and detects the voltage via the grid 13 </ b> B. It is configured to uniformly charge the surface to positive polarity. The laser scanner unit 14 emits a laser beam L corresponding to image data input from the outside from a light source (not shown), and the laser beam is reflected by a mirror surface of a polygon mirror (not shown) rotated by a polygon motor. L is scanned to irradiate the surface of the photosensitive drum 11.

  The developing unit 15 includes a developing roller 16 at a portion facing the photosensitive drum 11. The developing unit 15 is triboelectrically charged by a well-known supply roller, a layer thickness regulating blade, etc. (not shown) of a positively chargeable non-magnetic one-component polymer toner (not shown) accommodated in the developing unit 15. However, the toner is supplied to the surface of the photosensitive drum 11 through the developing roller 16.

  For this reason, the surface of the photosensitive drum 11 is first uniformly charged positively by the charger 13 along with the rotation of the photosensitive drum 11, and then by high-speed scanning of the laser light L from the laser scanner unit 14. It is exposed to form an electrostatic latent image corresponding to the image data.

  Next, when a positively charged toner is supplied from the developing unit 15 to the photosensitive drum 11, the toner is an electrostatic latent image formed on the surface of the photosensitive drum 11, that is, a uniform positive toner. The charged surface of the photosensitive drum 11 is supplied to the exposed portion exposed to the laser beam L and the potential is lowered, and is selectively carried to be visualized, thereby forming a toner image. Is done.

  The transfer roller 12 is supported by the laser printer 1 so as to be rotatable in the clockwise direction in FIG. The transfer roller 12 is configured such that a metal roller shaft is covered with a roller made of an ion conductive rubber material, and a transfer bias (transfer forward bias) is applied during transfer. Therefore, the toner image carried on the surface of the photosensitive drum 11 is transferred to the paper P while the paper P passes between the photosensitive drum 11 and the transfer roller 12. A drum cleaner 17 is disposed on the surface of the photosensitive drum 11 disposed between the transfer roller 12 and the charger 13, and toner and dust remaining on the surface of the photosensitive drum 11 are removed from the drum cleaner 17. Is adsorbed electrostatically. Further, the sheet P after the toner image is transferred is conveyed to a fixing device 20 provided with a heating roller 21 and a pressure roller 22, and the toner image is thermally fixed.

[Configuration of electrical control unit]
Next, FIG. 2 shows a configuration of an electric control unit that applies a bias voltage to each part of the charger 13, the developing roller 16, the transfer roller 12, the drum cleaner 17, and the like (each corresponding to an example of a voltage applying unit). It is a block diagram. As shown in FIG. 2, the electric control unit is a CPU 50 as an example of a digital information output unit that outputs digital information (which may be a clock signal or serial data) according to a voltage value to be applied to each unit. It has. Each digital information output from the CPU 50 controls the D / A converter 51, and the D / A converter 51 outputs an analog control voltage of 0 to 5V. The control voltage is input to a CHG (charging) high voltage circuit 53, a DEV (development) high voltage circuit 54, a TRCC (transfer) high voltage circuit 55, and a DCLN (drum cleaning) high voltage circuit 56 corresponding to the control object of the digital information. Is done. The D / A converter 51 and the high-voltage circuits 53 to 56 correspond to an example of a control voltage conversion output unit.

  The CHG high voltage circuit 53 applies (outputs) a high voltage (CHG output) corresponding to the control voltage input from the D / A converter 51 to the charging wire 13 </ b> A of the charger 13. The DEV high voltage circuit 54 applies (outputs) to the developing roller 16 a high voltage (DEV output) corresponding to the control voltage input from the D / A converter 51. The TRCC high voltage circuit 55 applies (outputs) a high voltage (TRCC output) corresponding to the control voltage input from the D / A converter 51 to the transfer roller 12. The DCLN high voltage circuit 56 applies (outputs) a high voltage (DCLN output) corresponding to the control voltage input from the D / A converter 51 to the drum cleaner 17. In addition, since the circuit which outputs the high voltage according to the control voltage of 0-5V in this way is well-known, detailed description of the structure of each said high voltage circuit 53-56 is omitted.

  The control voltage input from the D / A converter 51 to each of the high voltage circuits 53 to 56 is input to the A / D input port of the CPU 50 via the multiplexer 58. Then, each of the control voltages is individually digitized by an A / D converter 50C (corresponding to an example of a control voltage detection unit) built in the CPU 50, and is used for processing described later. The DEV output, TRCC output, and DCLN output are detected by the DEV detection circuit 64, TRCC detection circuit 65, and DCLN detection circuit 66, respectively, and are supplied to the multiplexer 61 together with the voltage (GRID input) of the grid 13B detected by the GRID detection circuit 63. Have been entered. However, the TRCC detection circuit 65 inputs a voltage corresponding to the current value of the TRCC output to the multiplexer 61.

  The multiplexer 61 inputs each of these input voltages to another A / D input port of the CPU 50, and the A / D converter 50D built in the CPU 50 individually digitizes these inputs. The voltage input from the multiplexer 61 is converted into a digital value by the CPU 50 and then temporarily stored in a RAM 50B as an example of a storage unit built in the CPU 50.

[Processing in electrical control unit]
Next, image forming processing executed based on a program stored in the ROM 50A in which the CPU 50 is built when the image forming unit 10 forms an image will be described with reference to the flowchart of FIG. During the image formation, the laser scanner unit 14 and the like are controlled in parallel with this process. In addition to the image formation, this processing is appropriately executed as necessary, such as during cleaning or patch mark formation (in the case of a color printer).

  As shown in FIG. 3, in this process, first, the upper limit value and lower limit value of the DEV output, the TRCC output, the DCLN output, and the GRID input are set in S1 (S represents a step; the same applies hereinafter). Further, the control mode is set to CHG. In subsequent S2, it is determined whether or not the control mode is CHG. Since the control mode is initially CHG (S2: Y), the process proceeds to S3. In S3, it is determined whether or not it is the application timing of the CHG output. If it is the application timing (S3: Y), the following CHG high-pressure control is executed in the subsequent S4.

  FIG. 4 is a flowchart showing the CHG high pressure control in detail. The CHG high pressure control (S4) is substantially the same as the DEV high pressure control (S14), TRCC high pressure control (S24), and DCLN high pressure control (S34), which will be described later, and the flowchart of FIG. 4 is generalized. It was. As shown in FIG. 4, in this process, first, in S41, the voltage of the grid 13B detected by the GRID detection circuit 63 is input from the multiplexer 61 and digitized through the A / D converter 50D of the CPU 50. Is read as the FB voltage.

  In subsequent S42, it is determined whether or not the read FB voltage is smaller than the target lower limit value set in S1. If the FB voltage is smaller than the target lower limit value (S42: Y), the process proceeds to S43, where the DA setting value (the digital information output to the D / A converter 51 is CHG_DA setting value in the case of CHG output). (Also in other control modes) is reset to a value higher by ΔDA. In the subsequent S45, DA writing is performed with the reset DA setting value. That is, the DA set value is output to the D / A converter 51 as digital information.

  On the other hand, when the FB voltage is equal to or higher than the target lower limit (S42: N), the process proceeds to S47, and it is determined whether or not the FB voltage is larger than the target upper limit set in S1. If the FB voltage is less than or equal to the target upper limit value (S47: N), and if the FB voltage is greater than the target upper limit value (S47: Y), after the DA set value is reset to a value lower by ΔDA in S48, The process proceeds to S45 described above. In this way, the DA set value is adjusted so that the FB voltage falls between the target lower limit value and the target upper limit value. Note that ΔDA is a fixed value set in advance corresponding to each of CHG, DEV, TRCC, and DCLN.

  Returning to FIG. 3, on the other hand, if it is not the CHG application timing (S3: N), 0 is output to the D / A converter 51 as the CHG_DA set value. When the CHG_DA set value is output in S4 or S5, the process proceeds to S6, and the following TRCC_DAC reading control is executed.

  FIG. 5 is a flowchart showing in detail the TRCC_DAC reading control. Note that this TRCC_DAC read control (S6) is almost the same as DCLN_DAC read control (S16), CHG_DAC read control (S26), and DEV_DAC read control (S36) described later, so the flowchart of FIG. 5 is generalized notation. It was.

  As shown in FIG. 5, in this process, first, in S61, the DAC voltage, that is, the latest control voltage output from the D / A converter 51 (in this case, the voltage output to the TRCC high voltage circuit 55) is obtained. Digital information DAC_V read through the multiplexer 58 and digitized by the A / D converter 50C built in the CPU 50 is obtained in S62. If the D / A converter 51 and the A / D converter 50C perform conversion with the same number of bits, the value obtained from the A / D converter 50C and the value output to the D / A converter 51 are directly compared. Can do.

  In the subsequent S63 (an example of abnormality determination means), the digital value DAC_V is the latest digital information output from the CPU 50 to output the control voltage (in this case, the TRCC_DA set value output in S24 or S25 described later). ). If DAC_V is within the range of ± 2 × ΔDA with respect to the DAC set value (S63: N), the process proceeds to S7 in FIG. 3 as it is, and if DAC_V is not within the above range (S63). : Y) After the following processing is performed in S64, the processing proceeds to S7 in FIG.

  That is, in S64, the DA setting value is rewritten, that is, the DA setting value output immediately before the process (in this case, the TRCC_DA setting value) is re-output as digital information with exactly the same value (digital information re-recording). Processing as an example of output means). In S64, one of four rewrite flags (DEV rewrite flag, CHG rewrite flag, TRCC rewrite flag, DCLN rewrite flag) that is reset to 0 when the power is turned on corresponds to the DA set value (in this case, TRCC rewrite). Flag) is set to 1.

  Returning to FIG. 3, in S7, the control mode is set to DEV, and after waiting for 1 ms in S8, it is determined whether or not the period for applying the various voltages is completed after the image formation is completed. (S9). If the necessary period of application has not ended (S9: N), the process proceeds to S2 described above, and it is determined whether or not the control mode is CHG.

  This time, since the control mode is set to DEV in S7 (S2: N), the process proceeds to S12, and it is determined whether or not the control mode is set to DEV. Since the control mode is DEV (S12: Y), the process proceeds to S13, and it is determined whether it is the DEV output application timing. As in the case where the control mode is CHG, when the application timing is reached (S13: Y), DEV_DA adjusted so that the FB voltage (DEV output) falls between the target lower limit value and the target upper limit value in S14. If the set value is not the application timing (S13: N), 0 is output as the DEV_DA set value to the D / A converter 51 in S15, and the process proceeds to S16. In S16, the DAC read control similar to S6 described above is executed for the most recent control voltage output to the DCLN high voltage circuit 56, and after the control mode is set to TRCC in S17, the process proceeds to S8 described above. Migrate to

  And when the required period of application of various voltages is not complete | finished (S9: N), a process transfers to above-mentioned S2. This time, since the control mode is set to TRCC in S17, a negative determination is made in S2 and S12 described above, the process proceeds to S22, and it is determined whether or not the control mode is set to TRCC. . Since the control mode is TRCC (S22: Y), the process proceeds to S23, and it is determined whether it is the application timing of the TRCC output. As described above, when it is the application timing (S23: Y), the TRCC_DA set value adjusted so that the FB voltage (TRCC output) falls between the target lower limit value and the target upper limit value in S24 is applied. If it is not the timing (S23: N), 0 is output as the TRCC_DA set value to the D / A converter 51 in S25, and the process proceeds to S26. In S26, the DAC read control similar to S6 described above is executed for the latest control voltage output to the CHG high voltage circuit 53, and after the control mode is set to DCLN in S27, the processing is performed in S8 described above. Migrate to

  And when the required period of application of various voltages is not complete | finished (S9: N), a process transfers to above-mentioned S2. This time, the control mode is set to DCLN in S27, and a negative determination is made in S2, S12, and S22 described above. Therefore, the control mode is determined to be DCLN, the process proceeds to S33, and the DCLN output is output. It is determined whether it is the application timing.

  As described above, when it is the application timing (S33: Y), the DCLN_DA set value adjusted so that the FB voltage (DCLN output) falls between the target lower limit value and the target upper limit value in S34 is applied. If it is not the timing (S33: N), 0 is output as the DCLN_DA setting value to the D / A converter 51 in S35, and the process proceeds to S36. In S36, the DAC read control similar to S6 described above is executed for the most recent control voltage output to the DEV high voltage circuit 54, and after the control mode is set to CHG in S37, the process proceeds to S8 described above. Migrate to

  Hereinafter, similarly, the above-described processing is repeated while cyclically changing the control mode as CHG → DEV → TRCC → DCLN → CHG. When the necessary period for applying various voltages is completed (S9: Y), this process is temporarily terminated.

[Effects of the present embodiment]
As described above, in this embodiment, the latest digital information output from the CPU 50 is compared with the control voltage output from the D / A converter 51 corresponding to the digital information, and each control voltage is abnormal. Individual determination is made (S61 to S63). For this reason, it is possible to satisfactorily determine that an abnormality due to noise or the like has occurred in the process of converting the digital information into a control voltage. If the error between them is larger than the predetermined value 2 × ΔDA (S63: Y), it is determined that there is an abnormality, and the digital information is re-output (S64). For this reason, when the digital information is re-outputted, the control voltage can be returned to the normal value, and the voltage applied to each unit can be accurately controlled. Further, the rewrite flag set in S64 can be applied to various error processing and maintenance.

  In the above embodiment, since the digital information is output at that time and the control voltage abnormality according to the control mode different from the control voltage converted from the digital information is determined, the following further An effect is produced.

  In the present embodiment, a plurality of control modes CHG, DEV, TRCC, TCLN and the control mode are cyclically changed. And the timing (S4, S14, S24, S34) which outputs digital information and converts it into a control voltage, and the timing (S26, S36, S6, S16) which judge abnormality of a control voltage differ. Specifically, a process of rewriting the DA setting value when a control voltage abnormality is determined is performed between S4 and writing of the DA setting value in S14 (S45) (S64). Therefore, the control voltage abnormality can be corrected while minimizing the burden on the CPU 50 when the control voltage abnormality is determined.

[Other embodiments]
In addition, this invention is not limited to the said embodiment at all, It can implement with a various form in the range which does not deviate from the summary of this invention. For example, in S64, the DA setting value that has been output most recently is re-output as digital information with exactly the same value, but it is not necessarily required to be digital information with the same value. For example, digital information that is + ΔDA or −ΔDA in a direction out of the range of ± 2 × ΔDA may be output again. Further, the D / A converter 51 may be provided for each of the high voltage circuits 53 to 56.

  Furthermore, as described above, the rewrite flag that is set when an abnormality is detected can be applied to various controls. For example, when a specific rewrite flag is set to 1, a reprint command is issued as follows. The image formation may be performed again from the beginning.

  FIG. 6 is a flowchart showing image forming processing corresponding to the control. Note that this image forming process is the same as that in FIG. 3 until the period in which the application of various voltages is necessary and the determination in S9 is affirmative, so only the differences are shown in FIG. . Hereinafter, this difference will be described.

  As shown in FIG. 6, when the necessary period of application of various voltages ends (S9: Y), whether or not any of the DEV rewrite flag, CHG rewrite flag, and TRCC rewrite flag is set to 1 in S98. Is judged. If none of the rewrite flags is set (S98: N), the process is temporarily terminated. If any of the rewrite flags is set (S98: Y), the image re-forming unit is an example. After the reprint command is issued in S99, the process is temporarily terminated. In response to the reprint command, the image formation is restarted from the beginning.

  In this case, even when an abnormal image is formed due to an abnormality in the control voltage, the image can be automatically formed again. Since the DCLN output does not significantly affect the image quality, whether or not the control voltage is abnormal is not determined in S98, and the image formation is not repeated even if the DCLN output is abnormal. .

  Further, for a control mode in which an abnormality in the control voltage is detected and the rewrite flag is set to 1, control may be executed such that the execution frequency of the control mode is increased. FIG. 7 is a flowchart showing the image forming process corresponding to such control. This process is performed until the DA set value is output as digital information, that is, the process from S1 to any one of S4, S5, S14, S15, S24, S25, S34, and S35. 3 are the same as those in FIG.

  Hereinafter, differences will be described. As shown in FIG. 7, when the DA set value is output as digital information in any of S4, S5, S14, S15, S24, S25, S34, and S35, the process proceeds to S600, and each of the four control voltages The DAC read control (see FIG. 5) is sequentially executed. In subsequent S700, the following mode change process is executed. FIG. 8 is a flowchart showing the mode change process in detail.

  As shown in FIG. 8, in this process, first, in S701, it is determined whether or not any rewrite flag is set to 1 (whether rewriting is present). If no rewrite flag is set to 1 (S701: N), the process proceeds to S702, the normal control mode order is selected, and the process proceeds to S703. Here, in the present embodiment, as shown in the following Table 1, four types of control mode order are set: normal, CHG priority, DEV priority, TRCC priority, and DCLN priority. As shown in Table 1, in the normal control mode order, the control mode is changed in the same order as in the above-described embodiment.

Ｓ７０３では、その時点で選択されている制御モード順に従って、制御モードが次の制御モードに変更される。続くＳ７０４では、現時点（Ｓ７０３による変更後）の制御モードが、表１に規定する３番で、かつ、優先チャンネル（優先される制御モード）であるか否かが判断される。通常の制御モードでは、優先チャンネル自体が存在しないので、Ｓ７０４では否定判断がなされ、Ｓ７０５にて１ｍｓ待機がなされた後、処理は上記実施の形態と同様のＳ９（図７）へ移行する。すなわち、いずれの書換フラグも１にセットされていない場合は（Ｓ７０１：Ｎ）、Ｓ６００にて各制御電圧に対するＤＡＣ読込制御が実行される点を除いて、上記実施の形態と同様の制御が実行される。

In S703, the control mode is changed to the next control mode in accordance with the control mode order selected at that time. In subsequent S704, it is determined whether or not the current control mode (after the change in S703) is No. 3 defined in Table 1 and is a priority channel (prioritized control mode). In the normal control mode, since the priority channel itself does not exist, a negative determination is made in S704, and after waiting for 1 ms in S705, the process proceeds to S9 (FIG. 7) similar to the above embodiment. That is, when none of the rewrite flags is set to 1 (S701: N), the same control as the above embodiment is executed except that the DAC read control for each control voltage is executed in S600. Is done.

  On the other hand, if any of the rewrite flags is set to 1 (S701: Y), the process proceeds to S711, it is determined whether or not the DEV rewrite flag is set to 1, and the DEV rewrite flag is set. If yes (S711: Y), the process proceeds to S712. In S712, the DEV-priority control mode order is selected, and in the subsequent S713, ΔDA (hereinafter referred to as ΔDA (DEV): the same applies to other control modes) added to or subtracted from the DEV_DA set value is set to a half of the specified value. After the setting, the process proceeds to S703 described above.

  Here, as shown in Table 1, TRCC and DEV are set as No. 3 in the DEV priority control mode order, and in S703, the control mode is changed in the order of DEV → CHG → TRCC → DEV → DCLN. Is done. However, if the order of the control mode after the change in S703 is No. 3 and the priority channel (DEV in this case) (S704: Y), the process proceeds to S9 without waiting for 1 ms in S705. For this reason, the DEV control mode is executed twice as often as before without changing the overall control cycle. For this reason, in S713, ΔDA (DEV) is set to a half value to suppress the DEV_DA setting value from fluctuating excessively. Note that the processing of S713 does not need to be repeated many times. If ΔDA (DEV) has already been set to a half of the specified value, the processing proceeds to S713 again. The value is also maintained.

  If any of the rewrite flags is set to 1 (S701: Y) and the DEV rewrite flag is not set (S711: N), the process proceeds to S721, and the CHG rewrite flag is set to 1. It is determined whether or not. If the CHG rewrite flag is set (S721: Y), as in the case of DEV, the CHG priority control mode order is selected in S722, and ΔDA (CHG) is half the specified value in S723. The process proceeds to the above-described S703. Then, as in the case of DEV, the CHG control mode is executed twice as much as before without changing the overall control cycle so much.

  If any one of the rewrite flags is set to 1 (S701: Y) and neither the DEV rewrite flag nor the CHG rewrite flag is set (S711: N, S721: N), the process proceeds to S731. It is determined whether the TRCC rewrite flag is set to 1. When the TRCC rewrite flag is set (S731: Y), as in the case of DEV, the TRCC priority control mode order is selected in S732, and ΔDA (TRCC) is half the specified value in S733. The process proceeds to the above-described S703. Then, as in the case of DEV, the TRCC control mode is executed twice as much as before without changing the overall control cycle so much.

  Further, when any of the rewrite flags is set to 1 (S701: Y) and neither the DEV rewrite flag, the CHG rewrite flag, or the TRCC rewrite flag is set (S711: N, S721: N, S731: N) ), When the DCLN rewrite flag is set to 1. Therefore, in this case, the DCLN priority control mode order is selected in S742, ΔDA (DCLN) is reset to a half of the specified value in S743, and the process proceeds to the above-described S703. Then, as in the case of DEV, the DCLN control mode is executed twice as much as before without changing the overall control cycle so much. In the above process, S712, S722, S732, and S742 correspond to the frequency changing means.

  In the present embodiment, for a control mode in which an abnormality in the control voltage is detected and the rewrite flag is set to 1, the execution frequency of the control mode is high and the output frequency of the DA set value is also high. The control voltage abnormality can be quickly dealt with.

  In the present embodiment, when a plurality of rewrite flags are set to 1, the execution frequency of only the highest control mode in the order of DEV, CHG, TRCC, and DCLN is doubled. The order of the control modes is the order in which the influence on the image quality is large when the output of the control mode is out of the range of the upper and lower limit values. For this reason, in the present embodiment, when abnormality is detected in a plurality of control voltages, it is possible to preferentially increase the execution frequency of the control mode that has a large effect on the image quality, and the image due to the abnormality in the control voltage. It is possible to better suppress the deterioration of the quality.

  Further, in this embodiment, a reprint command may be issued when any or specific rewrite flag is set to 1 as shown in FIG. The execution frequency may be changed when image formation is performed again.

DESCRIPTION OF SYMBOLS 1 ... Laser printer 10 ... Image forming part 11 ... Photosensitive drum 12 ... Transfer roller 13 ... Charger 13A ... Charging wire 13B ... Grid 14 ... Laser scanner unit 16 ... Developing roller 17 ... Drum cleaner 50 ... CPU 50A ... ROM
50B ... RAM 51 ... D / A converter 53 ... CHG high voltage circuit 54 ... DEV high voltage circuit 55 ... TRCC high voltage circuit 56 ... DCLN high voltage circuit 63 ... GRID detection circuit 64 ... DEV detection circuit 65 ... TRCC detection circuit 66 ... DCLN detection circuit L ... Laser beam P ... Paper

Claims (5)

An image forming unit that includes a plurality of voltage application units and forms an image on a recording medium by individually applying a voltage to each voltage application unit;
Digital information output means for outputting digital information corresponding to the voltage value to be applied to each voltage application unit individually for each voltage application unit;
Control voltage conversion output means for individually converting each digital information output from the digital information output means to a control voltage, and outputting a voltage corresponding to each control voltage for each voltage application unit,
Control voltage detection means for detecting each control voltage converted by the control voltage conversion output means corresponding to each digital information;
Each of the digital information output by the digital information output means and the control voltage detected by the control voltage detection means are sequentially compared, and abnormality determination means for individually determining the abnormality of each control voltage;
A digital information re-output means for re-outputting the digital information corresponding to the control voltage via the digital information output means when the abnormality determination means determines any abnormality in the control voltage;
An image forming apparatus comprising: A frequency changing means for increasing the frequency at which the digital information output means outputs the digital information converted into the control voltage when the abnormality determining means determines any abnormality in the control voltage;
The image forming apparatus according to claim 1, further comprising:   The frequency changing means changes the order in which the digital information output means outputs the digital information, so that the order in which the digital information converted into the control voltage for which the abnormality has been determined is output is different from the other. 3. The image forming apparatus according to claim 2, wherein the digital information converted into the control voltage is circulated more frequently than the output order. An image re-forming unit that re-executes the formation of the image by the image forming unit when the abnormality determining unit determines any abnormality of the control voltage during the image formation by the image forming unit;
The image forming apparatus according to claim 1, further comprising: Storage means for individually storing the control voltages converted by the control voltage conversion output means,
In addition,
The control voltage conversion output means sequentially converts the digital information into the control voltages,
The abnormality determining means stores the information in the storage means after the control voltage conversion output means converts one digital information into the one control voltage and before converting the next digital information into the next control voltage. The image forming apparatus according to claim 1, wherein an abnormality of a control voltage different from the one control voltage is determined.

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