JP2011007843A - Display device and method for driving the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a display device and a method for driving a display device, favorably displaying an image even when the luminance of a group of display elements varies according to the order in which they are scanned.SOLUTION: A predetermined second node initializing voltage is applied to the p-th feeder line, thereby performing the preprocessing for changing the potential of a first node to the potential obtained by adding the threshold voltage of a driving transistor to the potential of one source/drain region of the driving transistor, in the state where a potential difference between an anode electrode and a cathode electrode provided on a light emitting part does not exceed the threshold voltage of the light emitting part. Subsequently, after auxiliary voltage having the same polarity as the driving voltage and a larger absolute value is applied to the p-th feeder line during a predetermined period, the driving voltage is applied to the p-th feeder line.

Description

  The present invention relates to a display device and a driving method of the display device.

  A display element including a current-driven light emitting unit and a display device including the display element are well known. For example, a display element (hereinafter, simply abbreviated as an organic EL display element) provided with an organic electroluminescence light emitting unit utilizing electroluminescence (hereinafter, abbreviated as EL) of an organic material is used. As a display element that can emit light with high brightness by low-voltage direct current drive, it is attracting attention.

  Similar to the liquid crystal display device, for example, in a display device including an organic EL display element (hereinafter, sometimes simply referred to as an organic EL display device), as a driving method, a simple matrix method and an active matrix method are used. Is well known. The active matrix method has a disadvantage that the structure is complicated, but has an advantage that the luminance of the image can be increased. In an organic EL display element driven by an active matrix method (hereinafter, sometimes simply referred to as a display element), in addition to a light emitting part composed of an organic layer including a light emitting layer, a light emitting part is provided. A drive circuit for driving is provided.

A drive circuit (referred to as a 2Tr / 1C drive circuit) composed of two transistors and one capacitor as a circuit for driving an organic electroluminescence light-emitting unit (hereinafter sometimes simply referred to as a light-emitting unit). However, this is well known, for example, from JP 2007-310311 A (Patent Document 1). As shown in FIG. 2, the 2Tr / 1C driving circuit includes two transistors, a write transistor TR _W and a driving transistor TR _D , and further includes a single capacitor C ₁ .

  FIG. 23 shows a conceptual diagram of a conventional display device. The display device includes N display elements 10 arranged in a two-dimensional matrix, N in the first direction, M in a second direction different from the first direction, and a total of N × M. . The display device further includes M scanning lines SCL extending in the first direction, N data lines DTL extending in the second direction, and M power supply lines PS1 extending in the first direction. . The scanning line SCL is connected to the scanning circuit 101. The data line DTL is connected to the signal output circuit 102. The feeder line PS1 is connected to the power supply unit 100.

As shown in FIG. 2, in the display device 10, in the driving transistor TR _D, the other source / drain region is connected to one end of the light emitting portion ELP, and, connected to one electrode of the capacitor C ₁ The second node ND ₂ is configured. The gate electrode is connected to the other source / drain region of the write transistor TR _W and is connected to the other electrode of the capacitor C ₁ , and constitutes the first node ND ₁ . In the write transistor TR _W is one of the source / drain regions is connected to the data line DTL, the gate electrode is connected to the scan line SCL. The cathode electrode of the light emitting unit ELP is connected to the second feeder line PS2. The second power supply line PS2 is a common power supply line. A voltage V _Cat (for example, 0 volt) is applied to the second feeder line PS2.

  As shown in FIG. 23, the display elements 10 in the m-th row are connected to the m-th scanning line SCL and constitute one display element group. In this display device, the display element 10 is line-sequentially scanned in units of display element groups, and displays a predetermined image based on the video signal from the signal line DTL.

JP 2007-310311 A

  In the display device shown in FIG. 23, the number of power supply lines PS1 is M as is the number of scanning lines SCL. Based on the operation of the power supply unit 100, the voltage applied to the power supply line PS1 is controlled in synchronization with the signal applied to the scanning line SCL. The power supply unit 100 basically includes a shift register circuit having the number of stages corresponding to the number of power supply lines PS1, a level shift circuit provided corresponding to the shift register circuit of each stage, and the like. In the display device shown in FIG. 23, when the number of rows of display elements is increased as the size and resolution are increased, the number of feeder lines PS1 is increased by the same number as the increased number of rows of display elements. As a result, the circuit scale of the power supply unit 100 increases and the cost of the power supply unit 100 increases. In order to reduce the cost and size of the display device, it is preferable to reduce the circuit scale of the power supply unit 100.

  If one power supply line is shared by a plurality of display element groups, the circuit scale of the power supply unit can be reduced, and the above-described increase in cost can be suppressed. However, in the display device having this configuration, as described later, a phenomenon in which the luminance of the display element group changes according to the scanning order is recognized. In particular, a luminance difference is noticeable between a display element group connected to a certain power supply line and a display element group adjacent to the display element group and connected to a power supply line different from the certain power supply line. Such a problem arises.

  Accordingly, an object of the present invention is to provide a display element group connected to a certain feeder line and a display element group adjacent to the display element group and connected to a feeder line different from the certain feeder line. It is an object of the present invention to provide a display device capable of reducing the luminance difference between them and a method for driving the display device.

In order to achieve the above object, a display device according to the present invention, and a display device used in a method for driving the display device according to the present invention,
N display elements arranged in a two-dimensional matrix of N in the first direction, M in the second direction different from the first direction, and a total of N × M,
One row of display elements arranged in the first direction constitutes one display element group, and P display area portions formed by a plurality of display element groups arranged adjacent to each other (where P is And a display area is formed by P display area portions arranged in the second direction, and the display area of the pth display area (where p = 1, 2,..., P) The part is represented as region DA (p),
For each part of the display area, the display element is a display device that is scanned in units of display element groups,
The display device further includes M scanning lines extending in the first direction, N data lines extending in the second direction, and P power supply lines extending in the first direction.
The display element includes a light emitting unit, and a drive circuit for driving the light emitting unit by passing current.
The drive circuit includes a write transistor, a drive transistor, and a capacitor,
In the display element of the m-th row (where m = 1, 2,..., M) and the n-th column (where n = 1, 2,..., N),
In the driving transistor, the other source / drain region is connected to one end of the light-emitting portion and is connected to one electrode of the capacitor portion to form a second node, and the gate electrode is the writing transistor Is connected to the other source / drain region of the capacitor, and is connected to the other electrode of the capacitor portion, forming a first node,
In the write transistor, one source / drain region is connected to the nth data line, and the gate electrode is connected to the mth scan line,
In the display element group forming the region DA (p), one source / drain region of the drive transistor constituting the display element relates to a display device connected to the p-th feeder line.

And the drive method of the display apparatus which concerns on this invention for achieving said objective is as follows.
(A) A predetermined first node initialization voltage is applied to the first node in a state where a predetermined drive voltage is applied from the p-th feeder line to one source / drain region of the drive transistor, thereby A threshold voltage canceling process for changing the potential of the second node toward the potential obtained by subtracting the threshold voltage of the driving transistor from the potential of the one node is performed at least once, and then
(B) performing a writing process of applying a video signal from the data line to the first node via the writing transistor;
(C) In a state where a predetermined drive voltage is applied to the p-th power supply line, the write transistor is turned off to make the first node floating, and the first node and the second node are connected via the drive transistor. A current corresponding to the value of the potential difference between and is sent to the light emitting part, and then
(D) In a state where a predetermined drive voltage is applied to the p-th feeder line, a turn-off signal is applied to the first node, so that the drive transistor is turned off.
It has a process,
Steps (a) to (d) are repeated, and after the step (d) has been completed for all display elements forming the region DA (p) and until the next step (a) is performed. In addition,
(E) A predetermined second node initialization voltage is applied to the p-th feeder line, so that the potential difference between the anode electrode and the cathode electrode provided in the light emitting unit does not exceed the threshold voltage of the light emitting unit. In this state, pre-processing for changing the potential of the first node toward the potential obtained by adding the threshold voltage of the driving transistor to the potential of one of the source / drain regions of the driving transistor is performed. This is a driving method of a display device in which an auxiliary voltage having the same polarity as the driving voltage and a larger absolute value is applied for a predetermined period, and then the driving voltage is applied to the p-th feeder line.

In addition, a display device according to the present invention for achieving the above object is
(A) A process in which a predetermined first node initialization voltage is applied to the first node in a state where a predetermined drive voltage is applied from the p-th power supply line to one source / drain region of the drive transistor. At least once, then
(B) A video signal is applied from the data line to the first node via the write transistor, and then
(C) In a state where a predetermined drive voltage is applied to the p-th power supply line, the write transistor is turned off, and the potential difference value between the first node and the second node is set via the drive transistor. A corresponding current is passed through the light emitting part, and then
(D) In a state where a predetermined drive voltage is applied to the p-th power supply line, a turn-off signal is applied to the first node, so that the drive transistor is turned off.
The process is done,
Steps (a) to (d) are performed repeatedly, and after the step (d) is completed in all display elements forming the region DA (p) and until the next step (a) is performed. Between,
(E) A predetermined second node initialization voltage is applied to the p-th power supply line, so that the potential difference between the anode electrode and the cathode electrode provided in the light emitting unit does not exceed the threshold voltage of the light emitting unit. In this state, pre-processing for changing the potential of the first node toward the potential obtained by adding the threshold voltage of the driving transistor to the potential of one of the source / drain regions of the driving transistor is performed. The auxiliary voltage having the same polarity as the driving voltage and having a larger absolute value is applied for a predetermined period, and then the driving voltage is applied to the p-th feeder line.
It is a display device.

  In the display device according to the present invention and the display device driving method according to the present invention, the display element group connected to a certain power supply line, and the certain power supply line adjacent to the display element group The brightness difference between the display element groups connected to different power supply lines can be reduced. Thereby, an image can be displayed satisfactorily.

FIG. 1 is a conceptual diagram of a display device according to the first embodiment. FIG. 2 is an equivalent circuit diagram of a display element including a driving circuit. FIG. 3 is a schematic partial cross-sectional view of a part of the display device. FIG. 4 is a schematic diagram of a timing chart in the method for driving the display device according to the first embodiment. FIG. 5 is a schematic diagram of a timing chart for driving the display element. FIG. 6 is a schematic diagram of a timing chart in the driving method of the display device according to the reference example. FIG. 7 is a schematic diagram of a timing chart for driving the display element. FIGS. 8A to 8F are diagrams schematically showing ON / OFF states and the like of each transistor included in the drive circuit of the display element. 9A to 9F are diagrams schematically illustrating the on / off state of each transistor included in the driver circuit of the display element, following FIG. 8F. FIGS. 10A and 10B are diagrams schematically illustrating the on / off state of each transistor included in the driver circuit of the display element, following FIG. 9F. FIG. 11 is a schematic diagram of a driving timing chart of the display device for explaining a waiting period before the preprocessing and a waiting period after the preprocessing in the display device driving method according to the reference example. FIG. 12A is a schematic circuit diagram for explaining a current flowing through the light-emitting portion in [period-TP (2) _0B ] shown in FIG. FIG. 12B is a schematic timing chart for explaining potential changes of the first node and the second node in the vicinity of [period-TP (2) _0B ] shown in FIG. FIG. 13A is a schematic circuit diagram for explaining a potential change of the second node in [period-TP (2) _0D ] illustrated in FIG. FIG. 13B is a schematic timing chart for explaining the potential change of the second node after [period-TP (2) _0D ] shown in FIG. FIG. 14 is a schematic diagram for explaining the light / dark pattern displayed in the display area in the driving method of the display device according to the reference example. FIG. 15 is a schematic diagram of a driving timing chart of the display device for explaining the waiting period before the preprocessing and the waiting period after the preprocessing in the display device driving method according to the embodiment. FIG. 16A is a schematic circuit diagram for explaining a potential change of the second node in [period-TP (2) _0D ] illustrated in FIG. FIG. 16B is a schematic circuit diagram for explaining a potential change of the second node in [period-TP (2) _0E ] illustrated in FIG. FIG. 16C is a schematic timing chart for explaining the potential change of the second node after [period-TP (2) _0D ] shown in FIG. FIG. 17 is a schematic diagram of a drive timing chart of the display device for explaining a configuration of a waiting period after preprocessing in the display device drive method according to the second embodiment. FIG. 18 is a schematic diagram of a driving timing chart of the display device for explaining the waiting period before the preprocessing and the waiting period after the preprocessing in the display device driving method according to the second embodiment. FIG. 19 is a diagram illustrating the relationship among row numbers in a region, scanning order in a region, luminance values, row numbers as a whole, and scanning order as a whole in a method for driving a display device according to a second embodiment. This is a table. FIG. 20 is a diagram illustrating the relationship among the row number in the region, the scanning order in the region, the luminance value, the row number as a whole, and the scanning order as a whole in the method for driving the display device according to the first embodiment. This is a table. FIG. 21 is a schematic diagram for explaining the light / dark pattern displayed in the display area in the method for driving the display device according to the second embodiment. FIG. 22 is an equivalent circuit diagram of a display element including a drive circuit. FIG. 23 is a conceptual diagram of a display device according to a conventional example.

Hereinafter, the present invention will be described based on examples with reference to the drawings. However, the present invention is not limited to the examples, and various numerical values and materials in the examples are examples. The description will be given in the following order.
1. 1. Detailed description of the display device according to the present invention and the driving method of the display device according to the present invention 2. Outline of display device used in embodiment Example 1
4). Example 2 (Modification of Example 1 and others)

<Detailed Description of the Display Device According to the Present Invention and the Driving Method of the Display Device According to the Present Invention>
In the display device according to the present invention and the method for driving the display device according to the present invention (hereinafter, these may be simply referred to as the present invention), the drive voltage has the same polarity as the absolute value. The value of the auxiliary voltage having a large value and the length of the predetermined period during which the auxiliary voltage is applied may basically be appropriately set according to the specifications of the display device.

  In the present invention, the display element group can be sequentially scanned from the first row to the Mth row. In this configuration, the display element group constituting the area DA (p) is scanned line-sequentially.

Alternatively, in the present invention, the value of the number of rows of the display element group forming the region DA (p) is expressed as NL (p), and the minimum value in NL (1) to NL (P) is expressed as _{NL_MIN} . Represent,
A row including the display element group of the i-th row (where i = 1, 2,..., NL (p)) in the region DA (p) is represented as a [p, i] -th row, and the region DA (p) The order in which each display element group belonging to is scanned is counted as the first to NL (p) th,
In the area DA (p), the maximum absolute value of the scanning order difference between adjacent display element groups is expressed as AD (p), and the maximum value in AD (1) to AD (P) is expressed as _{AD_MAX.} ,
The order in which the [p, NL (p)] rows are scanned in the area DA (p) (except when p = P) and the [p + 1, 1] rows are scanned in the area DA (p + 1). When the absolute value of the difference from the order is represented as BD (p) and the maximum value in BD (1) to BD (P-1) is represented as _{BD_MAX} ,
_{NL_MIN} is an integer greater than or _equal to 4,
The display element group constituting the areas DA (1) to DA (P) is the [p, k] -th row (where k = 1, 2,..., NL (p) −1) in the area DA (p). Is scanned so that a positive value and a negative value are mixed in a value obtained by subtracting the order in which the [p, k + 1] -th row is scanned from the order in which they are scanned.
_{AD_MAX} is _equal to a certain integer TN (where TN is a predetermined value satisfying 2 ≦ TN <( _{NL_MIN−} 1)), and _{BD_MAX} is less than or equal to TN. It can be set as the structure scanned in this way.

Here, in the present invention,
In a state where the display device is operated based on the video signal having a certain value, the luminance of the display element group constituting the area DA (p) changes in a certain direction in accordance with an increase in the scanning order in the area DA (p). And
The maximum luminance value in the N display element groups when a video signal having a constant value that causes the display device to display black is input is represented as L _MAX, and the display element is generated by one difference in scanning order. When the change amount of the luminance value of the group is expressed as ΔL and a certain coefficient is expressed as α (where α satisfies 0 <α <1 and one predetermined value in the display device),
The TN value may be set so as to satisfy TN · ΔL ≦ α · L _MAX .

For example, in order to set 1% of L _MAX as a guideline as the upper limit of the difference in luminance value between a display element group and an adjacent display element group, α = 1 × 10 ⁻² is satisfied and the above equation is satisfied. The value of TN may be set in.

In the present invention including the above-described preferable configuration, _{NL_MIN} is an integer of 5 or more, and 2 ≦ TN < _{NL_MIN} / 2 can be satisfied. For example, when DA (1) to DA (P) have the same number of rows and the luminance value changes linearly due to the difference in the scanning order of the display element group, the above configuration simply For a display device that performs line sequential scanning, the luminance difference between adjacent DA (p) and DA (p + 1) can be suppressed to about half at the maximum. Furthermore, in this case, _{NL_MIN} is an integer _equal to or greater than 20, and can be configured to satisfy 2 ≦ TN < _{NL_MIN} / 5. In this case, the luminance difference between adjacent DA (p) and DA (p + 1) can be suppressed to about 1/5 at the maximum.

  In the display device according to the present invention including the preferred configuration described above and the display device used in the driving method of the display device according to the present invention (hereinafter, these may be simply referred to as the display device of the present invention). The number of rows of the display element group forming the region DA (p), in other words, the value of NL (p) may be appropriately set according to the design and specifications of the display device. In the present invention, NL (p) can take a value of 4 or more. From the viewpoint of reducing the number of feeder lines, the value of NL (p) is preferably large. If the value of the pixel (pixel) of the display device is (640, 480), for example, the value of M described above is 480. When the display area is equally divided into 16, P = 16 and M = 480, so NL (p) = 480/16 = 30. Similarly, NL (p) = 20 when dividing into 24, NL (p) = 10 when dividing into 48, and NL (p) = 5 when dividing into 96. The value of NL (p) is convenient to be a constant value, but is not limited to this. When a surplus occurs in the result of M ÷ P, the surplus may be appropriately distributed. For example, the surplus can be allocated to NL (1) or NL (P).

  In the display device including P power supply lines, the power supply lines are shared in the display element group of NL (p) rows constituting the area DA (p). Therefore, since the number of feeder lines is reduced, the circuit scale of the power supply unit 100 can be reduced.

  As a light-emitting portion that constitutes the display element, a current-driven light-emitting portion that emits light when current is supplied can be widely used. Examples of the light emitting part include an organic electroluminescence light emitting part, an inorganic electroluminescence light emitting part, an LED light emitting part, and a semiconductor laser light emitting part. These light emitting portions can be configured using known materials and methods. From the viewpoint of configuring a flat display device for color display, among these, the configuration in which the light emitting section is composed of an organic electroluminescence light emitting section is preferable. The organic electroluminescence light emitting unit may be a so-called top emission type or a bottom emission type.

  Note that the conditions shown in the various expressions in this specification are satisfied not only when the expression is strictly mathematically established but also when the expression is substantially satisfied. In other words, regarding the formation of the formula, the presence of various variations that occur in the design or manufacture of the display element or the display device is allowed.

  In the driving method of the display device according to the present invention (hereinafter, sometimes simply referred to as the driving method of the present invention), the potential of the second node is driven from the potential of the first node by the threshold voltage canceling process. When a potential obtained by reducing the threshold voltage of the transistor is reached, the driving transistor is turned off. On the other hand, when the potential of the second node does not reach the potential obtained by subtracting the threshold voltage of the driving transistor from the potential of the first node, the potential difference between the first node and the second node is larger than the threshold voltage of the driving transistor. The driving transistor is not turned off. In the driving method of the present invention, it is not always necessary that the driving transistor is turned off as a result of the threshold voltage canceling process.

  In the driving method of the present invention, the writing process may be performed immediately after the threshold voltage canceling process is completed, or may be configured to be performed at intervals. The writing process may be performed in a state where a predetermined driving voltage is applied to one source / drain region of the driving transistor, or the predetermined driving voltage is applied to one source / drain region of the driving transistor. An embodiment may be performed in a state where no voltage is applied. In the former configuration, a mobility correction process for changing the potential of the other source / drain region of the drive transistor in accordance with the characteristics of the drive transistor is also performed in the write process.

  The display device may have a so-called monochrome display configuration or a color display configuration. For example, one pixel is composed of a plurality of subpixels. Specifically, one pixel is composed of three subpixels: a red light emitting subpixel, a green light emitting subpixel, and a blue light emitting subpixel. A display configuration can be adopted. Furthermore, a set of these three types of sub-pixels plus one or more types of sub-pixels (for example, a set of sub-pixels that emit white light to improve brightness, a color reproduction range) A set of sub-pixels that emit complementary colors for enlargement, a set of sub-pixels that emit yellow for expanding the color reproduction range, and yellow and cyan for expanding the color reproduction range It can also be composed of a set of subpixels).

  As values of pixels (pixels) of the display device, VGA (640, 480), S-VGA (800, 600), XGA (1024, 768), APRC (1152, 900), S-XGA (1280, 1024), U-XGA (1600, 1200), HD-TV (1920, 1080), Q-XGA (2048, 1536), (1920, 1035), (720, 480), (1280, 960), etc. Although some of the resolutions can be exemplified, the present invention is not limited to these values.

  In the display device, various wirings such as a scanning line, a data line, and a feeder line, and the configuration and structure of the light emitting unit can be a known configuration and structure. For example, when the light emitting part is composed of an organic electroluminescence light emitting part, it can be composed of an anode electrode, a hole transport layer, a light emitting layer, an electron transport layer, a cathode electrode, and the like. Various circuits such as a power supply unit, a scanning circuit, a signal output circuit, and a control circuit, which will be described later, can be configured using well-known circuit elements.

  As a transistor included in the driver circuit, an n-channel thin film transistor (TFT) can be given. The transistor constituting the driver circuit may be an enhancement type or a depletion type. In an n-channel transistor, an LDD structure (Lightly Doped Drain structure) may be formed. In some cases, the LDD structure may be formed asymmetrically. For example, since a large current flows through the driving transistor when the display element emits light, an LDD structure may be formed only on one source / drain region side that becomes the drain region side during light emission. For example, a p-channel thin film transistor may be used.

  The capacitor portion constituting the drive circuit can be composed of one electrode, the other electrode, and a dielectric layer (insulating layer) sandwiched between these electrodes. The above-described transistors and capacitors that constitute the drive circuit are formed in a certain plane (for example, formed on a support), and the light-emitting portion is a transistor that constitutes the drive circuit via an interlayer insulating layer, for example. And formed above the capacitor portion. In addition, the other source / drain region of the driving transistor is connected to one end of the light emitting unit (an anode electrode or the like provided in the light emitting unit) via, for example, a contact hole. In addition, the structure which formed the transistor in the semiconductor substrate etc. may be sufficient.

  Hereinafter, the present invention will be described based on examples with reference to the drawings. Prior to that, an outline of a display device used in the examples will be described.

<Overview of Display Device Used in Examples>
A display device suitable for use in the embodiment is a display device including a plurality of pixels. One pixel is composed of a plurality of sub-pixels (in the embodiment, three sub-pixels are a red light-emitting sub pixel, a green light-emitting sub pixel, and a blue light-emitting sub pixel). The current-driven light emitting unit is composed of an organic electroluminescence light emitting unit. Each subpixel includes a display element 10 having a structure in which a drive circuit 11 and a light emitting unit (light emitting unit ELP) connected to the drive circuit 11 are stacked.

  A conceptual diagram of a display device used in the embodiment is shown in FIG.

  FIG. 2 shows a drive circuit (sometimes referred to as a 2Tr / 1C drive circuit) basically composed of 2 transistors / 1 capacitor.

  As shown in FIG. 1, the display device used in the embodiment has a two-dimensional matrix shape of N in the first direction, M in the second direction different from the first direction, and a total of N × M. The display elements 10 are arranged. One row of the display elements 10 arranged in the first direction constitutes one display element group, and P display area portions formed from a plurality of display element groups arranged adjacent to each other (note that P Is an integer of 2 or more), and the display area EA is formed by P display area portions arranged in the second direction. A portion of the p-th display area (where p = 1, 2,..., P) is represented as an area DA (p). The display element 10 is scanned in units of display element groups for each display area. In FIG. 1, three rows of display elements 10 are shown, but this is merely an example.

  The display device further includes M scanning lines SCL extending in the first direction, N data lines DTL extending in the second direction, and P power supply lines PS1 extending in the first direction. . The power supply line PS1 is connected to the power supply unit 100. The data line DTL is connected to the signal output circuit 102. The scanning line SCL is connected to the scanning circuit 101.

As shown in FIG. 2, the display element 10 includes a light emitting unit ELP and a drive circuit 11 for driving the light emitting unit ELP by supplying a current. The drive circuit 11 includes a write transistor TR _W , a drive transistor TR _D , and a capacitor C ₁ . In the embodiment, the light emitting part ELP is composed of an organic electroluminescence light emitting part.

  The light emitting unit ELP has a well-known configuration and structure including, for example, an anode electrode, a hole transport layer, a light emitting layer, an electron transport layer, a cathode electrode, and the like. The configurations and structures of the scanning circuit 101, the signal output circuit 102, the scanning line SCL, the data line DTL, and the power supply unit 100 can be well-known configurations and structures. The configuration of the control circuit 103 will be described later.

The p-th display area (where p = 1, 2,..., P) is expressed as area DA (p), and the value of the number of rows in the display element group forming area DA (p) is expressed as NL ( p), the maximum value of NL (p) is represented as _{NL_MAX,} and the display element group in the i-th row (where i = 1, 2,..., NL (p)) in the area DA (p) is represented. The including row is represented as the [p, i] -th row. Although NL (p) = 4 in FIG. 1, this is merely an example.

  In Example 1 to be described later, the display element group is sequentially scanned from the first row to the M-th row. In the first embodiment, the display element group constituting the area DA (p) is scanned in a line sequential manner. On the other hand, in Example 2 to be described later, the order in which the display element group is scanned in the area DA (p) is different from that in Example 1. Details will be described later.

The m (where, m = 1, 2 · · ·, M), the n-th column (where, n = 1,2 ···, N) in the display device 10, in the driving transistor TR _D The other source / drain region is connected to one end of the light emitting unit ELP (in the embodiment, an anode electrode provided in the light emitting unit ELP) and connected to one electrode of the capacitor unit C _1. And constitutes the second node ND ₂ . The gate electrode is connected to the other of the source / drain regions of the write transistor TR _W, and is connected to the other electrode of the capacitor portion C _1, which forms a first node ND _1. In the write transistor TR _W, one of the source / drain region is connected to the n th data line DTL _n. The gate electrode is connected to the mth scanning line SCL. In the display element group forming the region DA (p), one source / drain region of the drive transistor TR _D constituting the display element 10 is connected to the p-th feeder line PS1 _p .

  Here, the relationship between the “m-th row in the display device” and the “[p, i] -th row in the area DA (p)” will be described. The “[1,1] th row in the area DA (1)” is “a first row in the display device”. When NL (p) = 4, “the [p, i] th row in the area DA (p)” is “the (4 · (p−1) + i) row in the display device”. is there. For example, “the [2,1] th row in the area DA (2)” is “the fifth row in the display device”.

In the example shown in FIG. 1, the first scanning line SCL ₁ is also expressed as the [1,1] -th scanning line SCL _[1,1] in the area DA (1). The former notation is mainly used for explaining the operation of the entire display device, and the latter notation is mainly used for explaining the operation in each area DA (p). The same applies to other components.

The drive transistor TR _D is composed of an n-channel TFT having a source / drain region, a channel formation region, and a gate electrode. The write transistor TR _{W is} also composed of an n-channel TFT having a source / drain region, a channel formation region, and a gate electrode. Note that the write transistor TR _W may be composed of a p-channel TFT. The drive circuit 11 may further include another transistor.

  As shown in FIG. 2, the other end of the light emitting unit ELP (in the embodiment, the cathode electrode provided in the light emitting unit ELP) is connected to the second power supply line PS2.

  More specifically, in the display element 10 constituting the display device shown in FIG. 1, the cathode electrode provided in the light emitting unit ELP is connected to the common second power supply line PS2. For convenience, the illustration of the second feeder line PS2 is omitted in FIG.

FIG. 3 is a schematic partial sectional view of a part of the display device. The transistors TR _D and TR _W and the capacitor part C ₁ constituting the drive circuit 11 are formed on the support 20, and the light emitting part ELP is, for example, the transistor TR _D constituting the drive circuit 11 via the interlayer insulating layer 40. , TR _W and the capacitor C ₁ . The other source / drain region of the driving transistor TR _D is connected to an anode electrode provided in the light emitting unit ELP through a contact hole. In FIG. 3, only the drive transistor TR _D is shown. Other transistors are hidden from view.

More specifically, the drive transistor TR _D includes a gate electrode 31, a gate insulating layer 32, source / drain regions 35 and 35 provided in the semiconductor layer 33, and a semiconductor layer between the source / drain regions 35 and 35. The portion 33 is constituted by the corresponding channel forming region 34. On the other hand, the capacitor C ₁ includes the other electrode 36, a dielectric layer composed of the extending portion of the gate insulating layer 32, and one electrode 37 (corresponding to the second node ND ₂ ). The gate electrode 31, a part of the gate insulating layer 32, and the other electrode 36 constituting the capacitor portion C ₁ are formed on the support 20. One source / drain region 35 of the driving transistor TR _D is connected to the wiring 38, and the other source / drain region 35 is connected to one electrode 37. The drive transistor TR _{D, the} capacitor C _{1, and the} like are covered with an interlayer insulating layer 40, and an anode electrode 51, a hole transport layer, a light emitting layer, an electron transport layer, and a cathode electrode 53 are formed on the interlayer insulating layer 40. A light emitting unit ELP is provided. In the drawing, the hole transport layer, the light emitting layer, and the electron transport layer are represented by one layer 52. A second interlayer insulating layer 54 is provided on the portion of the interlayer insulating layer 40 where the light emitting part ELP is not provided, and the transparent substrate 21 is disposed on the second interlayer insulating layer 54 and the cathode electrode 53. The light emitted from the light emitting layer passes through the substrate 21 and is emitted to the outside. One electrode 37 (second node ND ₂ ) and the anode electrode 51 are connected to each other through a contact hole provided in the interlayer insulating layer 40. Further, the cathode electrode 53 is connected to the wiring 39 provided on the extending portion of the gate insulating layer 32 through the contact holes 56 and 55 provided in the second interlayer insulating layer 54 and the interlayer insulating layer 40. Yes.

A method for manufacturing the display device shown in FIG. First, on the support 20, various wirings such as scanning lines SCL, the electrodes constituting the capacitance section C _1, the transistor comprising a semiconductor layer, an interlayer insulating layer, a contact hole or the like, is suitably formed by a known method. Next, film formation and patterning are performed by a known method to form light emitting portions ELP arranged in a matrix. Then, after the support 20 and the substrate 21 that have undergone the above-described steps are made to face each other and the periphery is sealed, a connection with an external circuit is performed, and a display device can be obtained.

  The display device in each embodiment is a color display device including a plurality of display elements 10 (for example, N × M = 1920 × 480). Each display element 10 constitutes a sub-pixel, and one pixel is constituted by a group of a plurality of sub-pixels, and is in a two-dimensional matrix form in a first direction and a second direction different from the first direction. Pixels are arranged in the. One pixel is composed of three types of sub-pixels arranged in the extending direction of the scanning line SCL: a red light-emitting subpixel that emits red light, a green light-emitting subpixel that emits green light, and a blue light-emitting subpixel that emits blue light. Has been.

  The display device includes (N / 3) × M pixels arranged in a two-dimensional matrix. The frame frequency (frame rate) is expressed as FR (Hertz). The display elements 10 constituting each of (N / 3) pixels (N sub-pixels) arranged in the m-th row are driven simultaneously. In other words, in each display element 10 constituting one row, the light emission / non-light emission timing is controlled in units of rows to which they belong. The process of writing a video signal for each pixel constituting one row may be a process of writing a video signal for all the pixels simultaneously (hereinafter, simply referred to as a simultaneous writing process), A process of sequentially writing video signals for each pixel (hereinafter sometimes simply referred to as a sequential writing process) may be used. Which writing process is used may be appropriately selected according to the configuration of the display device.

For convenience of explanation, a period allocated for scanning the display elements 10 in each row is represented as a horizontal scanning period. In an embodiment described later, in each horizontal scanning period, a period during which a first node initialization voltage (V _Ofs described later) is applied from the signal output circuit 102 to the data line DTL (hereinafter referred to as an initialization period), video There are a period (hereinafter referred to as a video signal period) for applying a signal (V _Sig described later) and a period (hereinafter referred to as an extinguished signal period) for applying a light extinction signal (V _Ers described later). In the embodiment, a voltage and a signal are applied to the data line DTL in the order of the first node initialization voltage, the video signal, and the turn-off signal in each horizontal scanning period, but the present invention is not limited to this. Voltages and signals may be applied in a different order.

  Here, in principle, the structure and operation of the display element 10 located in the [p, i] -th row and the n-th column in the p-th region DA (p) will be described. The display element 10 is hereinafter referred to as the [p, i] -th row and n-th column display element 10 or the [p, i] -th row and n-th column sub-pixel. Various processes (threshold voltage canceling process, writing process, and mobility correcting process described later) are performed until the horizontal scanning period assigned to the display element 10 in the [p, i] -th row ends. Note that the writing process and the mobility correction process are performed within a horizontal scanning period assigned to the display element 10 in the [p, i] -th row. On the other hand, the threshold voltage canceling process and the preprocessing associated therewith can be performed in advance.

  Then, after all the various processes described above are completed, the light emitting units ELP constituting the display elements 10 arranged in the [p, i] -th row are caused to emit light. The light emitting state of the light emitting unit ELP constituting each display element 10 is continued until “m ′” horizontal scanning periods have elapsed. Here, the value of “m ′” is set based on the specifications of the display device. Then, until the writing process and the mobility correction process are completed within the horizontal scanning period in the next display frame, the light emitting units ELP constituting the display elements 10 arranged in the [p, i] -th row are in principle The non-light emitting state is maintained. By providing the above-described non-light emitting period (hereinafter, simply referred to as a non-light emitting period), the afterimage blur caused by the active matrix driving can be reduced, and the moving image quality can be further improved. However, the light emission state / non-light emission state of each sub-pixel (display element 10) is not limited to the state described above. The time length of the horizontal scanning period is a time length of less than (1 / FR) × (1 / M) seconds. When “m ′” horizontal scanning periods elapse from the horizontal scanning period of each display element 10 arranged in the [p, i] th row reaches the next display frame, the excess horizontal The scanning period is processed in the next display frame.

  In two source / drain regions of one transistor, the term “one source / drain region” may be used to mean a source / drain region connected to the power supply side. Further, the transistor being in an on state means a state in which a channel is formed between the source / drain regions. It does not matter whether current flows from one source / drain region of the transistor to the other source / drain region. On the other hand, the transistor being in an off state means a state in which no channel is formed between the source / drain regions. In addition, the source / drain region of a certain transistor is connected to the source / drain region of another transistor means that the source / drain region of a certain transistor and the source / drain region of another transistor occupy the same region. The form is included. Furthermore, the source / drain regions can be composed not only of conductive materials such as polysilicon or amorphous silicon containing impurities, but also metals, alloys, conductive particles, their laminated structures, organic materials (conductive Polymer). In the timing chart used in the following description, the length of the horizontal axis (time length) indicating each period is a schematic one and does not indicate the ratio of the time length of each period. The same applies to the vertical axis. The waveform shape in the timing chart is also schematic.

  Hereinafter, based on an example, a display device concerning the present invention and a drive method of a display device are explained.

  Example 1 relates to a display device and a driving method of the display device according to the present invention.

As shown in FIG. 2, the drive circuit 11 constituting the display element 10 is composed of two transistors, a write transistor TR _W and a drive transistor TR _D , and is further composed of one capacitor C ₁ ( 2Tr / 1C driving circuit).

[Drive transistor TR _D ]
One source / drain region of the driving transistor TR _D is connected to the p-th feeder line PS1 _p . A predetermined voltage is applied to one source / drain region of the drive transistor TR _D from the p-th feeder line PS1 _p based on the operation of the power supply unit 100. Specifically, the drive voltage V _CC-H , the second node initialization voltage V _CC-L , and the auxiliary voltage V _CC-FH are supplied from the power supply unit 100. These voltages will be described later. On the other hand, the other source / drain region of the drive transistor TR _D is
[1] An anode electrode of the light emitting unit ELP, and
[2] One electrode of the capacitor C ₁
To the second node ND ₂ . The gate electrode of the drive transistor TR _D is
[1] The other source / drain region of the write transistor TR _W , and
[2] The other electrode of the capacitor C ₁
And constitutes the first node ND ₁ .

Here, in the light emitting state of the display element 10, the driving transistor TR _D is set to a voltage so as to operate in the saturation region, and is driven so that the drain current I _ds flows according to the following formula (1). In the light emission state of the display device 10, one source / drain region of the driving transistor TR _D works as a drain region, the other source / drain region acts as a source region. For convenience of description, in the following description, one source / drain region of the drive transistor TR _D may be simply referred to as a drain region, and the other source / drain region may be simply referred to as a source region. still,
μ: effective mobility L: channel length W: channel width V _gs : potential difference between gate electrode and source region V _th : threshold voltage C _ox : (relative permittivity of gate insulating layer) x (vacuum dielectric) Rate) / (thickness of gate insulating layer)
k≡ (1/2) ・ (W / L) ・ C _ox
And

I _ds = k · μ · (V _gs −V _th ) ² (1)

When the drain current I _ds flows through the light emitting part ELP of the display element 10, the light emitting part ELP of the display element 10 emits light. Furthermore, the light emission state (luminance) in the light emitting portion ELP of the display element 10 is controlled by the magnitude of the drain current I _ds .

[Write transistor TR _W ]
The other source / drain region of the write transistor TR _W is connected to the gate electrode of the drive transistor TR _D as described above. On the other hand, one source / drain region of the write transistor TR _W is connected to the _nth data line DTL _n . A predetermined voltage is applied to one source / drain region of the write transistor TR _W from the _nth data line DTL _n based on the operation of the signal output circuit 102. Specifically, the signal output circuit 102 supplies the first node initialization voltage V _Ofs , the video signal (drive signal, luminance signal) V _Sig for controlling the luminance in the light emitting unit ELP, and the extinction signal V _Ers. Is done.

ON / OFF operation of the writing transistor TR _W is connected to the gate electrode of the writing transistor TR _W, the signal from the i-th scanning line SCL _{[p, i]} in the area DA (p), specifically, Controlled by a signal from the scanning circuit 101.

[Light emitting part ELP]
The anode electrode of the luminescence part ELP, as described above, is connected to the source area of the driving transistor TR _D. On the other hand, the cathode electrode of the light emitting unit ELP is connected to the second feeder line PS2. A predetermined voltage V _Cat described later is applied from the second feeder line PS2 to the cathode electrode of the light emitting unit ELP. The capacity of the light emitting part ELP is represented by the symbol C _EL . Further, the threshold voltage required for light emission of the light emitting unit ELP is set to V _th-EL . That is, when a voltage equal to or higher than V _th-EL is applied between the anode electrode and the cathode electrode of the light emitting unit ELP, the light emitting unit ELP emits light.

  In the following description, the voltage or potential value is as follows. However, this is merely a value for explanation, and is not limited to these values.

V _Sig : Video signal for controlling the luminance in the light emitting part ELP 2 V (black display) to 8 V (white display)
V _CC-H : Driving voltage for flowing current to the light emitting part ELP ... 20 volts V _CC-L : Second node initialization voltage ... -14 volts V _CC-FH : Same polarity as the driving voltage auxiliary voltage ... 30 more large absolute value Te volts V _Ofs: driving transistor TR _D first node initialization voltage for initializing the electric potential (the potential of the first node ND ₁₎ of the gate electrode of ... 1 Volt V _Ers : Light-off signal for turning off the light emitting part ELP ... 3 volts V _th : Threshold voltage of the driving transistor TR _D ... 3 volts V _Cat : Voltage applied to the cathode electrode of the light emitting part ELP・ 0 volt V _th-EL : threshold voltage of light emitting part ELP ・ ・ ・ 4 volt

In the first embodiment, the display element group is sequentially scanned from the first row to the Mth row. The display element group constituting the area DA (p) is scanned line-sequentially. FIG. 4 is a schematic diagram of a timing chart in the driving method of the first embodiment. For convenience of comparison with FIG. 1, FIG. 4 shows a timing chart with NL (p) = 4, but this is only an example. FIG. 5 is a diagram schematically showing a driving timing chart of the display element 10 in the [p, i] -th row and the n-th column in the p-th region DA (p). In the first embodiment, in [period-TP (2) _0D ] shown in FIG. 5, the auxiliary voltage V _CC-FH having the same polarity as the drive voltage V _CC-H and a larger absolute value is supplied to the feeder line PSP. applied to _p .

First, in order to help the understanding of the invention, in the display device shown in FIG. 1, the driving method in which the application of the auxiliary voltage V _CC-FH is not performed. It may be abbreviated as an example driving method). FIG. 6 is a schematic diagram of a timing chart in the driving method of the reference example.

A timing chart for driving the display element 10 in the [p, i] -th row and the n-th column in the p-th region DA (p) in the reference example is schematically shown in FIG. The on / off state and the like are schematically shown in FIGS. 8A to 8F, FIGS. 9A to 9F, and FIGS. 10A and 10B. Hereinafter, the operation of the display element 10 will be described. The operation of the display element 10 is basically the same between the driving method of the reference example and the driving method of each embodiment except that the auxiliary voltage V _CC-FH is applied to the feeder line PSP _p. Is the same.

In the driving method of the display device according to each example and reference example,
(A) In a state where a predetermined drive voltage V _CC-H is applied from the p-th feeder line PS1 _p to one source / drain region of the drive transistor TR _D , a predetermined first node initial state is applied to the first node ND _1. writing voltage is applied to V _Ofs, than Te, the first node ND ₁ the threshold voltage canceling process of changing the second node ND ₂ in potential towards the potential obtained by subtracting the threshold voltage V _th of the driving transistor TR _D from the potential At least once, then
(B) A write process is performed in which the video signal V _Sig is applied from the data line DTL to the first node ND ₁ via the write transistor TR _W , and then
(C) In a state where a predetermined drive voltage V _CC-H is applied to the p-th power supply line PS1 _p , the write transistor TR _W is turned off to make the first node ND ₁ floating and the drive transistor TR A current corresponding to the value of the potential difference between the first node ND ₁ and the second node ND ₂ is passed through the light emitting unit ELP via _D , and then
(D) With the predetermined drive voltage V _CC-H applied to the p-th feed line PS1 _p , the extinction signal V _Ers is applied to the first node ND ₁ , thereby turning off the drive transistor TR _D And
It has a process,
Steps (a) to (d) are repeated, and after the step (d) is completed in all the display elements 10 that form the region DA (p) until the next step (a) is performed. Between,
(E) A predetermined second node initialization voltage V _CC-L is applied to the p-th feeder line PS1 _{p, so} that the potential difference between the anode electrode and the cathode electrode provided in the light-emitting unit ELP is emitted. The first node ND ₁ toward the potential obtained by adding the threshold voltage V _th of the drive transistor TR _D to the potential of one source / drain region of the drive transistor TR _{D in} a state where the threshold voltage V _th-EL of the part ELP is not exceeded. A pre-process for changing the potential of is performed.

  For convenience of explanation, the operation shown in FIG. 7 will be described as performing a threshold voltage canceling process described later over three horizontal scanning periods, but is not limited thereto.

[Period -TP (2) _-1 ] (see FIGS. 7 and 8A)
This [Period-TP (2) ₋₁ ] is a period in which the display element 10 is in a light emitting state after completion of various previous processes in the previous display frame, and is a period in which the above-described step (c) is performed. is there. That is, the drain current I ′ _ds based on the formula (5 ′) described later flows in the light emitting unit ELP in the display element 10, and the display constituting the [p, i] -th row and the n-th column sub-pixel. The luminance of the element 10 is a value corresponding to the drain current I ′ _ds . Here, the write transistor TR _W is in an off state, and the drive transistor TR _D is in an on state. The light emitting state of the display element 10 in the [p, i] -th row and the n-th column is the horizontal scanning period next to the horizontal scanning period assigned to the display element 10 in a certain [p ′, i ′]-th row. Continue halfway. Note that the values of “p ′” and “i ′” are determined by the value of “m ′” described above.

Corresponding to each horizontal scanning period, the first node initialization voltage V _Ofs , the video signal V _Sig and the turn-off signal V _Ers are applied to the data line DTL _n . However, since the write transistor TR _W is in an off state, even _if the potential (voltage) of the data line DTL _n changes in [period -TP (2) ₋₁ ], the first node ND ₁ and the second node ND ₂ (In reality, potential changes due to electrostatic coupling such as parasitic capacitance may occur, but these can usually be ignored.) The same applies to [Period-TP (2) _0B ] to [Period-TP (2) _0D ] to be described later.

[Period-TP (2) _0A ] to [Period-TP (2) _6A ] shown in FIG. 7 are from the end of the light emission state after completion of the previous various processes to immediately before the next writing process is performed. Is the operation period. In [Period -TP (2) _0A ] to [Period -TP (2) _6B ], the display element 10 is in a non-light emitting state in principle. As shown in FIG. 7, in addition to [Period-TP (2) ₅ ] and [Period-TP (2) _6A ], [Period-TP (2) _6B ] and [Period-TP (2) _6C ] It is included in the horizontal scanning period H _{[p, i]} assigned to the display elements 10 in the [p, i] -th row.

Hereinafter, an operation in each period of [Period-TP (2) _0A ] to [Period-TP (2) ₇ ] will be described.

[Period -TP (2) _0A ] (see FIGS. 7 and 8B)
This [period-TP (2) _0A ] is a turn-off signal period in the horizontal scanning period assigned to the display elements 10 in the [p ′, i ′ + 1] th row, for example, and the above-described step (d) is performed. It is a period. At the beginning of this period, the write transistor TR _W is turned on based on the operation of the scanning circuit 101. As a result, in a state where a predetermined drive voltage V _CC-H is applied to the p-th power supply line PS1 _p , the extinction signal V _Ers is applied to the first node ND ₁ , thereby turning off the drive transistor TR _D And

In the light emitting state, the drive voltage V _CC-H (20 volts) is applied to one source / drain region of the drive transistor TR _D , and the potential of the second node ND ₂ is V _th-EL (4 volts). ) At a potential exceeding. Accordingly, the drive transistor TR _D is turned off by applying the extinction signal V _Ers (3 volts) to the first node ND ₁ . The light emitting unit ELP is turned off, and the potential of the second node ND ₂ drops to (V _Cat + V _th−EL ). Assuming ideal operation, the potential of the first node ND ₁ is 3 volts and the potential of the second node ND ₂ is 4 volts.

Then, at the end of this [period-TP (2) _0A ], the writing transistor TR _W is turned off based on the operation of the scanning circuit 101.

[Period -TP (2) _0B ] (see FIGS. 7 and 8C)
This period is a period of the voltage of the feeder line PS1 _p from the driving voltage V _CC-H immediately before switching to the second node initialization voltage V _CC-L. The drive transistor TR _D maintains an off state. The potentials of the first node ND ₁ and the second node -ND ₂ also maintain the previous state.

[Period -TP (2) _0C ] (see FIGS. 7 and _8D )
At the beginning of this period, the voltage of the feed line PS1 _p is switched from the drive voltage V _CC-H to the second node initialization voltage V _CC-L and the state is maintained until just before [period-TP (2) _0D ] described later. maintain. In this period, the above-described step (e), that is, pre-processing is performed. A second node initialization voltage V _CC-L (−14 volts) is applied to one source / drain region of the drive transistor TR _D. Therefore, the potential of one source / drain region of the drive transistor TR _D is lower than the potential (4 volts) of the second node ND ₂ . Thus, the relationship between the source region and the drain region of the driving transistor TR _D is inverted, one of the source / drain regions of the driving transistor TR _D becomes the source region, the other source / drain region is the drain region. Since the potential of the first node ND ₁ is 3 volts, the driving transistor TR _D is turned on. Therefore, the potential of the second node ND ₂ decreases, and accordingly, the potential of the first node ND ₁ also decreases. However, when the potential of the first node ND ₁ decreases and reaches (V _CC−L + V _th ), the drive transistor TR _D is turned off. The potential difference between the first node ND ₁ and the second node ND ₂ basically maintains the previous state.

Therefore, if it operates ideally, the potential of the first node ND ₁ is −11 volts and the potential of the second node ND ₂ is −10 volts during this period. The drive transistor TR _D is in an off state.

[Period -TP (2) _0D ] (see FIGS. 7 and _8E )
At the beginning of this period, the voltage of the feeder line PS1 _p is switched from the second node initialization voltage V _CC-L to the drive voltage V _CC-H . The relationship between the source region and the drain region of the driving transistor TR _D is inverted, the other source / drain region is a source region of the drive transistor TR _D, is one of the source / drain region becomes the drain region. However, since the potential difference between the first node ND ₁ and the second node ND ₂ is −1 volt, the driving transistor TR _D maintains the off state.

Therefore, if it operates ideally, the potential of the first node ND _{1 and} the potential of the second node ND ₂ maintain the previous state. The potential of the first node ND ₁ is −11 volts, and the potential of the second node ND ₂ is −10 volts.

Next, the above-described step (a), that is, the threshold voltage canceling process is performed over [Period-TP (2) ₁ ] to [Period-TP (2) ₅ ]. Specifically, the first threshold voltage canceling process is performed in [Period-TP (2) ₁ ], the second threshold voltage canceling process is performed in [Period-TP (2) ₃ ], and [Period- In TP (2) ₅ ], the third threshold voltage canceling process is performed.

[Period-TP (2) ₁ ] and [Period-TP (2) ₂ ] are periods included in the horizontal scanning period two times before the horizontal scanning period H _{[p, i]} . [Period-TP (2) ₁ ] corresponds to the initialization period, and [Period-TP (2) ₂ ] corresponds to the video signal period and the turn-off signal period. [Period-TP (2) ₃ ] and [Period-TP (2) ₄ ] are periods included in the horizontal scanning period immediately before the horizontal scanning period H _{[p, i]} . [Period-TP (2) ₃ ] corresponds to the initialization period, and [Period-TP (2) ₄ ] corresponds to the video signal period and the turn-off signal period.

[Period -TP (2) ₁ ] (see FIGS. 7 and 8D)
At the beginning of this period, based on the operation of the scanning circuit 101, the write transistor TR _W is turned on, and a predetermined first node initialization voltage V _Ofs (1 is applied to the first node ND ₁ via the write transistor TR _W. Voltage). The driving transistor TR _D is turned on and the potential of the first node ND ₁ does not change (V _Ofs = 1 volt is maintained), but the threshold voltage V _th of the driving transistor TR _D is subtracted from the potential of the first node ND ₁ . The potential of the second node ND ₂ changes toward the potential. That is, the potential of the second node ND ₂ increases.

If this [period-TP (2) ₁ ] is sufficiently long, the potential difference between the gate electrode of the drive transistor TR _D and the other source / drain region reaches V _th , and the drive transistor TR _D is turned off. That is, the potential of the second node ND ₂ approaches (V _Ofs -V _th), and finally becomes (V _Ofs -V _th). However, in the example shown in FIG. 7, the length of [Period -TP (2) ₁ ] is insufficient to change the potential of the second node ND ₂ sufficiently, and [Period -TP (2) ₁ ], the potential of the second node ND ₂ reaches a certain potential V ₁ that satisfies the relationship V _CC-L <V ₁ <(V _Ofs −V _th ).

[Period -TP (2) ₂ ] (see FIGS. 7 and 9A)
In [Period -TP (2) ₂ ], the voltage of the data line DTL _n is switched from the first node initialization voltage V _Ofs to the video signal V _Sig and the turn-off signal V _Ers . In order to prevent the video signal V _Sig and the extinction signal V _{Ers from} being applied to the first node ND ₁ , the write transistor TR _W is turned off based on the operation of the scanning circuit 101 at the beginning of this [period-TP (2) ₂ ]. And As a result, the first node ND ₁ is in a floating state.

Since the drive voltage V _CC-H is applied from the power supply unit 100 to one source / drain region of the drive transistor TR _D , the potential of the second node ND ₂ rises from the potential V ₁ to a certain potential V ₂ . . On the other hand, since the gate electrode of the driving transistor TR _D is in a floating state and the capacitance portion C ₁ exists, a bootstrap operation occurs on the gate electrode of the driving transistor TR _D. Therefore, the potential of the first node ND ₁ rises as the potential of the second node ND ₂ changes.

[Period -TP (2) ₃ ] (see FIGS. 7 and 9B)
At the beginning of [Period -TP (2) ₃ ], the voltage of the data line DTL _n is switched to the first node initialization voltage V _Ofs . At the beginning of [Period -TP (2) ₃ ], the writing transistor TR _W is turned on based on the operation of the scanning circuit 101. As a result, the potential of the first node ND ₁ becomes V _Ofs . Since one of the source / drain regions to the drive voltage V _CC-H of the drive transistor TR _D from the power supply unit 100 is applied, the potential obtained by subtracting the threshold voltage V _th of the driving transistor TR _D from the potential of the first node ND ₁ The potential of the second node ND ₂ changes toward. That is, the potential of the second node ND ₂ rises from the potential V ₂ to a certain potential V ₃ .

[Period -TP (2) ₄ ] (see FIGS. 7 and 9C)
In [Period -TP (2) ₄ ], the voltage of the data line DTL _n is switched from the first node initialization voltage V _Ofs to the video signal V _Sig and the turn-off signal V _Ers . In order to prevent the video signal V _Sig and the extinction signal V _{Ers from} being applied to the first node ND ₁ , the writing transistor TR _W is turned off based on the operation of the scanning circuit 101 at the beginning of this [period-TP (2) ₄ ]. And As a result, the first node ND ₁ is in a floating state.

Since the drive voltage V _CC-H is applied from the power supply unit 100 to one source / drain region of the drive transistor TR _D , the potential of the second node ND ₂ rises from the potential V ₃ to a certain potential V ₄ . . On the other hand, since the gate electrode of the driving transistor TR _D is in a floating state and the capacitance portion C ₁ exists, a bootstrap operation occurs on the gate electrode of the driving transistor TR _D. Therefore, the potential of the first node ND ₁ rises as the potential of the second node ND ₂ changes.

Given the operation of [period -TP (2) _5], at the beginning of [Period -TP (2) _5], the second node ND ₂ in the potential V ₄ is to be lower than (V _Ofs -V _th) Necessary. The length from the start of [Period -TP (2) ₁ ] to the start of [Period -TP (2) ₅ ] is determined so as to satisfy the condition of V ₄ <(V _Ofs−L −V _th ). Yes.

[Period -TP (2) ₅ ] (see FIGS. 7 and 9D)
The operation of [Period-TP (2) ₅ ] is basically the same as described in [Period-TP (2) ₃ ]. At the beginning of [Period -TP (2) ₅ ], the voltage of the data line DTL _n is switched to the first node initialization voltage V _Ofs . At the beginning of this [period-TP (2) ₅ ], the write transistor TR _W is turned on based on the operation of the scanning circuit 101.

The first node ND ₁ is in a state where the first node initialization voltage V _Ofs is applied from the data line DTL _n via the write transistor TR _W. Further, since the drive voltage V _CC-H is applied from the power supply unit 100 to one source / drain region of the drive transistor TR _D , the second node is the same as described in [Period -TP (2) ₃ ]. The potential of ND ₂ changes toward a potential obtained by subtracting the threshold voltage V _th of the drive transistor TR _D from the potential of the first node ND ₁ . When the potential difference between the gate electrode of the driving transistor TR _D and the other source / drain region reaches V _th , the driving transistor TR _D is turned off. In this state, the potential of the second node ND ₂ is approximately (V _Ofs −V _th ). Here, if the following formula (2) is guaranteed, in other words, if the potential is selected and determined so as to satisfy the formula (2), the light emitting unit ELP does not emit light.

(V _Ofs −V _th ) <(V _th−EL + V _Cat ) (2)

In this [period-TP (2) ₅ ], the potential of the second node ND ₂ is ideally (V _Ofs −V _th ). That is, the threshold voltage V _th of the driving transistor TR _D, and the potential of the gate electrode of the driving transistor TR _D and the voltage V _Ofs for initializing the potential of the second node ND ₂ is determined. And it is unrelated to the threshold voltage V _{th-EL of} the light emitting unit ELP.

[Period -TP (2) _6A ] (see FIGS. 7 and 9E)
At the beginning of [Period -TP (2) _6A ], the writing transistor TR _W is turned off based on the operation of the scanning circuit 101. In addition, the voltage applied to the data line DTL _n is switched to the video signal V _Sig (video signal period). If the drive transistor TR _D has reached the OFF state in the threshold voltage canceling process, the potentials of the first node ND ₁ and the second node ND ₂ do not change substantially. In the threshold voltage canceling process performed in [Period-TP (2) ₅ ], when the drive transistor TR _D has not reached the OFF state, a bootstrap operation occurs in [Period-TP (2) _6A ], and the first node The potentials at ND ₁ and the second node ND ₂ slightly increase.

[Period -TP (2) _6B ] (see FIGS. 7 and 9F)
Within this period, the above step (b), that is, the writing process is performed. Based on the operation of the scanning circuit 101, the writing transistor TR _W is turned on. Then, the video signal V _Sig is applied from the data line DTL _n to the first node ND ₁ via the write transistor TR _W. As a result, the potential of the first node ND ₁ rises to V _Sig . The drive transistor TR _D is in an on state. In some cases, the writing transistor TR _W can be kept on in [Period -TP (2) _6A ]. In this configuration, the writing process is started immediately when the voltage of the data line DTL _n is switched from the first node initialization voltage V _Ofs to the video signal V _Sig in [Period -TP (2) _6A ].

Here, the value of the capacitor C ₁ is set as a value c _1, and the value of the capacitor C _EL of the light emitting unit ELP is set as a value c _EL . A capacitance value between the gate electrode of the driving transistor TR _D and the other source / drain region is defined as c _gs . If the capacitance value between the first node ND ₁ and the second node ND ₂ is represented by the symbol c _A , c _A = c ₁ + c _gs . In addition, if a capacitance value between the second node ND ₂ and the second power supply line PS2 is represented by a symbol c _B , c _B = c _EL . Note that both ends of the light emitting section ELP, although additional capacity portion may have a configuration that is connected in parallel, in which case, further capacitance value of the additional capacitance portion to c _B is added.

When the potential of the gate electrode of the drive transistor TR _D changes from V _Ofs to V _Sig (> V _Ofs ), the potential between the first node ND ₁ and the second node ND ₂ changes. That is, the electric charge based on the change (V _Sig −V _Ofs ) of the potential of the gate electrode of the drive transistor TR _D (= the potential of the first node ND ₁ ) is between the first node ND ₁ and the second node ND _2. and the capacitance value of the second node ND ₂ in response to the capacitance value between the second feeder line PS2, are distributed. However, if the value c _b (= c _EL ) is sufficiently larger than the value c _A (= c ₁ + c _gs ), the change in the potential of the second node ND ₂ is small. In general, the value c _EL of the capacitance C _EL of the light emitting unit ELP is larger than the value c ₁ of the capacitance unit C ₁ and the parasitic capacitance value c _{gs of the} driving transistor TR _D. For convenience, the following description will be made without considering the potential change of the second node ND ₂ caused by the potential change of the first node ND ₁ . In the drive timing chart shown in FIG. 7, the change in the potential of the second node ND ₂ caused by the change in the potential of the first node ND ₁ is shown without consideration. The same applies to FIG.

In the above-described writing process, the video signal V _CC is applied to the gate electrode of the drive transistor TR _D while the drive voltage V _CC-H is applied from the power supply unit 100 to one source / drain region of the drive transistor TR _{D. Sig} is applied. For this reason, as shown in FIG. 7, the potential of the second node ND ₂ rises in [Period -TP (2) _6B ]. The amount of increase in potential (ΔV shown in FIG. 7) will be described later. When potential V _g of the gate electrode of the driving transistor TR _D (the first node ND _1), the potential of the other of the source / drain regions of the driving transistor TR _D (the second node ND ₂₎ was V _s, the above-described If the increase in the potential of the two-node ND ₂ is not taken into consideration, the values of V _g and V _s are as follows. The potential difference between the first node ND ₁ and the second node ND ₂ , that is, the potential difference V _gs between the gate electrode of the driving transistor TR _{D and} the other source / drain region serving as the source region is expressed by the following equation (3). Can be represented.

V _g = V _Sig
V _s ≈V _Ofs −V _th
V _gs ≈V _Sig − (V _Ofs −V _th ) (3)

That, V _gs obtained in the writing process for the driving transistor TR _D, the video signal V _Sig for controlling the luminance of the light emitting section ELP, the threshold voltage V _th of the driving transistor TR _D, and the gate of the driving transistor TR _D It depends only on the voltage V _Ofs for initializing the potential of the electrode. And it is unrelated to the threshold voltage V _{th-EL of} the light emitting unit ELP.

Next, an increase in the potential of the second node ND ₂ in [period-TP (2) _6B ] described above will be described. In the driving method described above, in the writing process, the potential (that is, the second source / drain region) of the other source / drain region of the driving transistor TR _D is determined in accordance with the characteristics of the driving transistor TR _D (for example, the magnitude of the mobility μ). Mobility correction processing for increasing the potential of the node ND ₂ is also performed.

When the driving transistor TR _D is made of a polysilicon thin film transistor or the like, it is difficult to avoid variations in the mobility μ between the transistors. Therefore, even if the video signal V _Sig having the same value is applied to the gate electrodes of the plurality of drive transistors TR _D having different mobility μ, the drain current I _ds flowing through the drive transistor TR _D having the high mobility μ and the movement A difference is generated between the drain current I _ds flowing through the driving transistor TR _D having a small degree μ. And when such a difference arises, the uniformity (uniformity) of the screen of a display apparatus will be impaired.

In the drive method described above, the video signal V V is applied to the gate electrode of the drive transistor TR _D while the drive voltage V _CC-H is applied from the power supply unit 100 to one source / drain region of the drive transistor TR _{D. Sig} is applied. For this reason, as shown in FIG. 7, the potential of the second node ND ₂ rises in [Period -TP (2) _6B ]. If the value of the mobility μ of the driving transistor TR _D is large, the increase amount [Delta] V (potential correction value) of the potential of the other of the source / drain regions of the driving transistor TR _D (i.e., the potential of the second node ND ₂₎ increases . Conversely, if the value of the mobility μ of the driving transistor TR _D is small, the rise amount of the potential of the other of the source / drain regions of the driving transistor TR _D [Delta] V (potential correction value) is small. Here, the potential difference V _gs between the gate electrode of the driving transistor TR _{D and} the other source / drain region serving as the source region is transformed from the equation (3) into the following equation (4).

V _gs ≈V _Sig − (V _Ofs −V _th ) −ΔV (4)

Note that the total time (t ₀ ) of a predetermined time for executing the writing process (in FIG. 7, [period-TP (2) _6B ]) may be determined according to the design of the display element and the display device. [Period -TP (2) _6B ] so that the potential (V _Ofs −V _th + ΔV) in the other source / drain region of the driving transistor TR _D at this time satisfies the following expression (2 ′). total time t ₀ is the assumed to be determined in. [period -TP (2) _6B], does not light emission unit ELP emits light. this mobility correction processing, the coefficient k (≡ (1/2) Correction of (W / L) · C _ox ) variation is also performed at the same time.

(V _Ofs −V _th + ΔV) <(V _th−EL + V _Cat ) (2 ′)

[Period -TP (2) _6C ] (see FIGS. 7 and 10A)
By the above operation, the steps (a) to (c) are completed. Thereafter, the step (d) is performed in [Period-TP (2) _6C ] and [Period-TP (2) ₇ ]. That is, the write transistor TR _W is turned off based on the operation of the scanning circuit 101 in a state where the drive voltage V _CC-H is applied from the power supply unit 100 to one source / drain region of the drive transistor TR _D. The first node ND ₁ , that is, the gate electrode of the driving transistor TR _D is brought into a floating state. Therefore, as a result of the above, the potential of the second node ND ₂ rises.

Here, as described above, the gate electrode of the drive transistor TR _D is in a floating state, and since the capacitor portion C ₁ exists, the same phenomenon as that in the so-called bootstrap circuit occurs in the gate electrode of the drive transistor TR _D. As a result, the potential of the first node ND ₁ also rises. The potential difference V _gs between the gate electrode of the driving transistor TR _{D and} the other source / drain region serving as the source region holds the value of the equation (4).

Further, since the potential of the second node ND ₂ rises and exceeds (V _th−EL + V _Cat ), the light emitting unit ELP starts to emit light (see FIG. 10B). At this time, since the current flowing through the light emitting unit ELP is the drain current I _ds flowing from the drain region to the source region of the driving transistor TR _D , it can be expressed by Expression (1). Here, from the formulas (1) and (4), the formula (1) can be transformed into the following formula (5).

I _ds = k · μ · (V _Sig −V _Ofs −ΔV) ² (5)

Therefore, the current I _ds flowing through the light emitting unit ELP is a value of the potential correction value ΔV caused by V _Ofs and the mobility μ of the driving transistor TR _D from the value of the video signal V _Sig for controlling the luminance in the light emitting unit ELP. Is proportional to the square of the value obtained by subtracting. Stated words, current I _ds flowing through the light emitting section ELP, the threshold voltage V _th-EL of the luminescence part ELP, and does not depend on the threshold voltage V _th of the driving transistor TR _D. That is, the light emitting quantity of the light emitting portion ELP (luminance), the influence of the threshold voltage V _th-EL of the luminescence part ELP, and not affected by the threshold voltage V _th of the driving transistor TR _D. The luminance of the display element 10 is a value corresponding to the current _Ids .

In addition, since the potential correction value ΔV increases as the driving transistor TR _D has a higher mobility μ, the value of V _{gs on} the left side of Equation (4) decreases. Accordingly, in equation (5), even if the value of mobility μ is large, the value of (V _Sig −V _Ofs −ΔV) ² becomes small. As a result, variation in mobility μ of drive transistor TR _D (and further, k Variation in drain current I _ds caused by variation) can be corrected. As a result, it is possible to correct the luminance variation of the light emitting unit ELP caused by the variation in mobility μ (further, the variation in k).

Then, the light emission state of the light emitting unit ELP is continued for m ′ horizontal scanning periods. The subsequent operation is the same as that described for [period-TP (2) ₋₁ ] described above. The period until immediately before the next [period-TP (2) _0A ] is the light emission period.

  The operation of the display element 10 has been described above. As shown in FIG. 14 to be described later, in the driving method of the reference example, in the area DA (p), a phenomenon in which the luminance gradually changes according to the scanning order is recognized. In FIG. 14 and FIG. 21 described later, three areas DA (1) to DA (3) are shown for convenience.

  Details of the phenomenon in which the luminance gradually changes according to the scanning order will be described. In the following description, NL (p) = 48 is assumed for convenience.

In the display device shown in FIG. 1, is feeder line PS1 _p shared in the region DA (p), the [p, 1] row, second [p, 48] lines constituting the region DA (p) In the display element group, the voltage of the feeder line PS1 is switched at the same timing. On the other hand, the display element group constituting the area DA (p) is sequentially scanned from the [p, 1] row to the [p, 48] row. Accordingly, as shown in FIG. 11, [period-TP (2) _0B ], which is a waiting period before preprocessing, is the longest in the [p, 1] _-th row, and is shortened by one horizontal scanning period as scanning progresses. Become. On the other hand, [period-TP (2) _0D ], which is a waiting period after the preprocessing, is the shortest in the [p, 1] _-th row, and becomes longer by one horizontal scanning period as scanning progresses.

In the above description, it is assumed that the potential of the second node ND ₂ drops to (V _Cat + V _th−EL ) in [period-TP (2) _0A ] that is a waiting period before preprocessing. However, in practice, a certain amount of time is required for the potential of the second node ND ₂ to reach (V _Cat + V _th−EL ). Accordingly, as shown in FIG. 12A, a current flows through the light-emitting portion ELP during [period-TP (2) _0B ], which is a waiting period before preprocessing, and the light-emitting portion ELP emits light.

That is, as indicated by a broken line in FIG. 12B, the potential of the second node ND ₂ changes toward (V _Cat + V _th−EL ) in [Period -TP (2) _0B ]. On the other hand, at the beginning of [Period -TP (2) _0C ], the voltage of the feed line PS1 _p is switched from V _CC-H (20 volts) to V _CC-L (-14 volts). At the beginning of [Period -TP (2) _0C ], the potential of the second node ND ₂ rapidly drops to a voltage lower than (V _Cat + V _th-EL ).

Therefore, qualitatively, as [Period-TP (2) _0B ] becomes shorter, the amount of current flowing through the light emitting portion ELP in [Period-TP (2) _0B ] decreases. In other words, as [Period-TP (2) _0B ] becomes shorter, the light emission amount of the light emitting part ELP in [Period-TP (2) _0B ] becomes smaller.

In the above description, the drive transistor TR _D is in the OFF state in [Period -TP (2) _0D ], and ideally, the potential of the first node ND _{1 and} the potential of the second node ND ₂ . Decided to maintain the previous state. However, actually, as shown in FIG. 13A, the leakage current from the light emitting unit ELP and the leakage current from the driving transistor TR _D flow into the second node ND ₂ . Due to these leakage currents, the potential of the second node ND ₂ gradually rises as shown by the broken line in FIG. The amount of increase in the potential of the second node ND ₂ has a relationship such that it increases as [period-TP (2) _0D ] increases.

In the above description, the potential V ₀ of the second node ND ₂ at the start of [Period -TP (2) ₁ ] shown in FIG. 13B is ideally maintained at −10 volts. . However, as [Period -TP (2) _0D ] becomes longer, the potential V ₀ changes to the positive side. Then, when the potential V ₀ changes to the plus side, the influence also affects the potential of the second node ND ₂ in [Period-TP (2) ₂ ] to [Period-TP (2) _6B ]. Therefore, qualitatively, the potential of the second node ND ₂ in [period-TP (2) _6B ] also changes to the positive side as [period-TP (2) _0D ] becomes longer. As a result, as [Period-TP (2) _0D ] becomes longer, the potential difference between the first node ND ₁ and the second node ND _{2 at} the end of [Period-TP (2) _6B ] becomes smaller.

Therefore, qualitatively, as [Period-TP (2) _0D ] becomes longer, the drain current I _ds flowing in the drive transistor TR _D after [Period-TP (2) _6C ] decreases, and the light emitting unit ELP The brightness also decreases.

As described above, as [Period-TP (2) _0B ] becomes shorter, the light emission amount of the light emitting part ELP in [Period-TP (2) _0B ] becomes smaller, and [Period-TP (2) _0D ] becomes smaller. The longer it is, the lower the luminance of the light emitting part ELP after [Period -TP (2) _6C ].

As described above, [period-TP (2) _0B ], which is a waiting period before preprocessing, is the longest in the [p, 1] _-th row, and is shortened by one horizontal scanning period as scanning progresses. On the other hand, the [period-TP (2) _0D ], which is a waiting period after the preprocessing, is the shortest in the [p, 1] _-th row, and is shortened by one horizontal scanning period as scanning progresses. Therefore, even if the value of the video signal V _Sig is constant, the luminance of the light emitting unit ELP is relatively lowered in the [p, i + 1] -th row with respect to the [p, i] -th row.

Therefore, in the driving method of the first embodiment, after performing the pre-processing, the p-th feeder line has the same polarity as the driving voltage V _CC-H (20 volts) and has an absolute value. After applying the auxiliary voltage V _CC-FH (30 volts) having a large value for a predetermined period, the drive voltage V _CC-H is applied to the p-th feeder line. FIG. 15 illustrates a waiting period before pre-processing and a waiting period after pre-processing in the driving method of the display device according to the first embodiment (hereinafter, sometimes simply referred to as the driving method of the first embodiment). It is a schematic diagram of the drive timing chart of a display apparatus for demonstrating.

As shown in FIG. 15, in the first embodiment, during the waiting period after the pretreatment, the auxiliary voltage V _CC-FH (30 volts) is applied to the feeder line PS1 _p [period-TP (2). _[0D ] and [period-TP (2) _0E ] in which the drive voltage V _CC-H (20 volts) is applied to the feeder line PS1 _p . The length of [Period -TP (2) _0D ] is a constant length in the [p, 1] -th to [p, 48] -th rows. On the other hand, [Period -TP (2) _0E ] is the shortest in the [p, 1] _-th row, and becomes shorter by one horizontal scanning period as scanning progresses. In the first embodiment, the waiting period after the preprocessing in the [p, 1] -th row is configured only by [period-TP (2) _0D ], but is not limited thereto. .

FIG. 16A is a schematic circuit diagram for explaining a potential change of the second node in [period-TP (2) _0D ] illustrated in FIG. FIG. 16B is a schematic circuit diagram for explaining a potential change of the second node in [period-TP (2) _0E ] illustrated in FIG. FIG. 16C is a schematic timing chart for explaining the potential change of the second node after [period-TP (2) _0D ] shown in FIG.

In the [period -TP (2) _0D] The feeder line PS1 ₁ is applied auxiliary voltage V _CC-FH (30 volts), the period -TP (2) _0E] In the feeder line PS1 ₁ Is applied with a drive voltage V _CC-H (20 volts). Accordingly, focusing on the leakage current flowing from the driving transistor TR _D into the second node ND ₂ , the amount of leakage current per horizontal scanning period (1H) is more than [period-TP (2) _0E ] than [period-TP (2) _0E ]. (2) _0D ] is larger. In other words, the potential change per horizontal scanning period of the second node ND ₂ is larger in [Period -TP (2) _0D ] than in [Period -TP (2) _0E ].

FIG. 17 is a schematic diagram of a driving timing chart of the display device for explaining a configuration of a waiting period after preprocessing in the driving method of the first embodiment. [Period-TP (2) _0D ] is set to 100 horizontal scanning periods (100H), and [Period-TP (2) _0E ] is the longest 47 horizontal scanning periods (47H) in the [p, 48] -th row. Become.

It can be assumed that the degree of potential change of the second node generated in one horizontal scanning period (1H) due to the leak current flowing from the driving transistor TR _D is substantially proportional to the value of the voltage applied to the power supply line PS1 _p . Further, the degree of potential change of the second node per horizontal scanning period (1H) in [Period-TP (2) _0D ] and per horizontal scanning period (1H) in [Period-TP (2) _0E ]. It can be assumed that the degree of potential change at the second node is constant.

Here, in [Period -TP (2) _0E ], the degree of potential change of the second node generated in one horizontal scanning period (1H) due to the leak current flowing from the driving transistor TR _D is normalized as “1”. In [Period -TP (2) _0D ], the degree of potential change of the second node generated in one horizontal scanning period (1H) due to the leak current flowing from the driving transistor TR _D can be expressed as “1.5”.

In the area DA (p), in the [p, 1] -th row, the waiting period after the pre-processing is constituted only by [period-TP (2) _0D ], and is generated by a leak current flowing from the driving transistor TR _D. The degree of potential change of the second node is “150 (= 1.5 × 100)”. On the other hand, in the [p, 48] -th row, “197 (= 1.5 × 100 + 1 × 47)”. Taking the [p, 1] -th row as a reference, the degree of potential change of the second node in the [p, 48] -th row is 31% larger.

On the other hand, in the case of the operation of the reference example, even in the 17 [Period -TP (2) _0D], the feeder line PS1 ₁ driving voltage V _CC-H (20 V) is applied. Accordingly, in the [p, 1] -th row, the degree of potential change of the second node caused by the leak current flowing from the driving transistor TR _D is “100 (= 1 × 100)”. On the other hand, in the [p, 48] -th row, “147 (= 1 × 100 + 1 × 47)”. Taking the [p, 1] -th row as a reference, the degree of potential change of the second node in the [p, 48] -th row is 47% larger.

  In the first embodiment, the difference in the degree of potential change of the second node in the [p, 1] -th row and the [p, 48] -th row is more relaxed than in the reference example. Thereby, the brightness | luminance difference between the area | regions shown in FIG. 14 can be suppressed.

  Example 2 also relates to a display device and a driving method of the display device according to the present invention. The second embodiment is a modification of the first embodiment. The second embodiment is mainly different from the first embodiment in that the scanning order of the display element group in the area DA (p) is different.

  Since the configuration of the display device and the display element is the same as that described in the first embodiment, the description thereof is omitted. In the following description, NL (p) = 30 is assumed for convenience.

  FIG. 18 shows a waiting period before pre-processing and a waiting period after pre-processing in the driving method of the display device according to the second embodiment (hereinafter, sometimes simply referred to as driving method of the second embodiment). It is a schematic diagram of the drive timing chart of a display apparatus for demonstrating. FIG. 19 is a table showing the relationship among the row number in the region, the scanning order in the region, the luminance value, the overall row number, and the overall scanning order in the driving method of the second embodiment. is there.

In the first embodiment, even if the value of the video signal V _Sig is constant, the luminance of the light emitting unit ELP is relatively decreased in the [p, i + 1] -th row with respect to the [p, i] -th row. The trend remains. FIG. 20 shows that when NL (p) = 30 and the display device is driven by the driving method of Embodiment 1, the row number in the region, the scanning order in the region, the luminance value, the row number as a whole, And it is the table | surface showing the relationship of the order of scanning as a whole. The luminance value in FIGS. 19 and 20 is the display element group that is scanned first in each region when the video signal V _Sig (2 volts in the above example) that causes the display device to display black is input. The value is normalized with the luminance value set to 100.

Each row in the area DA (p + 1) is scanned under the same conditions as each corresponding row in the area DA (p). Accordingly, in a state where the display device is operated based on the video signal V _Sig having a constant value, the luminance value in the display element group scanned first in the area DA (p) and the first value in the area DA (p + 1). The luminance value of the display element group scanned first is substantially equal. If the amount of change in the luminance value of the display element group caused by one difference in scanning order is expressed as ΔL, ΔL = 0.25 in the examples shown in FIGS. 19 and 20.

  Next, a driving method according to the second embodiment will be described. Also in the driving method of the second embodiment, as a whole, the display device is scanned line-sequentially, after the display element group constituting the area DA (p) is scanned, the display element group constituting the area DA (p + 1) is scanned. Is done. However, the scanning order of the display element group in each area DA (p) is different from the driving method of the first embodiment.

The value of the number of rows of the display element group forming the region DA (p) is represented as NL (p), and the minimum value in NL (1) to NL (P) is represented as _{NL_MIN} . A row including the display element group of the i-th row (where i = 1, 2,..., NL (p)) in the region DA (p) is represented as a [p, i] -th row, and the region DA (p) The order of scanning the display element groups belonging to the first is counted as the first to NL (p) th, and the maximum absolute value of the difference in the scanning order between adjacent display element groups in the area DA (p) _Is represented as AD (p), and the maximum value in AD (1) to AD (P) is represented as _{AD_MAX} . The order in which the [p, NL (p)] rows are scanned in the area DA (p) (except when p = P) and the [p + 1, 1] rows are scanned in the area DA (p + 1). The absolute value of the difference from the order is represented as BD (p), and the maximum value in BD (1) to BD (P-1) is represented as _{BD_MAX} .

In the second embodiment, _{NL_MIN} is an integer of 4 or more, and the display element group constituting the areas DA (1) to DA (P) is in the [p, k] _-th row ( However, a positive value and a negative value are mixed in a value obtained by subtracting the order in which the [p, k + 1] -th row is scanned from the order in which k = 1, 2,..., NL (p) −1) is scanned. Furthermore, _{AD_MAX} is _equal to a certain integer TN (where TN is a predetermined value satisfying 2 ≦ TN <( _{NL_MIN−} 1)), and _{BD_MAX} is smaller than TN Or are scanned to satisfy an equal condition. More specifically, in Example 2, TN = 4.

In the second embodiment, the value of TN is set so as to satisfy TN · ΔL ≦ α · L _MAX . In the embodiment, α = 0.01. That is, the value of TN is set so that the difference in luminance value between adjacent display element groups is 1% or less.

In the second embodiment, _{NL_MIN} is an integer greater than or _equal to 5, and satisfies the relationship 2 ≦ TN < _{NL_MIN} / 2. Furthermore, _{NL_MIN} is an integer _equal to or greater than 20, and satisfies 2 ≦ TN < _{NL_MIN} / 5. Therefore, for a display device that simply performs line-sequential scanning, adjacent DA (p) and DA (p + 1) ) Is suppressed to about 1/5 at the maximum.

  In the driving method of the second embodiment, in the area DA (p), after the [p, 1] -th row is scanned, the [p, 29] -th row is scanned, and then the [p, 2] -th row. A row is scanned. In this way, the scanning order is changed with respect to the row arrangement in the area DA (p). That is, the order in which the [p, k + 1] -th row is scanned is subtracted from the order in which the [p, k] -th row (where k = 1, 2,..., 29) is scanned in the area DA (p). The value is scanned so that a positive value and a negative value are mixed. The order in which the [p, 30] rows in the area DA (p) are scanned is fourth, and the order in which the [p + 1, 1] rows in the adjacent area DA (p + 1) are scanned is first. is there.

As is clear from FIG. 19, the absolute value of the difference in scanning order between adjacent display element groups in the area DA (p) is 1 to 4, and the maximum value, that is, AD (p) is 4. The order in which the [p, 30] th row is scanned in the area DA (p) (except when p = P) and the order in which the [p + 1, 1] th row is scanned in the area DA (p + 1). The absolute value of the difference between and is 3. Therefore, BD (p) is 3. Since the areas DA (1) to DA (P) are scanned under the same conditions, the maximum value _{AD_MAX} in AD (1) to AD (P) is 4, and in BD (1) to BD (P-1). The maximum value _{BD_MAX} = 3.

  Therefore, according to the driving method of the second embodiment shown in FIG. 19, the difference in luminance value between adjacent display element groups in the area DA (p) is kept at 1 or less. Further, even in a portion where the region DA (p) and the region DA (p + 1) are adjacent to each other, the difference in luminance value between the adjacent display element groups is kept at 1 or less. Therefore, as shown in FIG. 21, the contrast between DA (p) and DA (p + 1) does not stand out.

The scanning order shown in FIG. 19 is an example, and the area DA (p) may be scanned in another order under the condition of TN = 4. Note that the signal output circuit 102 shown in FIG. 1 needs to output the video signal V _Sig by changing the order in accordance with the change of the order of scanning. The control circuit 103 controls the scanning circuit 101 and the signal output circuit 102 with reference to the table storing the correspondence relationship between the row numbers as a whole and the order of scanning as shown in FIG. If NL (P) is the same, the operation timing of the power supply unit 100 is the same between the driving method of the first embodiment and the driving method of the second embodiment.

  As mentioned above, although this invention was demonstrated based on the preferable Example, this invention is not limited to this Example. The structure and structure of the display device and the display element described in the embodiments and the steps of the display device driving method are examples, and can be changed as appropriate.

For example, the first node initialization voltage V _Ofs may be used as the extinguishing signal instead of the extinguishing signal V _Ers . In this case, V _Ofs and V _Sig are alternately applied to the data line DTL.

In addition, as illustrated in FIG. 22, the drive circuit 11 configuring the display element 10 may include a transistor (first transistor TR ₁ ) connected to the first node ND ₁ . In the first transistor TR ₁ , the first node initialization voltage V _Ofs and the extinction signal V _Ers are applied to one source / drain region, and the other source / drain region is connected to the first node ND _1. Yes. A signal from the first transistor control circuit 104 is applied to the gate electrode of the first transistor TR ₁ via the first transistor control line AZ1 to control the on / off state of the first transistor TR ₁ . Thereby, the potential of the first node ND ₁ can be set. In addition to this, another transistor may be provided.

In the embodiment, the drive transistor TR _D has been described as an n-channel type. In the case where the driving transistor TR _D is a p-channel transistor, the connection may be made by replacing the anode electrode and the cathode electrode of the light emitting unit ELP. In this configuration, since the direction in which the drain current flows changes, the value of the voltage applied to the power supply line or the like may be changed as appropriate.

TR _W: writing transistor, TR _D: driving transistor, TR _1: first transistor, C _1: capacitance unit, ELP: organic electroluminescence light emitting unit, C _EL: light emitting unit ELP capacitance, ND ₁ ... First node, ND ₂ ... Second node, SCL... Scanning line, DTL... Data line, AZ1. Feed line, PS2 ... second feed line, 10 ... display element, 11 ... drive circuit, 20 ... support, 21 ... substrate, 31 ... gate electrode, 32 ... Gate insulating layer 33: Semiconductor layer 34 ... Channel forming region 35, 35 ... Source / drain region 36 ... Other electrode 37 ... One electrode 38 ...・ Wiring, 39 ... wiring, 40 ... interlayer insulating layer, 51. Anode electrode, 52... Hole transport layer, light emitting layer and electron transport layer, 53... Cathode electrode, 54... Second interlayer insulating layer, 55, 56. Power supply unit, 101... Scanning circuit, 102... Signal output circuit, 103... Control circuit, 104.

Claims (8)

N display elements arranged in a two-dimensional matrix of N in the first direction, M in the second direction different from the first direction, and a total of N × M,
One row of display elements arranged in the first direction constitutes one display element group, and P display area portions formed by a plurality of display element groups arranged adjacent to each other (where P is And a display area is formed by P display area portions arranged in the second direction, and the display area of the pth display area (where p = 1, 2,..., P) The part is represented as region DA (p),
For each display region portion, the display element is a method of driving a display device that is scanned in units of display element groups,
The display device further includes M scanning lines extending in the first direction, N data lines extending in the second direction, and P power supply lines extending in the first direction.
The display element includes a light emitting unit, and a drive circuit for driving the light emitting unit by passing current.
The drive circuit includes a write transistor, a drive transistor, and a capacitor,
In the display element of the m-th row (where m = 1, 2,..., M) and the n-th column (where n = 1, 2,..., N),
In the driving transistor, the other source / drain region is connected to one end of the light-emitting portion and is connected to one electrode of the capacitor portion to form a second node, and the gate electrode is the writing transistor Is connected to the other source / drain region of the capacitor, and is connected to the other electrode of the capacitor portion, forming a first node,
In the write transistor, one source / drain region is connected to the nth data line, and the gate electrode is connected to the mth scan line,
In the display element group that forms the region DA (p), one source / drain region of the drive transistor that forms the display element is connected to the p-th feeder line.
(A) A predetermined first node initialization voltage is applied to the first node in a state where a predetermined drive voltage is applied from the p-th feeder line to one source / drain region of the drive transistor, thereby A threshold voltage canceling process for changing the potential of the second node toward the potential obtained by subtracting the threshold voltage of the driving transistor from the potential of the one node is performed at least once, and then
(B) performing a writing process of applying a video signal from the data line to the first node via the writing transistor;
(C) In a state where a predetermined drive voltage is applied to the p-th power supply line, the write transistor is turned off to make the first node floating, and the first node and the second node are connected via the drive transistor. A current corresponding to the value of the potential difference between and is sent to the light emitting part, and then
(D) In a state where a predetermined drive voltage is applied to the p-th feeder line, a turn-off signal is applied to the first node, so that the drive transistor is turned off.
It has a process,
Steps (a) to (d) are repeated, and after the step (d) has been completed for all display elements forming the region DA (p) and until the next step (a) is performed. In addition,
(E) A predetermined second node initialization voltage is applied to the p-th feeder line, so that the potential difference between the anode electrode and the cathode electrode provided in the light emitting unit does not exceed the threshold voltage of the light emitting unit. In this state, pre-processing for changing the potential of the first node toward the potential obtained by adding the threshold voltage of the driving transistor to the potential of one of the source / drain regions of the driving transistor is performed. After applying an auxiliary voltage having the same polarity as the drive voltage and a larger absolute value for a predetermined period, the drive voltage is applied to the p-th feeder line.
A driving method of a display device. The value of the number of rows of the display element group forming the region DA (p) is represented as NL (p), and the minimum value in NL (1) to NL (P) is represented as _{NL_MIN} .
A row including the display element group of the i-th row (where i = 1, 2,..., NL (p)) in the region DA (p) is represented as a [p, i] -th row, and the region DA (p) The order in which each display element group belonging to is scanned is counted as the first to NL (p) th,
In the area DA (p), the maximum absolute value of the scanning order difference between adjacent display element groups is expressed as AD (p), and the maximum value in AD (1) to AD (P) is expressed as _{AD_MAX.} ,
The order in which the [p, NL (p)] rows are scanned in the area DA (p) (except when p = P) and the [p + 1, 1] rows are scanned in the area DA (p + 1). When the absolute value of the difference from the order is represented as BD (p) and the maximum value in BD (1) to BD (P-1) is represented as _{BD_MAX} ,
_{NL_MIN} is an integer greater than or _equal to 4,
The display element group constituting the areas DA (1) to DA (P) is the [p, k] -th row (where k = 1, 2,..., NL (p) −1) in the area DA (p). Is scanned so that a positive value and a negative value are mixed in a value obtained by subtracting the order in which the [p, k + 1] -th row is scanned from the order in which they are scanned.
_{AD_MAX} is _equal to a certain integer TN (where TN is a predetermined value satisfying 2 ≦ TN <( _{NL_MIN−} 1)), and _{BD_MAX} is less than or equal to TN. The method of driving a display device according to claim 1, wherein scanning is performed as described above. In a state where the display device is operated based on the video signal having a certain value, the luminance of the display element group constituting the area DA (p) changes in a certain direction in accordance with an increase in the scanning order in the area DA (p). And
The maximum luminance value in the N display element groups when a video signal having a constant value that causes the display device to display black is input is represented as L _MAX, and the display element is generated by one difference in scanning order. When the change amount of the luminance value of the group is expressed as ΔL and a certain coefficient is expressed as α (where α satisfies 0 <α <1 and one predetermined value in the display device),
The display device driving method according to claim 2, wherein the value of TN is set so as to satisfy TN · ΔL ≦ α · L _MAX . _{4. The} method for driving a display device according to claim 2, wherein _{NL_MIN} is an integer of 5 or more and satisfies 2 ≦ TN < _{NL_MIN} / 2. 5. _{NL_MIN} is an integer greater than or _equal to 20, The drive method of the display apparatus of Claim 4 which satisfy _{| fills} 2 <= TN < _{NL_MIN} / 5.   2. The display device driving method according to claim 1, wherein the number of rows of the display element group forming the area DA (p) is a constant value.   The method of driving a display device according to claim 1, wherein the light emitting unit is an organic electroluminescence light emitting unit. N display elements arranged in a two-dimensional matrix of N in the first direction, M in the second direction different from the first direction, and a total of N × M,
One row of display elements arranged in the first direction constitutes one display element group, and P display area portions formed by a plurality of display element groups arranged adjacent to each other (where P is And a display area is formed by P display area portions arranged in the second direction, and the display area of the pth display area (where p = 1, 2,..., P) The part is represented as region DA (p),
For each part of the display area, the display element is a display device that is scanned in units of display element groups,
The display device further includes M scanning lines extending in the first direction, N data lines extending in the second direction, and P power supply lines extending in the first direction.
The display element includes a light emitting unit, and a drive circuit for driving the light emitting unit by passing current.
The drive circuit includes a write transistor, a drive transistor, and a capacitor,
In the display element of the m-th row (where m = 1, 2,..., M) and the n-th column (where n = 1, 2,..., N),
In the driving transistor, the other source / drain region is connected to one end of the light-emitting portion and is connected to one electrode of the capacitor portion to form a second node, and the gate electrode is the writing transistor Is connected to the other source / drain region of the capacitor, and is connected to the other electrode of the capacitor portion, forming a first node,
In the write transistor, one source / drain region is connected to the nth data line, and the gate electrode is connected to the mth scan line,
In the display element group that forms the region DA (p), one source / drain region of the drive transistor that forms the display element is connected to the p-th feeder line.
(A) A process in which a predetermined first node initialization voltage is applied to the first node in a state where a predetermined drive voltage is applied from the p-th power supply line to one source / drain region of the drive transistor. At least once, then
(B) A video signal is applied from the data line to the first node via the write transistor, and then
(C) In a state where a predetermined drive voltage is applied to the p-th power supply line, the write transistor is turned off, and the potential difference value between the first node and the second node is set via the drive transistor. A corresponding current is passed through the light emitting part, and then
(D) In a state where a predetermined drive voltage is applied to the p-th power supply line, a turn-off signal is applied to the first node, so that the drive transistor is turned off.
The process is done,
Steps (a) to (d) are performed repeatedly, and after the step (d) is completed in all display elements forming the region DA (p) and until the next step (a) is performed. Between,
(E) A predetermined second node initialization voltage is applied to the p-th power supply line, so that the potential difference between the anode electrode and the cathode electrode provided in the light emitting unit does not exceed the threshold voltage of the light emitting unit. In this state, pre-processing for changing the potential of the first node toward the potential obtained by adding the threshold voltage of the driving transistor to the potential of one of the source / drain regions of the driving transistor is performed. The auxiliary voltage having the same polarity as the driving voltage and having a larger absolute value is applied for a predetermined period, and then the driving voltage is applied to the p-th feeder line.
Display device.