JP2011004059A - Buffer management method and buffer management device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce power consumption of an OLT by reducing power consumed in a buffer provided on the OLT, in order to store arrival data addressed to a sleeping logical link terminal.SOLUTION: A buffer management method manages a first buffer and a second buffer having larger power consumption than that of the first buffer, in the OLT in a PON system where a plurality of ONUs and the OLT are connected one to one via logical links and the ONUs are provided with sleep control processing of logical link terminals. The method includes: determining whether the logical link terminals are sleeping or not with respect to data addressed to the logical link terminals of the plurality of ONUs, and storing the data in the first buffer or the second buffer when the data is addressed to a sleeping logical link terminal, or storing data in the first buffer when the data is addressed to a non-sleeping logical link terminal.

Description

  The present invention relates to a PON (Passive Optical Network) system having a sleep control function for a logical link termination of a subscriber side device (ONU: Optical Network Unit), and a station side device (OLT: Optical Line) in the PON. The present invention relates to a buffer management method and a buffer management device that are effective in reducing the power consumption of Terminal).

FIG. 1 shows a configuration example of a PON system.
In FIG. 1, the PON system uses an optical splitter 11 to physically share a part of the optical fiber transmission line 12 and the OLT among a plurality of ONUs # 1 to ONU # N. The communication between ONU # 1 to ONU # N and the OLT is physically a many-to-one communication sharing the optical fiber transmission line 12, but it is logically possible to perform a one-to-one communication. As shown in FIG. 2, a logical link is established between the OLT and ONU # 1 to ONU # N.

  After the logical link is established, data including a plurality of services is transmitted / received between the logical link ends of the OLT and ONU # 1 to ONU # N. The logical link terminations of OLT and ONU # 1 to ONU # N have a priority control function. With this function, even when multiple services are mixed, the average throughput and maximum burst length according to each service specification can be obtained. Guaranteed. Here, two methods are disclosed as methods for guaranteeing average throughput and maximum burst length in downlink data transmitted from the OLT to the logical link terminations of ONU # 1 to ONU # N.

  One is a method in which each ONU guarantees the average throughput and the maximum burst length required in service specifications as shown in FIG. 3 (Non-patent Document 1). In this method, both large-scale integrated circuits (OLT LSIs and ONU LSIs) constituting the OLT and each ONU (or each logical link termination) are mounted with a receive buffer for downlink data as the internal buffer 13. The internal buffer 13 generally has a smaller buffer capacity and consumes less power than a buffer externally attached to an OLT LSI or ONU LSI.

  The reason why the buffer capacity may be small is that in the OLT, an ONU having a buffer for downlink data accumulates downlink data, and therefore a speed difference between a network node interface (NNI) and a PON interface (PON-IF). This is because the buffer for absorbing the light can be handled with a small capacity. In the ONU, the average voice and video throughput required in the service specifications is sufficiently low compared to the transmission speed of the PON-IF, and the buffer for satisfying the worst condition for inputting data with the maximum burst length is small. This is because the capacity can be used. Therefore, if all of the buffers are small in quantity, the increase in the LSI manufacturing cost due to the increase in mounting area is small, so that they are often mounted inside the LSI.

  Another method for guaranteeing average throughput and maximum burst length in downlink data is a method of centralized management by OLT as shown in FIG. 4 (Non-patent Document 2). In this method, the OLT LSI needs to connect a large-capacity external buffer 14 for downlink data. This is because the OLT needs to have a sufficient buffer capacity required for the service specifications for all ONUs, so the buffer capacity required for the OLT becomes large, and the necessary buffer capacity is secured inside the OLT LSI. This is because it becomes difficult in terms of cost. On the other hand, each ONU does not need to be provided with a buffer required for service specifications, so that the buffer capacity to be mounted can be accommodated with a small amount and can be mounted inside the ONU LSI.

  In the current PON system that always operates, the method of Non-Patent Document 1 is superior to the method of Non-Patent Document 2 in terms of OLT power consumption. That is, when an external buffer 14 that consumes more power and has a larger buffer capacity than the internal buffer 13 is used for the OLT, an external connection terminal for connecting to the external buffer 14 is required for the OLT LSI, and the OLT LSI internal As compared with the case where a buffer is mounted on the OLT, the power consumption of the OLT increases. Therefore, compared to the case where the OLT and each ONU both have the internal buffer 13 as in Non-Patent Document 1, the power consumption of the OLT is larger when centralized management is performed with the OLT as in Non-Patent Document 2.

  However, in recent years, the PON system has been required to reduce power consumption, and neither the OLT nor the ONU always operates. If there is no data to be transmitted / received between the OLT and the ONU logical link terminals, the logical link terminal A method for reducing the power consumption of the ONU by sleeping is proposed (for example, Non-Patent Document 3). The sleep control process is executed by negotiation using a dedicated frame as shown in FIG. 5, for example, and the OLT manages the sleep state for each logical link end. In addition, even if the logical link termination is in sleep, data may reach the sleeping logical link termination. Therefore, among the data sent to the sleeping logical link termination, particularly high priority Data needs to be stored in the OLT. As a result, the OLT requires a buffer capacity capable of storing data even when all logical link terminations sleep, and it is necessary to attach a buffer externally.

  Therefore, even in the method of Non-Patent Document 1 in which the OLT LSI and each ONU LSI have the internal buffer 13, as shown in FIG. 6, it is necessary to connect the external buffer 14 to the OLT LSI when sleep control is introduced. There is an inevitable increase in power consumption of the OLT. On the other hand, in the case of the method of Non-Patent Document 2 in which the OLT LSI has the external buffer 14, the external buffer 14 originally provided for the OLT to satisfy the service specifications may be used as it is at the time of sleep. The power consumption of the OLT does not change before and after. As for the power consumed by the buffer provided in the ONU, an internal buffer is used in any method. However, since the non-patent document 2 requires a smaller amount of the internal buffer capacity of the ONU, the non-patent document 2 is better. Low power consumption. Therefore, when sleep control is introduced, Non-Patent Document 2 is superior in terms of power consumption.

"PAS5201 Product Brief", PMC-Sierra, http://www.eefocus.com/data/06-12/110 1166149185 / File / 1166150970.pdf "TK3721 Product Brief", Teknovus Inc., http://www.teknovus.com/files/TK3721%20PB.pdf Jeff Mandin, "EPON Powersaving via Sleep Mode", IEEE802.3av 10GEPON Task Force (Sep, 2008)

  By the way, in the method of Non-Patent Document 2 in which the OLT LSI performs centralized management using the external buffer 14, a buffer for storing data that arrives during sleep and a buffer required for service specifications are shared. It is necessary to always operate regardless of the sleep state of the link end, and it is difficult to reduce the power consumed by the buffer and the power consumption of the OLT.

  In the method of Non-Patent Document 1, since each ONU includes a buffer required for service specifications, the buffer provided for the downlink data by the OLT mainly absorbs the speed difference between the NNI and the PON-IF. Used for the purpose of accumulating data that arrives during sleep. For this reason, if there is almost no speed difference between NNI and PON-IF and the number of logical link terminations during sleep is small, most of the buffer capacity is unnecessary. However, a method for reducing the power consumption of the unnecessary buffer capacity and reducing the power consumption of the OLT is not disclosed.

  The present invention relates to a buffer management method and a buffer management device capable of suppressing the power consumed by a buffer included in the OLT and reducing the power consumption of the OLT in order to accumulate data reaching the logical link end in sleep The purpose is to provide.

  A first invention is the OLT of a PON system in which a plurality of ONUs and an OLT are connected one-to-one via a logical link, and the plurality of ONUs have a sleep control process for a logical link termination, and a first buffer In the buffer management method for managing the second buffer that consumes more power than the first buffer, whether or not the logical link termination is sleeping for data destined for the logical link termination of a plurality of ONUs. If the destination is a logical link end when the data is sleeping, the data is stored in either the first buffer or the second buffer, and the destination is a logical link end where the data is not sleeping. The data is stored in the first buffer.

  According to a second aspect of the present invention, in the buffer management method according to the first aspect of the invention, the number of logical link terminations K in sleep is counted based on the management information of logical link terminations in sleep that the OLT has, and the logical link termination in sleep Data is accumulated in either the first buffer or the second buffer when the number K is greater than or equal to the threshold, and data is accumulated only in the first buffer when the number K of logical link terminations during sleep is less than the threshold. It is characterized by that.

  According to a third aspect of the present invention, in the buffer management method according to the second aspect of the present invention, there is provided information G indicating whether or not there is data destined for the logical link termination during sleep stored in the second buffer, and the logic during sleep When the number of link terminations K is equal to or greater than the threshold value or indicates that the information G is present, the normal mode for disabling the low-power function of the second buffer is set. In the case shown, the low power mode is set to enable the low power function of the second buffer.

  According to a fourth aspect of the present invention, in the buffer management method of the third aspect, when the number of logical link terminations K in the sleep state is equal to or greater than a threshold value, the OLT is considered to be completed after the transition process from the low power mode to the normal mode is completed. The start of sleep transition processing is notified to the logical link end.

  A fifth invention is characterized in that in the buffer management method of the second to fourth inventions, the threshold value is 1.

  According to a sixth aspect of the present invention, in the buffer management methods of the first to fifth aspects, at least a part of each of the first buffer and the second buffer is divided into regions in units of logical link terminations and managed as divided regions. As a divided region for storing data destined for the logical link end in sleep, the divided region of the first buffer is preferentially determined by a predetermined allocation method and the data is stored.

  In a seventh aspect of the present invention, in the buffer management method according to the sixth aspect of the invention, the predetermined allocation method is such that when a logical link end in which data is sleeping is a destination, a divided area is assigned to the logical link end that is a data destination. If it has been completed, data is accumulated in the divided area, and if the divided area is not assigned to the end of the logical link, and if there is a divided area not assigned to the other logical link end in the first buffer, the divided If an area is assigned to the logical link end, a divided area is not assigned to the logical link end, and there is no unassigned divided area at the other logical link end, the other buffer If an unassigned divided area is assigned to the logical link terminal and the destination is a logical link terminal where the data is not sleeping, the divided area assigned to the logical link terminal should be unassigned. And butterflies.

  According to an eighth aspect of the present invention, in the buffer management method according to the seventh aspect of the present invention, the predetermined allocation method divides the data into priorities when the destination is a logical link end where the data is not sleeping, It is characterized by accumulating in areas other than the divided areas.

  According to a ninth aspect of the present invention, in the buffer management methods of the sixth to eighth aspects, the predetermined allocation method includes a predetermined divided area identifier (buffer ID) uniquely determined for each divided area and a unique logical link end in advance. The allocation is assigned to the logical link termination identifier by assigning a buffer ID of the divided area, and the unassignment is assigned by assigning a null buffer ID to the logical link termination identifier.

  According to a tenth aspect of the present invention, a plurality of subscriber side devices and a station side device are connected one-to-one via a logical link, and the plurality of subscriber side devices have a logical link termination sleep control process. In a buffer management apparatus that manages a first buffer and a second buffer that consumes more power than the first buffer, a logical link termination of a plurality of subscriber-side apparatuses is a destination Control means for determining whether or not the logical link termination is sleeping with respect to the data to be set, and when the destination is the logical link termination when the data is sleeping, the data is sent to the first buffer or the second buffer. In the case where the destination is a logical link termination that is stored in any of the above and the data is not sleeping, input / output data processing means for storing the data in the first buffer is provided.

  According to an eleventh aspect of the present invention, in the buffer management device according to the tenth aspect, the control means counts the number of logical link terminations K during sleep based on the management information of the logical link terminations during sleep that the station side device has, Data is accumulated in either the first buffer or the second buffer when the number of logical link terminations K in the sleep state is equal to or greater than the threshold, and the data is stored in the first case when the number of logical link terminations K in the sleep is less than the threshold. The input / output data processing means is controlled so as to be stored only in the buffer.

  In a twelfth aspect of the present invention, in the buffer management device according to the eleventh aspect, the control means has information G indicating whether or not there is data destined for the terminating logical link during sleep stored in the second buffer, When the number of logical link terminations K in the sleep state is equal to or greater than the threshold value or the information G is present, the normal mode for disabling the low-power function of the second buffer is set. When G indicates absence, the input / output data processing means is controlled so as to enter the low power mode in which the low power function of the second buffer is enabled.

  According to a thirteenth aspect of the present invention, in the buffer management device of the twelfth aspect, when the control means determines that the transition process from the low power mode to the normal mode is completed when the number of logical link terminations during sleep is equal to or greater than a threshold value. The station side device notifies the logical link end of the start of the sleep transition processing.

  In the buffer management method of the first invention and the buffer management device of the tenth invention, the data addressed to the logical link end that is not in sleep, which has a large amount of data input / output, is larger than the data addressed to the logical link end in sleep. By accumulating only in the first buffer, which consumes less power when data is input / output compared to the second buffer, the power consumed by the OLT buffer can be reduced.

  In the buffer management method of the second invention and the buffer management device of the eleventh invention, when the number of sleeping logical link terminals is less than the threshold, the data addressed to the sleeping logical link terminals and to the non-sleeping logical link terminals By accumulating both in only the first buffer and suppressing the use of the second buffer, the power consumed by the OLT buffer can be reduced.

  In the buffer management method of the third invention and the buffer management device of the twelfth invention, the number of logical link terminations in sleep is less than a threshold value, and the logical link termination in sleep stored in the second buffer is the destination. By placing the second buffer in the low power mode when there is no data, the power consumed by the OLT buffer can be further reduced.

  In the buffer management method of the fourth invention and the buffer management device of the thirteenth invention, the transition time until the transition from the valid state (low power mode) to the invalid state (normal mode) is reduced is large. The low power function can be employed in the low power mode, and the power consumed by the OLT buffer can be reduced.

  In general, a low power function with a long transition time such as power gating has a large effect of reducing power consumption, but is difficult to adopt in a low power mode. This is because when the ONU is in the sleep state, the data addressed to the logical link end needs to be stored in the buffer by the OLT, but when the data addressed to the logical link end arrives during the transition time, the second buffer May not be available, and may not be stored in the second buffer. In the buffer management method according to the fourth aspect of the present invention, the OLT adjusts the transition timing so that the transition to the sleep state is instructed after the transition processing from the low power mode to the normal mode is considered to be completed. The low power function can be adopted in the low power mode.

  In the buffer management method of the fifth aspect of the invention, when there is no logical link termination in sleep, data destined for the logical link termination not in sleep is stored only in the first buffer, and the second buffer is in the low power mode. The power consumed by the OLT buffer can be reduced.

  In the buffer management method according to the sixth aspect of the present invention, the divided areas are not fixedly determined in advance for each logical link end, but the divided areas should be stored with the data assigned to the sleeping logical link end in a predetermined allocation method. Determine and accumulate. As a result, when the number of logical link terminations in sleep is small by preferentially allocating to the logical link termination in sleep from the divided region of the first buffer, the use of the second buffer is suppressed and the buffer consumption is reduced. Electric power can be reduced.

  According to the buffer management method of the seventh invention, it is possible to increase the number of logical link terminations during sleep for storing data in the first buffer, and it is possible to suppress the use of the second buffer and reduce the power consumption of the buffer. .

  Here, a divided region is assigned to the logical link end during sleep, and no divided region is assigned to the logical link end not sleeping. This is because the buffer capacity required for the OLT differs depending on whether or not it is in sleep. When there is almost no speed difference between the NNI and the PON-IF for the data addressed to the logical link terminal that is not sleeping, the buffer capacity required for each logical link terminal that is not sleeping is small. On the other hand, data destined for the logical link end during sleep must be stored in a buffer, and the required capacity varies depending on the service specifications, but may require a large capacity. Therefore, the division area is not assigned to the logical link terminal that is not sleeping, and all the data destined for the logical link terminal that is not sleeping is accumulated in the first buffer area other than the dividing area. It is possible to prevent the buffer capacity from being allocated to the logical link end that is not in the sleep state.

  In the buffer management method according to the eighth aspect of the invention, the data addressed to the logical link end that is not in sleep is divided into priorities and stored in a predetermined area of the first buffer, thereby suppressing the buffer capacity necessary for storing the data. This makes it possible to further increase the number of logical link terminations during sleep in which data is stored in the first buffer. This is because, in general, data such as audio and video has a smaller buffer capacity than the buffer capacity required for each logical link end for adjusting the speed difference between the NNI and the PON-IF due to the statistical multiplexing effect. Because. Therefore, at the logical link end that is not in sleep, the capacity allocated to the data destined for the logical link end that is not in sleep is suppressed by storing data according to priority in the first buffer area other than the divided area. be able to.

  In the buffer management method according to the ninth aspect of the invention, a buffer ID is uniquely determined in advance for each divided area of the first buffer and the second buffer, and the buffer ID is assigned to the divided area at the end of the logical link during sleep. By doing so, it is only necessary to manage the buffer IDs for the assignment and non-assignment management of both the first buffer and the second buffer, and the management of the divided regions becomes easy.

It is a block diagram which shows the structural example of a PON system. It is a block diagram which shows the mode of the logical link between OLT and ONU. It is a block diagram which shows the example of buffer arrangement | positioning for the downlink data of the conventional OLT and ONU. It is a block diagram which shows another buffer arrangement example for the downlink data of the conventional OLT and ONU. It is a figure which shows the sleep control process performed between OLT and ONU (logical link termination | terminus). It is a block diagram which shows the example of buffer arrangement | positioning for accumulating the data which arrive at the logical link termination | terminus addressed during sleep. It is a block diagram which shows the structural example of the PON system in embodiment of this invention. It is a block diagram which shows the structural example of the buffer management apparatus 15 of this invention. It is a figure which shows the relationship between the division | segmentation area | region of an internal buffer and an external buffer, and buffer ID. It is a figure which shows the mode of buffer ID allocation in the buffer ID management part 32. FIG. 4 is a flowchart showing buffer ID allocation processing in a buffer ID management unit 32. 4 is a flowchart showing buffer ID return processing in a buffer ID management unit 32. It is a flowchart which shows the determination process of the normal mode in the control determination part 33, and a low power mode. 5 is a flowchart showing a control instruction process of a low power function in a control instruction generator 34.

FIG. 7 shows a configuration example of the PON system in the embodiment of the present invention.
In FIG. 7, the OLT and the plurality of ONUs # 1 to #N connected via the optical splitter 11 are the same as those in the conventional PON system. The configuration in which the OLT and each ONU include the internal buffer 13 and the OLT includes the external buffer 14 that consumes more power than the internal buffer 13 is the same as the configuration illustrated in FIG.

  The feature of the present invention is that the internal buffer 13 and the external buffer 14 of the OLT LSI are selectively used according to the number of logical link terminations during sleep, and further the normal mode and external buffer for disabling the low power function of the external buffer 14 A buffer management device that sets a low power mode that enables 14 low power functions, sets the normal mode when the number of logical link terminations during sleep is equal to or greater than a threshold, and sets the low power mode when the number is less than the threshold There is a place with 15.

  The internal buffer 13 of each ONU has a buffer capacity required for service specifications. The OLT internal buffer 13 and external buffer 14 have buffer capacities for absorbing the speed difference between the NNI and the PON-IF and accumulating data arriving at the end of the logical link during sleep. Hereinafter, a detailed description will be given with reference to FIGS.

<Configuration of OLT Buffer Management Device 15>
FIG. 8 shows a configuration example of the buffer management device 15 of the present invention. FIG. 9 shows the relationship between the divided areas of the internal buffer and the external buffer and the buffer ID in the embodiment of the present invention.

  In FIG. 8, the buffer management device 15 arranged in the OLT LSI controls the input / output data processing unit 20 that performs storage control of data received by the NNI or using the OLT as a transmission source, and controls the low power function provided in the buffer. It is comprised by the low power function control part 30 to perform. The input / output data processing means and the control means according to claims 10 to 13 correspond to the input / output data processing section 20 and the low power function control section 30 in this embodiment.

<Configuration of Input / Output Data Processing Unit 20>
The input / output data processing unit 20 includes a buffer access control unit 21, an internal buffer access control unit 22, an external buffer access control unit 23, and an external connection terminal unit 24. The input / output data processing unit 20 uses NNI for reception or OLT as a transmission source. Data has a function of accumulating in either the internal buffer 13 or the external buffer 14.

  At least a part of the internal buffer 13 and the external buffer 14 divides the area into logical link termination units, and a divided area identifier (buffer ID) is uniquely determined in advance for each divided area. In this embodiment, as shown in FIG. 9, for the internal buffer, buffer ID # 1, buffer ID # 2,..., Buffer ID # V (V: data addressed to the end of the logical link that is sleeping only with the internal buffer) An upper limit value of the number of logical link terminations that can be accumulated (for example, V = 1) and a null buffer ID are assigned, and buffer ID # (V + 1), buffer ID # (V + 2),. #C (C: total number of logical link terminations of OLT) is assigned. The buffer ID uses a logical link termination identifier uniquely determined in advance for the logical link termination, and any one of buffer ID # 1 to buffer ID # C is used as a logical link termination identifier during sleep. Assigned by the management unit, and a null buffer ID is assigned to other logical link termination identifiers. The input / output data processing unit 20 stores the data received by the NNI or transmitted from the OLT in the internal buffer 13 or the external buffer 14 according to the buffer ID assigned to the logical link termination identifier.

  Hereinafter, the function of each unit of the input / output data processing unit 20 and the operation when the OLT receives data addressed to the logical link end during sleep and when the OLT receives data addressed to the logical link end not sleeping. explain.

<Function of Buffer Access Control Unit 21>
The buffer access control unit 21 includes a management table in which a logical link termination identifier and a buffer ID are recorded and managed in association with each other, and using this management table, a logical link termination identifier of data received by the NNI or originating from the OLT The buffer ID corresponding to is determined. If the determined buffer ID is one of the null buffer ID or buffer ID # 1 to buffer ID # V (the null buffer ID or the buffer ID ID number is V or less), the data and the buffer ID are transferred to the internal buffer access control unit. 22, if any of the buffer ID # (V + 1) to the buffer ID #C (the ID number of the buffer ID is greater than V), the data and the buffer ID are notified to the external buffer access control unit 23. .

<Function of Internal Buffer Access Control Unit 22>
Based on the buffer ID notified from the buffer access control unit 21, the internal buffer access control unit 22 sends data notified from the buffer access control unit 21 to the divided area of the internal buffer 13 to which the buffer ID is assigned. Control of writing / reading is performed.

<Function of External Buffer Access Control Unit 23>
Based on the buffer ID notified from the buffer access control unit 21, the external buffer access control unit 23 provides data notified from the buffer access control unit 21 to the divided area of the external buffer 14 to which the buffer ID is assigned. Control of writing / reading is performed.

  In addition, the external buffer access control unit 23 has a function for controlling the validity / invalidity of the low power function of the external buffer 14 and a function for controlling whether data can be written to / read from the external buffer 14. These functions are controlled by the external buffer access control unit 23 in accordance with a control instruction from the low power function control unit 30. Details of the instruction from the low power function control unit 30 will be described later.

<Function of External Connection Terminal Unit 24>
The external connection terminal unit 24 has an external connection terminal with the external buffer 14. The external connection terminal has a low power function (for example, a power supply cutoff function of the external connection terminal), and performs control of validity / invalidity of the low power function according to a control instruction from the low power function control unit 30. Details of the control instruction from the low power function control unit 30 will be described later.

<Operation of Input / Output Data Processing Unit 20 When Data Addressed to Logical Link Termination During Sleep>
When data destined for the logical link end in sleep is received, the input / output data processing unit 20 stores the data in either the internal buffer 13 or the external buffer 14. For the received data, the buffer access control unit 21 first determines the buffer ID corresponding to the logical link termination identifier of the data using the management table described above. Since a buffer ID other than the null buffer ID is assigned to the logical link termination identifier during sleep, the buffer ID to be calculated is one of buffer ID # 1 to buffer ID # C.

  The buffer access control unit 21 stores the data in the internal buffer 13 so that the data is stored in the internal buffer 13 if the ID number of the determined buffer ID is 1 to V (ID number is V or less). The data and the buffer ID are notified, and the internal buffer access control unit 22 accumulates the data in the divided area of the internal buffer 13 corresponding to the buffer ID. Similarly, the buffer access controller 21 stores data in the external buffer 14 if the ID number of the determined buffer ID is any one of (V + 1) to C (ID number greater than V). Notifies the external buffer access control unit 23 of the data and the buffer ID, and the external buffer access control unit 23 accumulates the data in the divided area of the external buffer 14 corresponding to the buffer ID.

<Operation of Input / Output Data Processing Unit 20 when Data Addressed to Logical Link Termination Not in Sleep>
When the OLT receives data addressed to the end of the logical link that is not sleeping, the buffer is mainly used to absorb the speed difference between the NNI and the PON-IF. The buffer capacity required for absorption is small. In this embodiment, it is assumed that there is almost no speed difference, and data destined for the logical link end that is not sleeping is stored in divided areas of the internal buffer 13 corresponding to the null buffer ID shown in FIG. The input / output data processing unit 20 is controlled to do so.

  First, the input / output data processing unit 20 uses the management table of the buffer access control unit 21 to determine the buffer ID corresponding to the logical link termination identifier of the data. Since the null buffer ID is assigned to all the logical link termination identifiers that are not sleeping, the buffer ID to be calculated is the null buffer ID. Since the null buffer ID is in a divided area corresponding to the internal buffer 13, the buffer access control unit 21 notifies the internal buffer access control unit 22 of the data and the null buffer ID, and the internal buffer access control unit 22 receives the null buffer ID. The data is divided and stored for each priority in the divided area of the internal buffer 13 corresponding to.

<Configuration of Low Power Function Control Unit 30>
The low power function control unit 30 includes a sleep count counting unit 31, a buffer ID management unit 32, a control determination unit 33, and a control instruction generation unit 34. A functional unit that performs a sleep control process shown in FIG. 5 is connected to the sleep count counting unit 31 and the buffer ID management unit 32.

<Function of Sleep Number Counting Unit 31>
The sleep number counting unit 31 detects the start of the transition process from the sleep control process of FIG. 5 to the sleep state (hereinafter referred to as “sleep transition”) and the end of the sleep state release process (hereinafter referred to as “sleep release”). To do. The sleep transition is a stage before the SLEEP frame in FIG. 5 is transmitted to the logical link end, that is, the sleep transition is determined for the logical link end in the OLT, and the start of the generation of the SLEEP frame is determined. This refers to the stage (before sending the SLEEP frame). Further, the sleep release refers to the stage after transmission of DATA in FIG. 5, that is, when the sleep state of the logical link end is canceled and the data accumulated during the sleep is transmitted to the logical link end. . The sleep count counting unit 31 counts the number of logical link terminations in sleep from the management information of the logical link terminations in sleep of the OLT, triggered by detection of sleep transition and sleep release. The count result is notified to the control determination unit 33.

  The sleep number counting unit 31 blocks the generation of the SLEEP frame in FIG. 5 for a fixed time simultaneously with the detection of the sleep transition. This fixed time is, for example, a time sufficient for the low power function of the external connection terminal unit 24 to transition from the valid state to the invalid state, that is, a time that can be regarded as the completion of the transition process from the low power mode to the normal mode. is there. As a result, the SLEEP frame is not transmitted to the logical link end until a certain time elapses. Therefore, low power processing with a relatively long transition time from the valid state of the low power function to the invalid state is performed by the external connection terminal unit 24 or the external The buffer 14 can be applied as a low power mode.

<Function of Buffer ID Manager 32>
The buffer ID management unit 32 extracts the logical link termination identifier during the sleep transition processing and the sleep release processing from the management information of the logical link termination during sleep that the OLT has, and buffers each extracted logical link termination identifier. A function for assigning an ID is provided. The buffer ID assigned to the logical link termination identifier is notified from the buffer ID management unit 32 to the management table provided in the buffer access control unit 21 of the input / output data processing unit 20. The buffer ID management unit 32 includes an external buffer usage monitoring counter that counts the number of buffer IDs whose buffer ID number is greater than V, and notifies the control determination unit 33 of the count result.

  The notification to the management table and the external buffer utilization monitoring counter operate according to the buffer ID allocation and buffer ID return flowcharts shown in FIGS. 10 to 12, and details will be described later. Note that the logical link termination during the sleep transition process is the logical link in which the sleep transition process has been started and the transition process has not yet been completed (the SLEEP frame in FIG. 5 has not been notified to the logical link end). Refers to the end. The term “logical link termination during sleep release processing” refers to a logical link termination in a state in which the sleep release processing is completed (a state in which DATA in FIG. 5 has been transmitted).

<Function of Control Determination Unit 33>
The control determination unit 33 controls the external connection terminal unit 24 and the external buffer 14 based on the value of the count result K notified from the sleep number counting unit 31 and the value of the count result G notified from the buffer ID management unit 32. It is determined whether the normal mode or the low power mode is suitable as the state, and the determination result is notified to the control instruction generator 34. The normal mode refers to a state in which the low power function of the external connection terminal and the external buffer is disabled and both data writing / reading to the external buffer 14 is possible. The low power mode refers to a state in which the low power function of the external connection terminal and the external buffer is validated and both data writing / reading to / from the external buffer 14 is impossible. The determination process of which control state is suitable is performed according to the determination flowchart shown in FIG. 13 triggered by the notification of the count result from the sleep count counting unit 31, and details will be described later.

<Function of Control Instruction Generating Unit 34>
Based on the determination result notified from the control determination unit 33, the control instruction generation unit 34 enables the external connection terminal unit 24 and the external buffer access control unit 23 to enable / disable the low power function of the external connection terminal and the external buffer. A control instruction is issued for invalidity and whether data can be written to / read from the external buffer 14. Although the instruction to the external connection terminal unit 24 and the external buffer access control unit 23 of the control instruction generation unit 34 is performed according to the instruction flowchart shown in FIG. 14, the details will be described later.

<Buffer ID allocation processing and buffer ID return processing>
FIG. 10 shows how the buffer ID management unit 32 assigns buffer IDs. FIG. 11 shows buffer ID allocation processing of the buffer ID management unit 32. FIG. 12 shows buffer ID return processing of the buffer ID management unit 32.

  The buffer ID management unit 32 assigns a buffer ID to each sleeping logical link termination identifier, and assigns a null buffer ID to all logical link termination identifiers that are not sleeping. The number of buffer IDs is the same as the total logical link termination number C of the OLT. The buffer ID allocation process is performed for each logical link termination identifier during the sleep transition process according to the flowchart of FIG. Similarly, the buffer ID return process is performed for each logical link termination identifier during the sleep release process according to the flowchart of FIG. However, if buffer ID allocation and return occur at the same time, return is prioritized. As shown in FIG. 10, the buffer ID assignment process assigns the buffer ID having the smallest buffer ID number from among the buffer IDs not assigned to the sleeping logical link termination identifier. Hereinafter, as shown in FIG. 10, a buffer ID number that is arranged and managed in ascending order is referred to as an ID number management unit.

  In FIG. 11, the buffer ID management unit 32 detects a sleep transition from the sleep control process of FIG. 5 (step T1), and extracts a logical link termination identifier during the sleep transition process (step T2). Next, the buffer ID assigned to the extracted logical link termination identifier is taken out from the ID number management unit (step T3). At this time, if the assigned buffer ID number is larger than V, it means that the external buffer 14 is used. Therefore, the external buffer usage monitoring counter provided for monitoring the usage status of the external buffer 14 is incremented by one ( Steps T4 and T5). The count result G (initial value is 0) of the external buffer usage monitoring counter is notified to the control determination unit 33. The extracted logical link termination identifier and the buffer ID extracted from the ID number management unit are notified to the buffer access control unit 21. The buffer access control unit 21 performs record management by associating the logical link end identifier with the buffer ID in the management table (step T6).

  In FIG. 12, the buffer ID management unit 32 detects the sleep release (step T7), and extracts the logical link termination identifier during the sleep release process (step T8). Next, based on the extracted logical link termination identifier, the corresponding buffer ID is determined from the management table of the buffer access control unit 21 (step T9). At this time, if the determined buffer ID is larger than V, it means that the external buffer 14 is used, so the external buffer utilization monitoring counter is decremented by −1 (steps T10 and T11). The determined buffer ID is returned to the ID number management unit (step T12). After returning the buffer ID to the ID number management unit, the buffer access control unit 21 is notified so that the buffer ID corresponding to the logical link termination identifier recorded and managed in the management table is the null buffer ID, and the management table Records are managed (step T13). The ID number management unit arranges the ID numbers in ascending order (step T14).

<Determination process of the control determination unit 33>
FIG. 13 shows a determination process between the normal mode and the low power mode in the control determination unit 33.
In FIG. 13, the control determination unit 33 performs a determination process every time the count result K is notified from the sleep number counting unit 31. The determination result is either the normal mode or the low power mode. The initial state is the low power mode.

  First, a case where the low power mode is determined will be described. The low power mode is a state in which all the low power functions of the external connection terminal and the external buffer are validated and only the internal buffer 13 is used, and a state in which data writing / reading to the external buffer 14 is impossible. The count result K is received from the sleep number counting unit 31 (step S1). When the count result K is less than the threshold value V (the upper limit value of the number of logical link terminations capable of storing data addressed to the logical link termination that is sleeping only with the internal buffer) (step S2: Yes), the internal buffer 13 is sleeping only. This means that the capacity necessary for the number K of logical link terminations can be secured, and it is not necessary to use the external buffer 14. However, even if K is less than the threshold value V, there may be a sleeping logical link termination that is writing data to the external buffer 14. Therefore, the control determination unit 33 receives the count result G of the external buffer use monitoring counter from the buffer ID management unit 32 (step S3), and writes the data from the G value to the external buffer 14 during sleep. It is determined whether or not a termination exists (step S4). If G is 0, it indicates that there is no sleeping logical link termination that is writing data to the external buffer 14, and therefore the control determination unit 33 determines the low power mode (step S6).

  Next, the case where it determines with normal mode is demonstrated. If K is equal to or greater than the threshold value V, or K is less than the threshold value V and G is equal to or greater than 1, it indicates that it is necessary to use the external buffer 14. Therefore, if K is greater than or equal to the threshold value V, or K is less than the threshold value V and G is greater than or equal to 1, the low power function of the external connection terminal and the external buffer is invalidated, and normal writing / reading to the external buffer 14 is possible. The mode is determined (step S5).

  After the determination in steps S5 and S6, the control determination unit 33 notifies the control instruction generation unit 34 of the determination result (step S7).

<Instruction Processing of Control Instruction Generating Unit 34>
FIG. 14 shows a control instruction process for the low power function in the control instruction generator 34.
In FIG. 14, every time the determination result is notified from the control determination unit 33, the control instruction generation unit 34 gives the external connection terminal unit 24 and the external buffer access control unit 23 the low power of the external connection terminal and the external buffer. A control instruction is made to enable / disable the function and whether to write / read data to / from the external buffer 14. The determination result from the control determination unit 34 is either the normal mode or the low power mode. In FIG. 14, in any control state, whether or not the previous control state (control state based on the determination result notified from the previous control determination unit) was the low power mode (steps I1 and I2). The contents of instructions to the external connection terminal unit 24 and the external buffer access control unit 23 are changed.

  Processing when the previous control state is the low power mode (step I2: Yes) and the determination result notified from the control determination unit 33 is the normal mode (step I8: No) will be described. Since the previous determination result is the low power mode, in order to set to the normal mode, the control instruction generation unit 34 invalidates the low power function of the external connection terminal and the external buffer, and writes / reads to / from the external buffer 14. It is necessary to give control instructions that enable Therefore, the control instruction generating unit 34 first gives a control instruction (hereinafter referred to as “external buffer use prohibition instruction”) that disables writing / reading to / from the external buffer 14 to the external buffer access control unit 23 (step S31). I9), in order to invalidate the low power function of the external connection terminal and the external buffer on the external connection terminal unit 24 and the external buffer access control unit 23, the low power function of the external connection terminal and the external buffer is provided. A control instruction to be invalidated (hereinafter referred to as “low power invalidation instruction”) is issued (step I10). Next, the control instruction generation unit 34 waits for a sufficient time for the low power function of the external connection terminal unit 24 to transition from the valid state to the invalid state (step I11). A control instruction (hereinafter referred to as “external buffer use permission instruction”) is issued to permit writing / reading of the external buffer (step I12).

  When the previous control state is the low power mode (step I2: Yes) and the determination result notified from the control determination unit 33 is the low power mode (step I8: Yes), the low power function is originally provided. Since it is valid, the control instruction generation unit 34 maintains the state without changing the control instruction to the external connection terminal unit 24 and the external buffer access control unit 23 (step I13).

  Processing when the previous control state is not the low power mode (step I2: No) and the determination result notified from the control determination unit 33 is the normal mode (step I3: Yes) will be described. If the previous determination result is not the low power mode, the low power function of the external connection terminal and the external buffer is originally disabled, so the control instruction generation unit 34 controls the external connection terminal unit 24 and the external buffer access control. The low power invalidation instruction to the unit 23 is maintained (step I6), and an external buffer use permission instruction is issued to the external buffer access control unit 23 (step I7).

  Further, when the previous control state is not the low power mode (step I2: No) and the determination result notified from the control determination unit 33 is the low power mode (step I3: No), the control instruction generation unit 34 First, an external buffer use prohibition instruction is given to the external buffer access control unit 23 (step I4). Thereafter, a control instruction is issued to enable the low power function of the external connection terminal and the external buffer to the external connection terminal unit 24 and the external buffer access control unit 23 (step I5).

  The above is the configuration and operation of the input / output data processing unit 20 and the low power function control unit 30 in the present embodiment. The sleep count counting unit 31, the buffer ID management unit 32, the control determination unit 33, and the control instruction generation unit 34 are not necessarily implemented by hardware, and some or all of them may be implemented by software. Further, the low power function of the external connection terminal unit 24 and the external buffer 14 is variously changed within a range not departing from the gist of the invention, in addition to shutting off the power supply to the external connection terminal and using the low power function of the external buffer 14. Is possible.

  In addition to the sleep control process of FIG. 5, the present embodiment can be applied with various modifications without departing from the gist of the PON system having the sleep control process of the logical link termination.

ONU subscriber side device OLT station side device 11 optical splitter 12 optical fiber transmission line 13 internal buffer 14 external buffer 15 buffer control device 20 input / output data processing unit 21 buffer access control unit 21
22 internal buffer access control unit 23 external buffer access control unit 24 external connection terminal unit 30 low power function control unit 31 sleep count counting unit 32 buffer ID management unit 33 control determination unit 34 control instruction generation unit

Claims (13)

A station side of a PON (Passive Optical Network) system in which a plurality of subscriber-side devices and a station-side device are connected one-to-one via a logical link, and the plurality of subscriber-side devices have a logical link termination sleep control process. A buffer management method for managing a first buffer and a second buffer that consumes more power than the first buffer in the apparatus,
For data destined for logical link terminations of the plurality of subscriber side devices, it is determined whether or not the logical link termination is sleeping, and when the logical link termination during which the data is sleeping is destined, When the data is stored in either the first buffer or the second buffer, and the destination is a logical link end where the data is not in sleep, the data is stored in the first buffer. A characteristic buffer management method. The buffer management method according to claim 1,
Based on the management information of the logical link termination during sleep of the station side device, the number of logical link terminations K during sleep is counted, and the data is stored when the number of logical link terminations K during sleep is greater than or equal to a threshold value. A buffer management method, wherein the data is stored in either the first buffer or the second buffer, and the data is stored only in the first buffer when the number of terminating logical links K during sleep is less than a threshold value. . The buffer management method according to claim 2, wherein
Information G indicating the presence or absence of data destined for the end of the sleeping logical link stored in the second buffer;
When the number of logical link terminations K during sleep is equal to or greater than the threshold value or the information G is present, the normal mode for disabling the low power function of the second buffer is set, and the number of logical link terminations K during sleep A buffer management method comprising: setting a low power mode to enable a low power function of the second buffer when the information G is less than the threshold value and the information G indicates none. The buffer management method according to claim 3, wherein
When the number K of logical link terminations during sleep is equal to or greater than the threshold value, the station side apparatus determines that the transition processing from the low power mode to the normal mode is complete, and then the station side device starts the sleep transition processing. A buffer management method characterized by notifying the end. In the buffer management method according to any one of claims 2 to 4,
The threshold value is 1. A buffer management method, wherein: In the buffer management method according to any one of claims 1 to 5,
Division in which at least a part of each of the first buffer and the second buffer is divided as a logical link termination unit and managed as a divided region, and data destined for the sleeping logical link termination is accumulated. A buffer management method comprising: preferentially determining a divided area of the first buffer as a region by a predetermined allocation method and storing the data. The buffer management method according to claim 6, wherein
The predetermined allocation method is:
If the data is destined for the end of a sleeping logical link,
If the divided area has already been assigned to the logical link terminal that is the destination of the data, the data is accumulated in the divided area,
If the divided area is not assigned to the logical link end, and if there is a divided area not assigned to another logical link end in the first buffer, the divided area is assigned to the logical link end;
If the divided area is not assigned to the logical link end and there is no unassigned divided area to the other logical link end in the first buffer, it is not assigned to the other logical link end of the second buffer. And give
A buffer management method characterized in that, when the destination is a logical link end where the data is not in sleep, the divided area assigned to the logical link end is not assigned. The buffer management method according to claim 7, wherein
The predetermined allocation method is:
The buffer management method according to claim 1, wherein, when the destination is a logical link terminal where the data is not in sleep, the data is divided into priorities and accumulated in a region other than the divided region in the first buffer. In the buffer management method in any one of Claims 6-8,
The predetermined allocation method is:
A division region identifier (buffer ID) uniquely determined in advance for each division region is associated with a logical link termination identifier uniquely determined in advance for the logical link termination, and the assignment is performed on the logical link termination identifier. A buffer management method characterized by allocating a buffer ID of the divided area, and allocating a null buffer ID to the logical link termination identifier when unassigned. A station side of a PON (Passive Optical Network) system in which a plurality of subscriber-side devices and a station-side device are connected one-to-one via a logical link, and the plurality of subscriber-side devices have a logical link termination sleep control process. A buffer management device for managing a first buffer and a second buffer that consumes more power than the first buffer;
Control means for determining whether or not the logical link termination is in a sleep state for data destined for the logical link termination of the plurality of subscriber side devices;
When the data is destined for the logical link end in the sleep state, the data is stored in either the first buffer or the second buffer, and the logical link end is not in the sleep state. In this case, a buffer management device comprising: input / output data processing means for storing the data in the first buffer. The buffer management device according to claim 10, wherein
The control means counts the number of logical link terminations K during sleep based on the management information of the logical link terminations during sleep that the station side device has, and when the number of logical link terminations K during sleep is equal to or greater than a threshold value The data is accumulated in either the first buffer or the second buffer, and the data is accumulated only in the first buffer when the number of terminating logical links K during sleep is less than a threshold. A buffer management device characterized in that it is configured to control an entry output data processing means. The buffer management device according to claim 11, wherein
The control means has information G indicating the presence / absence of data stored in the second buffer and destined for the logical link termination during sleep, and the number K of logical link termination during sleep is equal to or greater than the threshold value. Alternatively, when the information G indicates the presence, the normal mode for disabling the low-power function of the second buffer is set, and the number of logical link terminations K during the sleep is less than the threshold and the information G indicates the absence In addition, the buffer management device is configured to control the input / output data processing means so as to be in a low power mode that enables a low power function of the second buffer. The buffer management device according to claim 12,
When the number of logical link terminations in the sleep is equal to or greater than the threshold, the control unit considers that the transition process from the low power mode to the normal mode is complete, and then the station side device starts the sleep transition process. The buffer management device is characterized in that the logical link termination is notified to the logical link terminal.

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