JP2010539588A - Memory sharing and data distribution - Google Patents

Abstract

A copy of the software tool computing process is instantiated on the master computing device and on a remote computing device that is separate from the master computing device. The primary instantiation of the computing process employs a data block resource manager that can store data in the memory of the master computing device and retrieve data therefrom. Each remote installation of the computing process employs a remote data client, while a remote data server is instantiated on each remote computing device. A remote instantiation of the computing process instructs its associated remote data client to request data when it needs access data. If the data is managed by another remote computing process, the remote data client will request data from a remote data server associated with that remote computing process.

Description

(Related application)
This application is US Provisional Patent Application No. 60 / 971,264 (named “Memory Sharing And Data Distribution”, filed on Sep. 11, 2007) by inventor Laurence Grodd et al. This application is hereby incorporated by reference in its entirety. This application is also related to US Patent Application No. 11 / 396,929 (named “Distribution Of Parallel Operations”, filed April 12, 2006) by inventor Laurence Grodd et al. Incorporated herein by reference.

(Field of Invention)
The present invention is directed to the use of shared and distributed memory within a parallel processing network. Various implementations of the invention may have particular application to the use of shared and distributed memory for storing design data for use by electronic design automation software tools operating within a parallel processing network.

  Many software applications can be efficiently executed on a single processor computer. However, some software applications have many operations and cannot be executed continuously on a single processor computer in an economical time. For example, a microdevice (eg, integrated circuit) design process software application may require execution of more than 100,000 operations based on hundreds of thousands or hundreds of millions of input data values. In order to execute these types of software applications more quickly, computers have been developed that employ multiple processors that can simultaneously use multiple processing threads. Although these computers can execute complex software applications more quickly than single processor computers, these multiprocessor computers are very expensive to purchase and maintain. In the case of a multiprocessor computer, the processor must execute a number of operations simultaneously, and thus employ a special operating system to coordinate the parallel execution of related operations. Furthermore, the bus structure and physical layout of a multiprocessor computer is inherently more complex than a single processor computer because the multiple processors can simultaneously retrieve access to resources such as memory.

  In view of the difficulties and costs associated with large multiprocessor computers, a network of linked single processor computers has become a popular alternative to the use of single multiprocessor computers. The cost of conventional single processor computers, such as personal computers, has decreased significantly over the past few years. In addition, techniques for linking the operations of multiple single processor computers to a network have become more sophisticated and reliable. Thus, multi-million dollar multiprocessor computers are now typically being replaced by relatively simple and low cost single processor computer networks or “farms”.

  The transition from a single multiprocessor computer to multiple networked single processor computers is particularly useful when the data being processed has parallel processing. For these types of data, one part of the data is independent of another part of the data. That is, manipulation of the first portion of data does not require knowledge of or access to the second portion of data. Thus, one single processor computer can perform operations on a first portion of data while another single processor computer can simultaneously perform the same operation on a second portion of data. By using multiple computers to perform the same operation on different data groups simultaneously, ie “in parallel”, large amounts of data can be processed quickly. Such use of multiple single processor computers is particularly beneficial for analyzing circuit design data using electronic design automation (EDA) tools. For this type of data, part of the design, such as the semiconductor gate, in the first region of the microcircuit is completely independent of another part of the design, such as the wiring line in the second region of the microcircuit. May be. Thus, some electronic design automation operations, such as operations that define minimum width confirmation of structures, can be performed by one computer for gates, while other computers perform the same operations for wiring lines. Execute.

  Although parallel processing substantially reduces the time required to run electronic design automation software tools, many of these tools still require large amounts of system memory. For example, an electronic design automation software tool may initiate several instantiations of a computing process on a single “master” computing device so that each instantiation can perform operations in parallel with each other. Alternatively, or in addition, the electronic design automation software tool can similarly make several copies of the computing process on multiple “remote” computing devices so that each instantiation can perform operations in parallel with each other. May be instantiated. For conventional parallel processing systems, each instantiation will require its own copy of the data required to perform its assigned operation. For example, if a parallel processing system is used to implement an electronic design automation software tool calculation process for processing layout design data, data for a single layer of an integrated circuit design may be used in multiple processes of the calculation process. May be replicated several times in the memory of the master computing device for use by instantiation. Still further, data may be replicated on multiple remote computing devices for use by instantiation of computing processes on those remote computing devices as well.

  Advantageously, various aspects of the present invention allow multiple instantiations of a software tool calculation process (such as the calculation process of an electronic design automation software tool) running on a single master computing device, The present invention relates to a technique for sharing data stored in a memory. Another aspect of the invention is directed to allowing multiple instantiations of a software tool computing process running on multiple remote computing devices and employing data distributed among those remote computing devices.

  According to various embodiments of the invention, copies of a plurality of software tool calculation processes, such as an electronic design automation software tool calculation process, are instantiated on a master computing device. Each instantiation of the computing process includes or otherwise employs a data block manager configured to request data needed by the computing process. Also, the primary instantiation of the computing process includes or otherwise employs a data block resource manager that can store and read data in the memory of the master computing device. For various embodiments of the present invention, the memory is a “fast” memory provided by an integrated circuit memory device operating adjacent to the processing unit of the master computing device, a “slow” memory provided by a magnetic or optical disk. Or some combination thereof. When an instantiation of a computational process requires access to data, it instructs its associated data block manager to request data from the data block resource manager. In response, the data block resource manager reads data from the memory of the master computing device and provides it to the requesting data block manager for use by the computing process. Similarly, if the calculation process requires data storage, it instructs its associated data block manager to provide the data to the data block resource manager. In response, the data block resource manager stores data in the memory of the master computing device.

  In yet another embodiment of the invention, one or more versions of the software tool computing process are instantiated on the master computing device and on separate remote computing devices. Each remote instantiation of the computing process involves or otherwise employs a remote data client. A remote data server (or remote data block resource manager) is also instantiated on each remote computing device. Similar to the data block resource manager, the remote data server can store data in and retrieve data from the memory of the remote computing device. Also, as is the case for the memory for the master computing device, the memory for the remote computing device is a “fast” memory, magnetic, provided by an integrated circuit memory device that operates adjacent to the processing unit of the remote computing device. Or “slow” memory provided by an optical disc, or some combination thereof.

  When a remote instantiation of a computing process requires access to access data, it instructs its associated remote data client to request the data. If the data is managed by another remote computing process, the remote data client will request data from a remote data server associated with that remote computing process. Alternatively, if the data is managed by a computing process on the master computing device, the remote data client will request data from the data block manager associated with that master computing process. As described above, the data block manager may in turn obtain data through the data block resource manager associated with the main computing process on the master computing device. Similarly, if a remote computing process requires storage of data, its associated to provide data to the appropriate remote data server or data block resource manager for storage in the corresponding memory. Command the remote data client. For various embodiments of the present invention, the data block manager, remote data client, and remote data server use a suitable network communication protocol such as Transmission Control Protocol / Internet Protocol (TCP / IP) or User Datagram Protocol. May be interconnected by an electronic communication network.

  These and other features and aspects of the present invention will become apparent upon consideration of the following detailed description.

FIG. 1 is a schematic diagram of a multiprocessor computer linked to a network of single processor computers that may be employed by various embodiments of the present invention. FIG. 2 is a schematic diagram of a processor unit for a computer that may be employed by various embodiments of the invention. FIG. 3 is a schematic diagram of an offset map for mapping an offset for identifying each 16 kB memory block constituting the data set. FIG. 4 is a schematic diagram illustrating an embodiment of a parallel processing computing system capable of sharing data among various processes of a master computing device in accordance with various embodiments of the present invention. FIG. 5 is a table representing operations that may be performed by various embodiments of the present invention. FIG. 6 is a schematic diagram illustrating an embodiment of a parallel processing computing system that can share data between different processes of a master computing device, in accordance with various embodiments of the present invention. 7 and 8 show the data format for reading and transmitting a block of data. 7 and 8 show the data format for reading and transmitting a block of data.

(Introduction)
Various embodiments of the present invention relate to tools and methods for distributing segments of data among a plurality of computational threads for conversion from a first format to a second format. Thus, aspects of some embodiments of the present invention have particular application to the distribution of data segments between computing networks, including at least one multiprocessor master computer and multiple single processor slave computers. In order to make these implementations easier to understand, an example of a network that links a multiprocessor master computer to a plurality of single processor slave computers is discussed.

(Example operating environment)
Implementation of a software tool (such as an electronic design automation software tool) according to various embodiments of the invention is implemented using computer-executable software instructions executed by one or more programmable computing devices. Also good. Since these examples of the invention may be implemented using software instructions, the components and operations of a general purpose programmable computer system in which various embodiments of the invention may be employed are first described. More specifically, the components and operations of a computer network having a host or master computer and one or more remote or slave computers will be described with reference to FIG. However, this operating environment is merely one example of a suitable operating environment and is not intended to suggest any limitation as to the scope of use or functionality of the invention.

  In FIG. 1, the master computer 101 is a multiprocessor computer that includes a plurality of input and output devices 103 and a memory 105. Input and output device 103 may include any device for receiving input data from a user or providing output data to a user. Examples of the input device include a keyboard, a microphone, a scanner, and a pointing device for receiving input from a user. The output device can then include a display monitor, speaker, printer, or haptic feedback device. These devices and their connections are well known in the art and will not be discussed in detail here.

  Similarly, memory 105 may be implemented using any combination of computer readable media accessible by master computer 101. Computer readable media include, for example, read / write memory (RAM), read only memory (ROM), read only memory (EEPROM) capable of electronic erasure and programming, or microcircuit memory devices such as flash memory microcircuit devices, CD- A ROM disk, a digital video disk (DVD), or other optical storage device. Also, as a computer readable medium, a magnetic cassette, magnetic tape, magnetic disk, or other magnetic storage device, perforated medium, holographic storage device, or any other that can be used to store desired information Medium.

  As detailed below, the master computer 101 executes a software application for performing one or more operations in accordance with various embodiments of the invention. Thus, the memory 105 stores software instructions 107A that implement a software application for performing one or more operations during execution. The memory 105 also stores data 107B that is used in combination with the software application. In the illustrated embodiment, data 107B contains process data that a software application uses to perform operations, at least some of which can be performed in parallel.

The master computer 101 includes a plurality of processor units 109 and an interface device 111. The processor unit 109 may be any type of processor device that is programmable to execute the software instructions 107A, but is conventionally a microprocessor device. For example, one or more of the processor units 109 may be a commercially available general purpose program such as an Intel® Pentium® or Xeon ^™ microprocessor, an Advanced Micro Devices Athlon ^™ microprocessor, or a Motorola 68K / Coldfire microprocessor. It may be a possible microprocessor. Alternatively or additionally, one or more of the processor units 109 may be a specially manufactured processor such as a microprocessor designed to optimally perform a particular type of mathematical operation. The interface device 111, the processor unit 109, the memory 105, and the input / output device 103 are connected together by a bus 113.

  In some implementations of the invention, the master computing device 101 may employ one or more processing units 109 having two or more processor cores. Thus, FIG. 2 illustrates an example of a multi-core processor unit 109 that may be employed with various embodiments of the present invention. As can be seen from this figure, the processor unit 109 includes a plurality of processor cores 201. Each processor core 201 includes a calculation engine 203 and a memory cache 205. As is well known to those skilled in the art, the computation engine includes logic devices for performing various computational functions, such as retrieving software instructions and then performing actions specified in the retrieved instructions. These actions include, for example, addition, subtraction, multiplication, number comparison, execution of logical operations such as AND, OR, NOR, and XOR, and reading of data. Each computation engine 203 may then use its corresponding memory cache 205 to quickly store and retrieve data and / or instructions for execution.

Each processor core 201 is connected to an interconnect 207. The particular structure of interconnect 207 may vary depending on the architecture of processor unit 201. For some processor units 201 such as cell microprocessors manufactured by Sony Corporation, Toshiba Corporation, and IBM Corporation, interconnect 207 may be implemented as an interconnect bus. However, in the case of other processor units 201 such as the Opteron ^™ and Athlon ^™ Alcore processors commercially available from Advanced Micro Devices (Sunnyvale, California), interconnect 207 may be implemented as a system request interface device. In any case, the processor core 201 communicates with the input / output interface 209 and the memory controller 211 through the interconnect 207. The input / output interface 209 provides a communication interface between the processor unit 201 and the bus 113. Similarly, the memory controller 211 controls information exchange between the processor unit 201 and the system memory 107. In some implementations of the invention, the processor unit 201 may include additional components such as accessible high level cache memory shared by the processor core 201.

  Although FIG. 2 illustrates one example of a processor unit 201 that may be employed by some embodiments of the present invention, it should be understood that this example is only representative and is not intended to be limiting. . For example, some embodiments of the present invention may employ a master computer 101 having one or more cell processors. The cell processor employs a plurality of input / output interfaces 209 and a plurality of memory controllers 211. The cell processor also has nine separate processor cores 201 of different types. More specifically, it has six or more synergistic processor elements (SPE) and power processor elements (PPE). Each synergistic processor element includes a vector-type computation engine 203 with 128 × 128-bit registers, four single-precision floating-point computation units, four integer computation units, and a 256 KB local store for both instructions and data. And a storage memory. The power processor element then controls the tasks performed by the synergistic processor element. Because of its configuration, the cell processor is substantially faster than many conventional processors and can perform some mathematical operations such as fast Fourier transform (FFT) calculations.

  Referring back to FIG. 1, the interface device 111 causes the master computer 101 to communicate with the slave computers 115A, 115B, 115C,... 115x through the communication interface. The communication interface may be any suitable type of interface including, for example, a conventional wired network connection or a light transmissive wired network connection. The communication interface may be a wireless connection such as a wireless optical connection, a radio frequency connection, an infrared connection, or an acoustic connection. The interface device 111 transmits data and control signals from each of the master computer 101 and the slave computer 115 to one or more communications such as a transmission control protocol (TCP), a user datagram protocol (UDP), and an Internet protocol (IP). Convert to network message according to protocol. These and other conventional communication protocols are well known in the art and will not be discussed in detail here.

Each slave computer 115 may include a memory 117, a processor unit 119, an interface device 121, and optionally one or more input / output devices 123 connected together by a system bus 125. As with master computer 101, optional input / output device 123 for slave computer 115 includes any conventional input or output device such as a keyboard, pointing device, microphone, display monitor, speakers, and printer. But you can. Similarly, the processor unit 119 may be any type of conventional or specially manufactured programmable processor device. For example, one or more of the processor units 119 may be an Intel® Pentium® or Xeon ^™ microprocessor, an Advanced Micro Devices Athlon ^™ microprocessor, or a Motorola 68K / Coldfire® microprocessor, etc. It may be a commercially available general-purpose programmable microprocessor. Alternatively, one or more of the processor units 109 may be specially manufactured processors such as microprocessors designed to optimally perform certain types of mathematical operations.

  Further, one or more of the processor units 119 may have two or more cores as described above with reference to FIG. For example, in some implementations of the invention, one or more of the processor units 119 may be a cell processor. The memory 117 may then be implemented using any combination of the computer readable media described above. Similar to the interface device 111, the interface device 121 causes the slave computer 115 to communicate with the master computer 101 via a communication interface.

  In the illustrated embodiment, the master computer 101 is a multiprocessor unit computer having a plurality of processor units 109, while each slave computer 115 has a single processor unit 119. However, it should be noted that alternative implementations of the present invention may employ a master computer having a single processor unit 109. Further, one or more of the slave computers 115 may have multiple processor units 119 depending on the intended use. Also, although only a single interface device 111 is shown for the host computer 101, in an alternative embodiment of the present invention, the computer 101 communicates with the remote computer 115 via multiple communication interfaces. Note that two or more different interface devices 111 may be used to do this.

  In various embodiments of the present invention, the master computer 101 may be connected to one or more external data storage devices. These external data storage devices may be implemented using any combination of computer readable media accessible by the master computer 101. Computer readable media include, for example, read / write memory (RAM), read only memory (ROM), read only memory (EEPROM) capable of electronic erasure and programming, or microcircuit memory devices such as flash memory microcircuit devices, CD- A ROM disk, a digital video disk (DVD), or other optical storage device. Computer-readable media also include magnetic cassettes, magnetic tapes, magnetic disks, or other magnetic storage devices, perforated media, holographic storage devices, or any other media that can be used to store desired information. It is done. According to some implementations of the invention, one or more of slave computers 115 may alternatively or additionally be connected to one or more external data storage devices. Typically, these external data storage devices include data storage devices that are also connected to the master computer 101, but they may be different from any data storage devices accessible by the master computer 101.

(Calculation)
As mentioned above, various aspects of the invention may be implemented to support execution of operations by a computing system having a multiprocessor architecture. Thus, different embodiments of the present invention can be employed with a variety of different types of software applications. However, some embodiments of the present invention are particularly useful in conjunction with electronic design automation software tools that perform operations to simulate, verify, or modify design data representing microdevices such as microcircuits. There may be. The design and manufacture of microcircuit devices has many steps during the “design flow” process. These steps are highly dependent on the type of microcircuit, its complexity, design team, and microcircuit manufacturer or factory. Some steps are common to the entire design flow. Initially, the design specification is typically logically modeled in a hardware design language (HDL). The software and hardware “tools” then validate the design and correct errors at various stages of the design by running a software simulator and / or hardware emulator.

  After the logical design is deemed satisfactory, it is converted into physical design data by synthesis software. The physical design data may represent a geometric pattern that is written onto a mask used to produce a desired microcircuit device, for example, in a photolithography process at a manufacturing plant. It is very important that the physical design information accurately embodies the design specifications and logical design for proper operation of the device. Furthermore, since the physical design data is employed to create a mask for use in a manufacturing plant, the data must conform to the manufacturing plant requirements. Each manufacturing plant specifies its own physical design parameters for compliance with their processes, equipment, and technology. Thus, the design flow may include a design rule check process. During this process, the physical layout of the circuit design is compared with the design rules. In addition to the rules specified by the manufacturing plant, the design rule checking process checks the physical layout of the circuit design against other design rules, such as rules derived from test chips, general industry knowledge, etc. Is also possible.

  When the designer uses a verification software application to verify that the physical layout of the circuit design complies with the design rules, the designer modifies the physical layout of the circuit design, and the physical layout becomes a photolithography process. You may improve the resolution of the image brought about in this case. These resolution enhancement techniques (RET) include physical layout modifications using, for example, optical proximity correction (OPC) or by adding sub-resolution assist features (SRAF). When the physical layout of the circuit design is modified using resolution enhancement techniques, a design rule check may be performed on the modified layout and the process is repeated until the desired degree of resolution is obtained. . Examples of such simulation and verification tools are disclosed in McSherry et al. US Pat. No. 6,230,299, issued May 8, 2001, and McSherry et al. US Pat. No. 6,249,903, U.S. Pat. No. 6,339,836 issued to Eisenhofer et al. Issued on Jan. 15, 2002, U.S. Pat. No. 6,397,372 issued to Bozkus et al. Issued May 28, 2002. US Pat. No. 6,415,421 issued to Anderson et al. Issued July 2, 2002, and US Pat. No. 6,425,113 issued to Anderson et al. Issued July 23, 2002. Each of which is incorporated herein by reference.

  New integrated circuit designs may include interconnections of millions of transistors, resistors, capacitors, or other electrical structures into logic circuits, memory circuits, programmable field arrays, and other circuit devices. Good. To make it easier for computers to create and analyze these large data structures (and to allow human users to better understand these data structures), they are often referred to as “cells”. Hierarchically organized into smaller data structures. Thus, for a microprocessor or flash memory design, all of the transistors that make up the memory circuit for storing a single bit may be classified as a single “bit memory” cell. Thus, rather than having to enumerate each transistor individually, the group of transistors that make up a single bit memory circuit are collectively referred to as a single unit and can be manipulated as such. Similarly, design data describing a larger 16-bit memory register circuit can be classified into a single cell. This high-level “register cell” may then include 16-bit memory cells along with design data describing various other circuits such as input / output circuits for exchanging data with each of the bit memory cells. . Similarly, the design data describing the 128 kB memory array, together with design data describing its own various circuits, such as input / output circuits that exchange data with each of the register cells, is only 64,000. It can be simply described as a combination of register cells.

  By classifying microcircuit design data into hierarchical cells, large data structures can be processed more quickly and efficiently. For example, circuit designers typically analyze a design to ensure that each circuit feature described in the design conforms to design rules specified by the manufacturing plant that produces the microcircuit from that design. To. In the embodiment described above, instead of having to analyze each feature of the entire 128 kB memory array, the design rule check process can analyze the features of a single bit cell. The result of the check can then be applied to all of the single bit cells. Once it is determined that one instance of a single bit cell complies with the design rules, the design rule check process can add its various additional features (which can themselves constitute one or more hierarchical cells). The analysis of the register cell can be completed simply by analyzing the characteristics of the circuit. The result of this check can then be applied to all of the register cells. Once one instance of a register cell is confirmed to comply with the design rules, the design rule check software application can analyze the entire 128 kB memory array by simply analyzing the additional various circuit features in the memory array. Analysis can be completed. Thus, analysis of large data structures can be compressed into analysis of cells that make up a relatively small number of data structures.

  Typically, the physical design data for a microcircuit will include two different types of data: “drawing layer” design data and “derived layer” design data. The drawing layer data describes a polygon drawn in the layer of material forming the microcircuit. The drawing layer data will typically include polygons in the metal layer, diffusion layer, and polysilicon layer. The derived layer will then include features composed of a combination of drawing layer data and other derived layer data. For example, for the transistor gate described above, the derived layer design data describing the gate would be derived from the intersection of the polygon in the polysilicon material layer and the polygon in the diffusion material layer.

  For example, a design rule check software application will perform two types of operations (a “check” operation to check whether the design data values conform to specified parameters, and a “derivation” operation to generate derivation layer data. ). Therefore, the transistor gate design data may be generated by the following derivation operation.

gate = diff AND poly
The result of this operation will identify all intersections between the diffusion layer polygon and the polysilicon layer polygon. Similarly, a p-type transistor gate formed by doping a diffusion layer with an n-type material is identified by the following derivation operation.

pgate = nwell AND gate
The result of this operation will then identify all transistor gates that have doped the polygon in the diffusion layer with n-type material (ie, the intersection of the polysilicon layer polygon and the diffusion layer polygon).

  The check operation will then define a parameter or parameter range for the data design value. For example, the user may wish to ensure that no metal wiring line is within 1 micron of another wiring line. This type of analysis may be performed by the following check operation.

external metal <1
The result of this operation will identify each polygon in the metal layer design data that is closer than 1 micron to another polygon in the metal layer design data.

  Further, although the above-described calculation employs drawing layer data, the check calculation may be similarly performed on the derived layer data. For example, if the user wishes to verify that no transistor gate is located within 1 micron of another gate, the design rule check process may include the following check operations:

external gate <1
The result of this operation will identify all gate design data representing a gate located less than 1 micron from another gate. However, it should be understood that this check operation cannot be performed until a derivation operation for identifying the gate from the drawing layer design data is performed.

  Table 1 describes an example of a circuit analysis process in pseudocode. An example of such a flow may be implemented using the Calibre family, a commercially available electronic design tool from Mentor Graphics Corporation (Wilsonville, Oregon). In particular, Table 1 shows an algorithm for inserting “dummy” geometric data (typically a rectangle) that is added to a layer in the design to achieve the desired amount of structural density per unit area. List the flows.

したがって、このフローは、アルゴリズムによって採用される一連の入力を指定する。特に、電子設計自動化ツールの場合、入力データが読み出されるデータベース（すなわち、ｉｎ．ｇｄｓ）、ＧＤＳＩＩデータフォーマットで電子設計自動化ツールに読み込まれる特定のレイアウト設計（すなわち、「ＧＤＳＩＩ」と称される回路設計）、および設計内の主要セル（すなわち、「Ｔｏｐｃｅｌｌ」と称されるセル）を識別する。

This flow thus specifies a set of inputs that are employed by the algorithm. In particular, in the case of an electronic design automation tool, a database from which input data is read (ie, in.gds), a specific layout design that is read into the electronic design automation tool in the GDSII data format (ie, a circuit design called “GDSII”) ), And the primary cell in the design (ie, the cell referred to as “Topcell”).

(Data organization)
As discussed in more detail below, various implementations of the invention transfer data to various computing processes executing on a master computing device, one or more remote computing devices, or both. Thus, for various implementations of the present invention, the software tool is configured to process data in blocks of a defined size. For example, in some implementations of the invention, the software tool may be configured to read, transfer, and store data in a 16 kilobyte block. More specifically, as discussed in more detail below, various implementations of the invention employ a data block resource manager to store and retrieve data from the memory of the master computing device. For various embodiments of the present invention, the memory is a “fast” memory provided by an integrated circuit memory device operating adjacent to the processing unit of the master computing device, a “slow” memory provided by a magnetic or optical disk. Or some combination thereof.

  The data block resource manager may generate a single file on a disk, such as a magnetic disk employed in a conventional hard drive storage device, for example. This file is divided into 16 kB blocks and can be expanded by the data block resource manager as needed. As discussed in more detail below, the data block resource manager may use DBLOCK ID to access a data set associated with memory (as used herein, the term “access” , Used to encompass operations for reading data from memory or storing data in memory). The data set may include one or more actual 16 kB block files. In this case, the DBLOCK ID refers to an offset map that maps offsets that identify each 16 kB memory block that makes up the data set, as illustrated in FIG. As will be appreciated by those skilled in the art, two DBLOCK IDs should not refer to the same file offset.

  However, it should be understood that a typical related data set may not be some integer quantity of 16 kB. For example, in some implementations of the present invention, the software tool is an electronic design automation software tool such as the Calibre® family of software tools that are commercially available software products from Mentor Graphics Corporation (Wilsonville, Oregon). Also good. For these types of software tools, the associated data set may include a sequence of geometric elements from the layout design of the integrated circuit. If the size of the associated data set, such as a geometric sequence, exceeds 16 kB, all initial full 16 kB blocks of data are migrated to a “slow” memory storage device such as a magnetic disk and, as described above, a common DBLOCK ID May be referred to using A “drabble” that is always non-empty can then be stored in a “fast” or local remainder in memory.

  By using this array, it is possible for the data block resource manager to use the associated DBLOCK ID when retrieving access data. For example, when a data block resource manager needs to read a data set, it first identifies the DBLOCK ID associated with that data set. After identifying the associated DBLOCK ID, the data block resource manager starts reading data by 16 kB using the offset associated with the DBLOCK ID. After all of the data blocks to be read are read and processed, the data block manager reads and processes the remainder of “able” (which may be stored in local memory). The DBLOCK ID may then be identified for the next data set to be accessed. Thus, various implementations of the present invention reduce the amount of local memory used to store a data set without having to waste, for example, a portion of the 16 Kb block of memory on a hard disk storage device. Is possible.

(Shared data)
FIG. 4 illustrates an embodiment of a parallel processing computing system that can share data among various processes of a master computing device in accordance with various embodiments of the present invention. As can be seen from this figure, the parallel processing computing system 401 includes instantiations (0, 1,... N) of N + 1 number computing processes 403. More specifically, parallel processing computing system 401 includes a main computing process 403 ′ and N number of “pseudo” computing processes 403A-403x. In the illustrated implementation of the present invention, the calculation process 403 is an electronic design automation tool configured to operate on a hierarchical database (HDB) of integrated circuit design information. Also, as illustrated in this figure, each calculation process 403 includes (or employs otherwise) a data block manager 405. Each data block manager is configured to request or transmit data in response to instructions from its associated computing process 403.

  The main calculation process 403 ′ also includes a data block resource manager 407. The data block resource manager 407 can store data in and read data from the memory components of the master computing device. In the illustrated embodiment, the memory is provided by a “fast” or local memory 409, which can be provided by an integrated circuit memory device operating adjacent to the processing unit of the master computing device, and a magnetic or optical disk storage device. Both of the “slow” memory 411 are included. However, it is understood that for various implementations of the present invention, the data block resource manager 407 may be able to read data from or store data in any number of different storage sources. I want. For these implementations, the blocks in the DBLOCK ID are allocated from the same source, and the source should support the specified block allocation (eg, 16 Kb in the illustrated embodiment).

  The data block resource manager 407 includes a data block resource server 413 for each instantiation of the pseudo-calculation processes 403A-403x. Accordingly, the data block resource manager 407 includes a data block resource server 413A associated with the calculation process 403A, a data block resource server 413x associated with the calculation process 403x, and the like. In various implementations of the invention, each data block resource server 413 is dedicated to its corresponding calculation process 403. Also, for the illustrated implementation of the present invention, the main calculation process 403 ′ can interact directly with the data block resource manager 407 and needs the data block resource server 413 associated with the main calculation process 403 ′. Eliminate sex. However, for still other implementations of the invention, the main computation process 403 'may interact with the data block resource manager 407 through the associated data block resource server 413' as well.

  When instantiation of the pseudo-calculation process 403 is necessary to read data from the memory of the computing device, it instructs its associated data block manager 405 to request data from the data block resource manager 407. In response, the data block manager 405 requests the specified data from its associated data block resource server 413. The data block resource server 413 then causes the data block resource manager 407 to obtain the requested data from the local memory 409, the disk memory 411, or both as required. After the data block resource manager 407 reads the requested data, the data block resource server 413 provides the read data to its associated data block manager 405 and can be employed by the pseudo-calculation process 403. An inverse process is used to save the data generated by the calculation process 403.

  FIG. 5 shows a sequence of geometric data (designated L in the table) between the main computation process 403 ′ (designated HDB0 in the table) and the pseudo-calculation process 403A (designated HDB1 in the table). FIG. 7 shows a table representing operations that can be performed by various embodiments of the present invention to replace In various implementations of the present invention, the data block manager 405 communicates with its associated data block resource server 413, eg, through a UNIX domain socket using conventional inter-process communication (IPC) technology. May be. Of course, other communication technologies can be employed for the underlying operating system, hardware configuration, etc. used, where appropriate.

(Distributed data)
FIG. 6 illustrates an embodiment of a parallel processing computing system that can share data between different processes of a master computing device in accordance with various embodiments of the present invention. As can be seen from this figure, the parallel processing computing system 601 includes a master computing device 603 (identified by the label “master node” in the figure) and a plurality of remote computing devices 605A, 605B... 605y (label “ Each of which is identified by a “remote node”. The master computer 503 includes an instantiation (0, 1,... N) of N + 1 numbers of calculation processes 403, each of which includes a data block manager 405, as described above. The main calculation process 403 ′ includes a data block resource manager 407.

  Each remote computing device includes one or more instantiations of remote computing process 607 (labeled as “HDB_RCS” in the figure). Each remote computing process 607 may be a copy of the corresponding computing process 403 on the master computing device 503 or may be a sub-process of the corresponding computing process 403 on the master computing device 503. Each remote computing process 607 includes or otherwise employs a remote data client (not shown). Each remote computing device 605 also implements a remote data server 609 (also referred to as a remote data block resource manager). Similar to the data block resource manager 407, each remote data server 609 can store data in the memory of its remote computing device 605 and read data therefrom. Again, the memory for the remote computing device 605 includes “fast” memory provided by an integrated circuit memory device operating adjacent to the processing unit of the remote computing device, “slow” memory provided by a magnetic or optical disk, Or some combination thereof. A remote data client, remote data server 609, and data block manager 405 are each interconnected within the network.

  As described above, each remote data client (not shown) has a function of data transmission / reception (read / write) within a 16K block via the network formed by the remote data client, the remote data server 609, and the data block manager 405. Involved in providing. Each remote computation process 607 has a remote data client, and each remote data client obtains a unique identifier from the data block resource manager 407 when instantiated.

  Each remote data server 609 is then responsible for receiving 16K blocks from any remote data client and storing data in the memory of its associated remote computing device 605. Each remote data server 609 is also responsible for receiving data from the memory of its associated remote computing device 605 and transmitting the data to any remote data client. When the remote data server 609 is instantiated, the data block resource manager 407 will be notified to track the remote data server 609 and be able to communicate with it. For various implementations of the invention, the remote data server 609 may manage a fixed amount of memory, such as 1 GB. Further, control information for controlling the remote data server 609 is transmitted to the remote data server 609 via a standard calculation process interface such as an interface using a transmission control protocol (TCP), and can be read from there. is there.

  When the remote instantiation of computing process 607 requires access to data, it instructs its associated remote data client to request the data. If the data is managed by another remote computing process 607, the remote data client will request data from the remote data server 609 associated with that remote computing process 607. Alternatively, if the data is managed by a computing process on the master computing device, the remote data client will request data from the data block manager associated with that master computing process. As described above, the data block manager may then obtain data through the data block resource manager associated with the main computing process on the master computing device. Similarly, if a remote computing process requires storage of data, its associated to provide data to the appropriate remote data server or data block resource manager for storage in the corresponding memory. Command the remote data client.

  For the various embodiments of the present invention, the data block manager, remote data client, and remote data server use a suitable network communication protocol such as Transmission Control Protocol / Internet Protocol (TCP / IP) or User Datagram Protocol. And may be interconnected by an electronic communication network. For some implementations of the invention, the data block manager, remote data client, and remote data server may be interconnected using a reliable form of UDP. For example, some implementations of the invention may use the data format shown in FIGS. 7 and 8 to reliably read and transmit each block of data using UDP. The elements of these blocks are discussed below.

  a. Sequence number: 4 bytes, RDC maintenance block sequence number, incremented after every successful transaction. This number is returned by the RDS so that the RDC can confirm that the specified transaction was successful.

  b. Transaction ID: 4 bytes, RDC / RDS maintenance, RDS designated transaction ID, incremented after every successful transaction so that RDS can detect stale transactions.

  c. Client ID: 4 bytes, unique to RDC (assigned by resource manager). Reason: Used by RDS as a reference for RDC transaction ID information.

  d. Time stamp: 8 bytes. Used by the client to estimate the round trip time and avoid retransmission RTT ambiguity issues.

  e. Block index: The index of the block that the RDC wants from the RDS.

  f. RDS IP address: 4 bytes, used by RDC to ensure that the received data is from the correct RDS. The client UDP socket receives any data scheduled for its IP address and port from anywhere.

  g. RDS port: 2 bytes, same purpose as above.

  The RDC authenticates the transaction using the sequence number, transaction ID, and remote address, but the RDC must be prepared to retransmit if it does not get a response from the RDS. The retransmission may be based on the RTT estimate (similar to TCP). The RDC will attempt to retransmit up to a maximum number of times and will use an exponential backoff until the maximum time of its retransmission timer (similar to TCP).

(Conclusion)
As described above, the present invention has been described in terms of its preferred and exemplary embodiments. Numerous other embodiments, modifications, and variations within the scope and spirit of the appended claims will occur to those skilled in the art from consideration of the disclosure.

Claims (6)

A method of distributing data within a parallel processing system,
In a data block resource manager, receiving a request for data from a first data block manager, the first data block manager executing on a first computing node in a parallel processing system Associated with the process,
Determining that the requested data block is stored in a memory location assigned to a second process executing on a second computing node in the parallel processing system;
Requesting the data from a second data block manager associated with the second process;
Receiving data from the second data block manager;
Providing the received data to the first data block manager.   The method of claim 1, wherein the first computing node and the second computing node are hosted on the same computing device.   The first computing node is hosted by a first computing device, and the second computing node is hosted by a second computing device that is separate from the first computing device. the method of.   The first computing node is hosted by a first computing device, and the second computing node is hosted by a second computing device that is separate from the first computing device. the method of. A method of distributing data within a parallel processing system,
At a remote data server, receiving a request for data from a first remote data client, the first remote data client executing on a first computing node in a parallel processing system Associated with that,
Providing the received data to the first remote data client.   A parallel processing system using any combination of the aforementioned components.

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