JP2010529559A5 - - Google Patents

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Publication number
JP2010529559A5
JP2010529559A5 JP2010511260A JP2010511260A JP2010529559A5 JP 2010529559 A5 JP2010529559 A5 JP 2010529559A5 JP 2010511260 A JP2010511260 A JP 2010511260A JP 2010511260 A JP2010511260 A JP 2010511260A JP 2010529559 A5 JP2010529559 A5 JP 2010529559A5
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JP
Japan
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loop
computer
parallel
open
section
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JP2010511260A
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English (en)
Japanese (ja)
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JP2010529559A (ja
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Priority claimed from US11/810,111 external-priority patent/US8024714B2/en
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Publication of JP2010529559A publication Critical patent/JP2010529559A/ja
Publication of JP2010529559A5 publication Critical patent/JP2010529559A5/ja
Pending legal-status Critical Current

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JP2010511260A 2007-06-04 2008-05-30 トランザクションを用いるシーケンシャルフレームワークの並行化 Pending JP2010529559A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/810,111 US8024714B2 (en) 2006-11-17 2007-06-04 Parallelizing sequential frameworks using transactions
PCT/US2008/065363 WO2008151046A1 (en) 2007-06-04 2008-05-30 Parallelizing sequential frameworks using transactions

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2014061450A Division JP5813165B2 (ja) 2007-06-04 2014-03-25 トランザクションを用いるシーケンシャルフレームワークの並行化

Publications (2)

Publication Number Publication Date
JP2010529559A JP2010529559A (ja) 2010-08-26
JP2010529559A5 true JP2010529559A5 (enExample) 2011-06-30

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Family Applications (2)

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JP2010511260A Pending JP2010529559A (ja) 2007-06-04 2008-05-30 トランザクションを用いるシーケンシャルフレームワークの並行化
JP2014061450A Expired - Fee Related JP5813165B2 (ja) 2007-06-04 2014-03-25 トランザクションを用いるシーケンシャルフレームワークの並行化

Family Applications After (1)

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JP2014061450A Expired - Fee Related JP5813165B2 (ja) 2007-06-04 2014-03-25 トランザクションを用いるシーケンシャルフレームワークの並行化

Country Status (7)

Country Link
US (2) US8024714B2 (enExample)
EP (1) EP2171592B1 (enExample)
JP (2) JP2010529559A (enExample)
CN (1) CN101681292B (enExample)
BR (1) BRPI0811470A2 (enExample)
TW (1) TWI451340B (enExample)
WO (1) WO2008151046A1 (enExample)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8010550B2 (en) * 2006-11-17 2011-08-30 Microsoft Corporation Parallelizing sequential frameworks using transactions
US8621468B2 (en) * 2007-04-26 2013-12-31 Microsoft Corporation Multi core optimizations on a binary using static and run time analysis
EP2202638A4 (en) * 2007-09-21 2011-12-14 Fujitsu Ltd TRANSLATION FACILITY, TRANSLATION PROCEDURE AND TRANSLATION PROGRAM AND PROCESSOR CONTROL SYSTEM AND PROCESSOR
US8739141B2 (en) * 2008-05-19 2014-05-27 Oracle America, Inc. Parallelizing non-countable loops with hardware transactional memory
JP4612710B2 (ja) * 2008-06-02 2011-01-12 株式会社日立製作所 トランザクション並行制御方法、データベース管理システム、およびプログラム
US8667476B1 (en) * 2009-01-20 2014-03-04 Adaptmicrosys LLC Instruction grouping and ungrouping apparatus and method for an adaptive microprocessor system
US8266604B2 (en) * 2009-01-26 2012-09-11 Microsoft Corporation Transactional memory compatibility management
US20110178984A1 (en) * 2010-01-18 2011-07-21 Microsoft Corporation Replication protocol for database systems
US8825601B2 (en) 2010-02-01 2014-09-02 Microsoft Corporation Logical data backup and rollback using incremental capture in a distributed database
CN104572506B (zh) * 2013-10-18 2019-03-26 阿里巴巴集团控股有限公司 一种并发访问内存的方法及装置
US9454313B2 (en) 2014-06-10 2016-09-27 Arm Limited Dynamic selection of memory management algorithm
CN104317850B (zh) * 2014-10-14 2017-11-14 北京国双科技有限公司 数据处理方法和装置
JP6645348B2 (ja) 2016-05-06 2020-02-14 富士通株式会社 情報処理装置、情報処理プログラム、及び情報処理方法
US11521242B2 (en) * 2016-08-31 2022-12-06 Meta Platforms, Inc. Asynchronous execution of tasks and ordering of task execution
EP3594804B1 (en) * 2018-07-09 2021-11-03 ARM Limited Transactional compare-and-discard instruction

Family Cites Families (59)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB8306813D0 (en) 1983-03-11 1983-04-20 Bonas Machine Co Heald control apparatus
US4884228A (en) 1986-10-14 1989-11-28 Tektronix, Inc. Flexible instrument control system
JPH01108638A (ja) * 1987-10-21 1989-04-25 Hitachi Ltd 並列化コンパイル方式
JPH0475139A (ja) * 1990-07-18 1992-03-10 Toshiba Corp ループ並列化装置
DE4216871C2 (de) 1991-05-21 2001-09-06 Digital Equipment Corp Ausführungsordnen zum Sicherstellen der Serialisierbarkeit verteilter Transaktionen
US5701480A (en) 1991-10-17 1997-12-23 Digital Equipment Corporation Distributed multi-version commitment ordering protocols for guaranteeing serializability during transaction processing
JPH05127904A (ja) * 1991-11-05 1993-05-25 Matsushita Electric Ind Co Ltd 情報処理装置及びコード生成装置
JPH05173988A (ja) * 1991-12-26 1993-07-13 Toshiba Corp 分散処理方式および該分散処理に適用されるトランザクション処理方式
US5241675A (en) 1992-04-09 1993-08-31 Bell Communications Research, Inc. Method for enforcing the serialization of global multidatabase transactions through committing only on consistent subtransaction serialization by the local database managers
US5335343A (en) 1992-07-06 1994-08-02 Digital Equipment Corporation Distributed transaction processing using two-phase commit protocol with presumed-commit without log force
US6704861B1 (en) 1993-06-17 2004-03-09 Hewlett-Packard Development Company, L.P. Mechanism for executing computer instructions in parallel
JPH0784851A (ja) * 1993-09-13 1995-03-31 Toshiba Corp 共有データ管理方法
US5799179A (en) 1995-01-24 1998-08-25 International Business Machines Corporation Handling of exceptions in speculative instructions
JP3434405B2 (ja) 1996-03-19 2003-08-11 富士通株式会社 通信制御装置及び通信制御方法並びに中間通信制御ユニット
US5920724A (en) * 1996-03-28 1999-07-06 Intel Corporation Software pipelining a hyperblock loop
JPH1049420A (ja) 1996-08-02 1998-02-20 Fuji Xerox Co Ltd データベース管理方法
US5898865A (en) 1997-06-12 1999-04-27 Advanced Micro Devices, Inc. Apparatus and method for predicting an end of loop for string instructions
CA2209549C (en) 1997-07-02 2000-05-02 Ibm Canada Limited-Ibm Canada Limitee Method and apparatus for loading data into a database in a multiprocessor environment
JP3052908B2 (ja) * 1997-09-04 2000-06-19 日本電気株式会社 トランザクションプログラム並列実行方法およびトランザクションプログラム並列実行方式
US7065750B2 (en) 1999-02-17 2006-06-20 Elbrus International Method and apparatus for preserving precise exceptions in binary translated code
AU6784600A (en) 1999-08-17 2001-03-13 Progress Software, Inc. Concurrent commit lock
US6374403B1 (en) * 1999-08-20 2002-04-16 Hewlett-Packard Company Programmatic method for reducing cost of control in parallel processes
US6507947B1 (en) * 1999-08-20 2003-01-14 Hewlett-Packard Company Programmatic synthesis of processor element arrays
US6438747B1 (en) * 1999-08-20 2002-08-20 Hewlett-Packard Company Programmatic iteration scheduling for parallel processors
JP4237354B2 (ja) 1999-09-29 2009-03-11 株式会社東芝 トランザクション処理方法及びトランザクション処理システム
US6745160B1 (en) 1999-10-08 2004-06-01 Nec Corporation Verification of scheduling in the presence of loops using uninterpreted symbolic simulation
US6557048B1 (en) 1999-11-01 2003-04-29 Advanced Micro Devices, Inc. Computer system implementing a system and method for ordering input/output (IO) memory operations within a coherent portion thereof
US6574725B1 (en) * 1999-11-01 2003-06-03 Advanced Micro Devices, Inc. Method and mechanism for speculatively executing threads of instructions
US20040236659A1 (en) 1999-12-01 2004-11-25 Cazalet Edward G. Method and apparatus for an engine system supporting transactions, schedules and settlements involving fungible, ephemeral commodities including electrical power
US6918053B1 (en) 2000-04-28 2005-07-12 Microsoft Corporation Compensation framework for long running transactions
US6708331B1 (en) * 2000-05-03 2004-03-16 Leon Schwartz Method for automatic parallelization of software
US6615403B1 (en) * 2000-06-30 2003-09-02 Intel Corporation Compare speculation in software-pipelined loops
EP1197876A3 (en) 2000-10-13 2003-04-16 Miosoft Corporation Persistent data storage techniques
US7111023B2 (en) 2001-05-24 2006-09-19 Oracle International Corporation Synchronous change data capture in a relational database
US7069556B2 (en) 2001-09-27 2006-06-27 Intel Corporation Method and apparatus for implementing a parallel construct comprised of a single task
GB0130399D0 (en) 2001-12-19 2002-02-06 Ibm Message ordering in a messaging system
US6754737B2 (en) 2001-12-24 2004-06-22 Hewlett-Packard Development Company, L.P. Method and apparatus to allow dynamic variation of ordering enforcement between transactions in a strongly ordered computer interconnect
KR100450400B1 (ko) 2001-12-26 2004-09-30 한국전자통신연구원 안전 기억 장치가 없는 환경을 위한 이중화 구조의 주 메모리 상주 데이터베이스 관리시스템 및 그 데이터 일치성 제어방법
US6785779B2 (en) 2002-01-09 2004-08-31 International Business Machines Company Multi-level classification method for transaction address conflicts for ensuring efficient ordering in a two-level snoopy cache architecture
US7685583B2 (en) 2002-07-16 2010-03-23 Sun Microsystems, Inc. Obstruction-free mechanism for atomic update of multiple non-contiguous locations in shared memory
US7103612B2 (en) 2002-08-01 2006-09-05 Oracle International Corporation Instantiation of objects for information-sharing relationships
US7076508B2 (en) 2002-08-12 2006-07-11 International Business Machines Corporation Method, system, and program for merging log entries from multiple recovery log files
US7089253B2 (en) 2002-09-13 2006-08-08 Netezza Corporation Computer method and system for concurrency control using dynamic serialization ordering
US6898685B2 (en) 2003-03-25 2005-05-24 Emc Corporation Ordering data writes from a local storage device to a remote storage device
US7185323B2 (en) * 2003-05-16 2007-02-27 Sun Microsystems, Inc. Using value speculation to break constraining dependencies in iterative control flow structures
KR100507782B1 (ko) 2003-12-04 2005-08-17 한국전자통신연구원 데이터베이스 관리시스템 및 그 시스템에서 시스템테이블에 대한 동시성 제어 방법
US20050210185A1 (en) 2004-03-18 2005-09-22 Kirsten Renick System and method for organizing data transfers with memory hub memory modules
US7386842B2 (en) 2004-06-07 2008-06-10 International Business Machines Corporation Efficient data reorganization to satisfy data alignment constraints
US7266571B2 (en) 2004-07-27 2007-09-04 International Business Machines Corporation Method and system for scheduling a partial ordered transactions for event correlation
US7921407B2 (en) * 2004-08-10 2011-04-05 Oracle America, Inc. System and method for supporting multiple alternative methods for executing transactions
US7376675B2 (en) 2005-02-18 2008-05-20 International Business Machines Corporation Simulating multi-user activity while maintaining original linear request order for asynchronous transactional events
US7627864B2 (en) * 2005-06-27 2009-12-01 Intel Corporation Mechanism to optimize speculative parallel threading
US7536517B2 (en) * 2005-07-29 2009-05-19 Microsoft Corporation Direct-update software transactional memory
US20070113056A1 (en) * 2005-11-15 2007-05-17 Dale Jason N Apparatus and method for using multiple thread contexts to improve single thread performance
KR100806274B1 (ko) * 2005-12-06 2008-02-22 한국전자통신연구원 멀티 쓰레디드 프로세서 기반의 병렬 시스템을 위한 적응형실행 방법
US7926046B2 (en) * 2005-12-13 2011-04-12 Soorgoli Ashok Halambi Compiler method for extracting and accelerator template program
US7720891B2 (en) 2006-02-14 2010-05-18 Oracle America, Inc. Synchronized objects for software transactional memory
US8010550B2 (en) 2006-11-17 2011-08-30 Microsoft Corporation Parallelizing sequential frameworks using transactions
US7937695B2 (en) * 2007-04-27 2011-05-03 International Business Machines Corporation Reducing number of exception checks

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