JP2010517307A - Dielectric cap layer - Google Patents

Dielectric cap layer Download PDF

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JP2010517307A
JP2010517307A JP2009547410A JP2009547410A JP2010517307A JP 2010517307 A JP2010517307 A JP 2010517307A JP 2009547410 A JP2009547410 A JP 2009547410A JP 2009547410 A JP2009547410 A JP 2009547410A JP 2010517307 A JP2010517307 A JP 2010517307A
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cap layer
silicon
nitrogen
dielectric cap
dielectric
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JP5679662B2 (en
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ベルヤンスキー・マイケル・ピー
ボニーラ・グリゼルダ
リュー・シャオ・ヒュー
グエン・ソン・バン
ショウ・トーマス・エム
ショバ・ホサドゥルガ・ケー
ヤン・デウォン
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International Business Machines Corp
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Abstract

【課題】 誘電体キャップ層（１００）を提供する。
【解決手段】 １つの実施例において、誘電体キャップ層（１００）は、硬化処理の間の紫外線照射を実質的に遮断する光学的バンドギャップ（例えば、約３．０電子−ボルトよりも大きい）を有し、電子ドナー、二重結合電子を有する窒素を含む誘電体材料（１０８）を含む。誘電体キャップ層（１００）は、高モジュラスを示し、そしてナノ電子デバイスに例えば銅及び低ｋ誘電体を形成する後工程（ＢＥＯＬ）におけるＵＶ光を使用する超低誘電率（ＵＬＫ）材料のポストキュア処理のもとで安定であり、膜及びデバイスのクラックを減少し、そして信頼性を改善する。
【選択図】図１A dielectric cap layer (100) is provided.
In one embodiment, a dielectric cap layer (100) has an optical band gap (eg, greater than about 3.0 eV) that substantially blocks ultraviolet radiation during the curing process. And a dielectric material (108) comprising an electron donor and nitrogen having double bond electrons. The dielectric cap layer (100) exhibits a high modulus and post of ultra low dielectric constant (ULK) material using UV light in post processing (BEOL) to form, for example, copper and low k dielectrics in nanoelectronic devices. It is stable under curing, reduces film and device cracks, and improves reliability.
[Selection] Figure 1

Description

本発明は、概略的には集積回路（ＩＣ）チップの製造に関し、更に具体的にいうならば、超低誘電率（ＵＬＫ）の中間レベルの誘電体のための誘電体キャップ層に関する。   The present invention relates generally to the manufacture of integrated circuit (IC) chips, and more specifically to a dielectric cap layer for ultra-low dielectric constant (ULK) intermediate level dielectrics.

従来のＩＣチップにおいては、デバイスの後工程（ｂａｃｋ−ｅｎｄ−ｏｆ−ｌｉｎｅ， ＢＥＯＬ）層内にデバイスへの及びデバイスからの電気的接続を与えるための相互接続金属体としてアルミニウム及びアルミニウム合金が使用されてきた。過去においてはアルミニウムを主体とする金属体が金属相互接続体として使用された金属であったが、アルミニウムは、ＩＣチップの回路密度及び動作速度の増大及びデバイスの寸法がナノメートルの寸法まで減少することに対する要求事項をもはや満たさなくなっている。かくして、銅はアルミニウムに比べて抵抗率が低くそしてエレクトロマイグレーションによる故障を受けにくいために、銅がアルミニウムに代わって使用されてきた。   Conventional IC chips use aluminum and aluminum alloys as interconnect metal bodies to provide electrical connection to and from the device in the back-end-of-line (BEOL) layer of the device It has been. In the past, aluminum-based metal bodies were the metals used as metal interconnects, but aluminum reduces the circuit density and operating speed of IC chips and device dimensions to nanometer dimensions. Is no longer meeting the requirements. Thus, copper has been used in place of aluminum because copper has a lower resistivity than aluminum and is less susceptible to failure due to electromigration.

銅を使用することに関する１つの問題点は、処理ステップが進むにつれて銅が周囲の誘電体材料内に拡散することである。銅の拡散を防止するために、銅の相互接続体は保護用のバリア層を使用することにより絶縁されることができる。このようなバリア層は、例えば銅の相互接続体の側壁及び底部に沿って設けられるタンタル、チタン若しくはタングステン又はこれらの合金からなる導電性の拡散バリア層を含む。層の相互接続体の上面には、キャップ・バリア層が設けられる。このようなキャップ・バリア層は、例えば窒化シリコン（Ｓｉ３Ｎ４）のような種々な誘電体材料を含む。 One problem with using copper is that copper diffuses into the surrounding dielectric material as processing steps progress. To prevent copper diffusion, copper interconnects can be insulated by using a protective barrier layer. Such barrier layers include, for example, conductive diffusion barrier layers made of tantalum, titanium or tungsten or alloys thereof provided along the sidewalls and bottom of the copper interconnect. A cap barrier layer is provided on the top surface of the layer interconnect. Such cap barrier layers include various dielectric materials such as silicon nitride (Si 3 N 4 ).

上述のような銅の金属接続体及びキャップ層を利用する従来のＢＥＯＬ相互接続は、例えばトランジスタのような論理回路素子を含む下側基板を含む。基板の上に中間レベルの誘電体材料（ＩＬＤ）層が設けられる。ＩＬＤ層は基板上に重なる。ＩＬＤ層は例えば二酸化シリコン（ＳｉＯ２）から形成される。しかしながら最新の相互接続構造では、ＩＬＤ層は低ｋ（低誘電率）の重合熱硬化性材料であるのが望ましい。基板及びＩＬＤ層の間に接着促進層が配置され得る。窒化シリコン（Ｓｉ３Ｎ４）層が、ＩＬＤ層の上に随意選択的に配置され得る。一般的に窒化シリコン層は、ハード・マスク層又は研磨停止層として知られている。少なくとも１つの導電体がＩＬＤ層内に埋め込まれる。導電体は、最新の相互接続では銅が代表的であるが、これの代わりにアルミニウムまたは他の導電材料が使用され得る。導電体が銅である場合、拡散バリア層がＩＬＤ層及び銅の導電体の間に配置されるのが望ましい。代表的には、拡散バリア・ライナは、タンタル、チタン、タングステン又はこれらの窒化物である。 Conventional BEOL interconnects utilizing copper metal connectors and cap layers as described above include a lower substrate that includes logic circuit elements such as transistors. An intermediate level dielectric material (ILD) layer is provided on the substrate. The ILD layer overlies the substrate. The ILD layer is made of, for example, silicon dioxide (SiO 2 ). However, in modern interconnect structures, it is desirable that the ILD layer be a low k (low dielectric constant) polymeric thermoset material. An adhesion promoting layer may be disposed between the substrate and the ILD layer. A silicon nitride (Si 3 N 4 ) layer may optionally be disposed on the ILD layer. In general, the silicon nitride layer is known as a hard mask layer or a polish stop layer. At least one conductor is embedded in the ILD layer. The conductor is typically copper in modern interconnects, but aluminum or other conductive material may be used instead. If the conductor is copper, it is desirable that a diffusion barrier layer be disposed between the ILD layer and the copper conductor. Typically, the diffusion barrier liner is tantalum, titanium, tungsten or nitrides thereof.

通常、化学−機械研磨（ＣＭＰ）ステップにより導電体の上面はハード・マスク窒化物層の上面と同一平面（コプレーナともいう）にされる。代表的には窒化シリコンであるキャップ層が導体及びハード・マスク層の上に配置される。キャップ層は、後続の処理ステップの間に導体からの銅が周囲の誘電体材料内に拡散するのを防止する拡散バリアとして働く。例えば窒化シリコンのような高密度プラズマ（ＨＤＰ）化学蒸着（ＣＶＤ）膜（フィルム）は、これがキャップ層の相互接続表面に沿う銅原子の移動をより効果的に停止するので、プラズマ増強（ＰＥ）ＣＶＤ膜に比べて優れたエレクトロマイグレーション耐性を与える。 Typically, the top surface of the conductor is flush with the top surface of the hard mask nitride layer (also called a coplanar) by a chemical-mechanical polishing (CMP) step. A cap layer, typically silicon nitride, is disposed over the conductor and hard mask layer. The cap layer serves as a diffusion barrier that prevents copper from the conductor from diffusing into the surrounding dielectric material during subsequent processing steps. For example, high density plasma (HDP) chemical vapor deposition (CVD) films (films) such as silicon nitride more effectively stop the movement of copper atoms along the interconnect surface of the cap layer, so that plasma enhanced (PE) Provides superior electromigration resistance compared to CVD films.

最近、銅の相互接続体に対して超低誘電率（ＵＬＫ）の誘電体材料（即ち、ｋ＜３．０）が、低ｋ２相又は重合熱硬化性誘電体材料の代わりに使用されるようになった。これらの誘電体材料は、紫外線（ＵＶ）照射又は電子ビーム（Ｅビーム）照射を使用するポスト・キュア・ステップを使用することを必要とする。例えばポスト・キュア（硬化後）ＵＶ照射により、キャップ層内の応力が増大しそしてキャップ層及びＵＬＫ層の両方にクラックが生じる。キャップ層にどのようなクラックが生じても、継ぎ目を介するＩＬＤ層への銅の拡散を引き起こし、キャップ層の下に銅の塊を形成する。このような銅の塊は、隣接する相互接続線相互間の漏洩電流に基づく短絡を引き起こす。又、ＵＶまたはＥビーム照射あるいはその両方は、特に後続の誘電体材料の付着、金属膜形成及び化学―機械研磨の間に、パターン化された銅ライン上で例えば応力の増大、層の剥離及びふくらみの増大のような他の損傷を引き起こす。 Recently, ultra-low dielectric constant (ULK) dielectric materials (ie, k <3.0) have been used instead of low k2 phase or polymerized thermoset dielectric materials for copper interconnects. Became. These dielectric materials require the use of a post cure step that uses ultraviolet (UV) irradiation or electron beam (E beam) irradiation. For example, post cure (post cure) UV irradiation increases the stress in the cap layer and causes cracks in both the cap layer and the ULK layer. Any cracking in the cap layer causes copper to diffuse into the ILD layer through the seam, forming a copper mass under the cap layer. Such a copper mass causes a short circuit based on leakage current between adjacent interconnect lines. Also, UV or E-beam irradiation or both can cause, for example, increased stress, delamination and layering on patterned copper lines, especially during subsequent dielectric material deposition, metal film formation and chemical-mechanical polishing. Causes other damage such as increased bulge.

上述の観点から、ＵＶ照射またはＥビーム照射に対する安定性が高い誘電体材料に対する必要性が生じてきた。 In view of the above, a need has arisen for dielectric materials that are highly stable to UV or E-beam irradiation.

誘電体材料のキャップ及びこれに関連する方法について説明する。１つの実施例において、誘電体キャップ層は、硬化処理の間の紫外線放射を実質的に遮断する光学的バンドギャップ（例えば約３．０電子−ボルトより大きい）を有しそして電子ドナー、二重結合電子（ｅｌｅｃｔｒｏｎ ｄｏｎｏｒ，ｄｏｕｂｌｅ ｂｏｎｄ ｅｌｅｔｒｏｎｓ）を有する窒素を含む誘電体材料を含む。この誘電体キャップ層は、高モジュラス（ｈｉｇｈ ｍｏｄｕｌｕｓ）を示しそして例えばナノ電子デバイスのための銅及び低ｋ材料を使用する後工程（ＢＥＯＬ）におけるＵＬＫのポストＵＶキュア（硬化）処理のもとで安定であり、膜及びデバイスのクラックを減少しそして信頼性を改善する。 A dielectric material cap and associated methods are described. In one embodiment, the dielectric cap layer has an optical band gap (eg, greater than about 3.0 electrons-volt) that substantially blocks ultraviolet radiation during the curing process and an electron donor, dual A dielectric material including nitrogen having electron donors (double bond eletrons) is included. This dielectric cap layer exhibits high modulus and under ULK post UV cure treatment in a post-process (BEOL) using, for example, copper and low-k materials for nanoelectronic devices. It is stable, reduces film and device cracks and improves reliability.

本発明の第１の態様は、硬化処理の間、紫外線照射を実質的に遮断する光学的バンドギャップを有しそして電子ドナー、二重結合電子を有する窒素を含む誘電体材料の誘電体キャップ層を提供する。 A first aspect of the present invention is a dielectric cap layer of a dielectric material having an optical band gap that substantially blocks ultraviolet radiation during the curing process and comprising an electron donor, nitrogen having double bond electrons I will provide a.

本発明の第２の態様は、中間レベルの誘電体層（ＩＬＤ）を形成するステップと、紫外線照射を実質的に遮断する光学的バンドギャップを有し電子ドナー、二重結合電子を有する窒素を含む誘電体材料の層をＩＬＤの上に形成するステップと、紫外線照射を使用して誘電体材料層を硬化するステップとを含む誘電体キャップを形成する方法を提供する。 A second aspect of the present invention comprises the steps of forming an intermediate level dielectric layer (ILD), an electron donor having an optical band gap that substantially blocks ultraviolet radiation, and nitrogen having double bond electrons. A method of forming a dielectric cap is provided that includes forming a layer of dielectric material comprising an ILD over the ILD and curing the dielectric material layer using ultraviolet radiation.

本発明の第３の態様は、（ａ）硬化処理の間、紫外線照射を実質的に遮断するための約３．０電子−ボルト（ｅＶ）よりも大きい光学的バンドギャップと、（ｂ）電子ドナー、二重結合電子を有する窒素と、（ｃ）炭素成分とを有する窒化シリコンを主体とする誘電体材料を含む誘電体キャップ層を提供する。 A third aspect of the present invention provides: (a) an optical band gap greater than about 3.0 electrons-volt (eV) for substantially blocking ultraviolet radiation during the curing process; and (b) electrons. Provided is a dielectric cap layer including a dielectric material mainly composed of silicon nitride having a donor, nitrogen having a double bond electron, and (c) a carbon component.

本発明の例示的な態様は、上述の問題点及びその他の問題点を解決するために示される。 Illustrative aspects of the invention are presented to solve the above and other problems.

本発明の上述の特徴及び他の特徴は、本発明の種々な実施例を示す図面を参照して説明する以下の本発明の種々な態様に関する説明から明らかになるであろう。 The foregoing and other features of the present invention will become apparent from the following description of various aspects of the invention which will be described with reference to the drawings, which illustrate various embodiments of the invention.

本発明の実施例に従う誘電体キャップ層を示す図である。FIG. 4 is a diagram illustrating a dielectric cap layer according to an embodiment of the present invention. 誘電体キャップ層を形成する方法の実施例を示す図である。It is a figure which shows the Example of the method of forming a dielectric material cap layer.

図に示す寸法は必ずしも正しくないことに注目されたい。図は本発明の代表的な態様のみを示すものであり、従って本発明の範囲を限定するものではない。図において、同じ参照番号は同じものを示す。 Note that the dimensions shown are not necessarily correct. The figures show only representative embodiments of the invention and therefore do not limit the scope of the invention. In the figures, the same reference numerals indicate the same items.

図１を参照すると、誘電体キャップ層１００及びこれに関連する方法が示されている。誘電体キャップ層１００は、例えば、高速マイクロプロセッサ、アプリケーション固有の集積回路、メモリ記憶デバイス及び多層化されたバリア層を有する関連する電子回路構造を含む超大規模集積回路（ＵＬＳＩ）及びマイクロ電子集積回路（ＩＣ）における相互接続構造において使用される。概略的にいうと、誘電体キャップ層は、紫外線（ＵＶ）またはＥビームあるいはその両方を使用する硬化処理が行われる後工程（ＢＥＯＬ）構造の相互接続金属体を保護するために使用される非常に安定なキャッピング・バリア層である。 Referring to FIG. 1, a dielectric cap layer 100 and associated methods are shown. Dielectric cap layer 100 may be, for example, a very large scale integrated circuit (ULSI) and microelectronic integrated circuit including a high speed microprocessor, application specific integrated circuit, memory storage device, and associated electronic circuit structure having a multilayered barrier layer. Used in interconnect structures in (IC). Generally speaking, the dielectric cap layer is used to protect post-process (BEOL) structure interconnect metal bodies that are cured using ultraviolet (UV) and / or E-beam. It is a highly stable capping barrier layer.

誘電体キャップ層１００は、中間レベルの誘電体層（ＩＬＤ）１０４内の例えば銅（Ｃｕ）又はアルミニウム（Ａｌ）である導電体１０２を覆って形成され得る。ＩＬＤ１０４は、例えば、多孔性の水素添加（ハイドロジェネーテッド）シリコン・オキシカーバイド（ｐ−ＳｉＣＯＨ、即ち、多孔性ＳｉＣＯＨ）、ｐ−ＳｉＣＯＨを含むスピン・オン型の低ｋ誘電体または有機及び無機ポリマのような周知の若しくは他の超低誘電率（ＵＬＫ）材料で形成され得る。１つの実施例において、誘電体キャップ層１００は、硬化処理の間、紫外線照射を実質的に遮断する光学的バンドギャップを有し電子ドナー、二重結合電子を有する窒素を含む誘電体材料１０８を含む。本明細書でいう光学的バンドギャップは、材料を通過するに必要な光のエネルギー・レベルを指す。１つの実施例において、誘電体材料１０８は、約３．０電子−ボルト（ｅＶ）（即ち、これのプラス・マイナス０．５ｅＶの範囲）よりも大きい光学的バンドギャップを有する。光学的バンドギャップは、例えば光学的露光技法を使用して測定され得る。１つの例において、光学的バンドギャップは、Ｊ．Ａ．ＷｏｏｌｌｍａｎのＶＵＶ−ＶＡＳＥ装置を使用して測定され得る。光学的に一定なバンドギャップ・データ・フィット（ｄａｔａ ｆｉｔｓ）は、４００−８００ｎｍの範囲で非常にわずかな吸収を生じるコーシー（Ｃａｕｃｈｙ）とウルバッハ（Ｕｒｂａｃｈ）の吸収裾（ａｂｓｏｒｐｔｉｏｎ ｔａｉｌ）の組み合わせであった。消極レベル（ｄｅｐｏｌａｒｉｚａｔｉｏｎ ｌｅｂｅｌｓ）は、低く（理想的な膜を示した）、そして例えば表面の非一様性及び表面の粗さのような共通モデルの改善はモデル・フィット（ｍｏｄｅｌ ｆｉｔｓ）を改善しない。リニアなブラッグマン（Ｂｒｕｇｇｍａｎ）、及びコーシーをオプションとするマクセル−ガーネット（Ｍａｘｗｅｌｌ−Ｇａｒｎｅｔ）モデルが、バンドギャップ結果を得るために使用された。上述の光学的バンドギャップ測定技術は例示的なものでこれに限定されないことに注目されたい。 The dielectric cap layer 100 may be formed over the conductor 102, for example copper (Cu) or aluminum (Al), in an intermediate level dielectric layer (ILD) 104. The ILD 104 may be, for example, a porous hydrogenated silicon oxycarbide (p-SiCOH, ie, porous SiCOH), a spin-on low-k dielectric containing p-SiCOH, or organic and inorganic It can be formed of known or other ultra low dielectric constant (ULK) materials such as polymers. In one embodiment, the dielectric cap layer 100 comprises a dielectric material 108 comprising an optical donor having an optical bandgap that substantially blocks ultraviolet radiation during the curing process, and nitrogen having double bond electrons. Including. As used herein, optical bandgap refers to the energy level of light required to pass through a material. In one embodiment, dielectric material 108 has an optical band gap greater than about 3.0 electron-volts (eV) (ie, its plus or minus 0.5 eV range). The optical band gap can be measured using, for example, optical exposure techniques. In one example, the optical band gap is A. It can be measured using a Woolman VUV-VASE instrument. Optically constant bandgap data fits are a combination of Cauchy and Urbach absorption tails that produce very little absorption in the 400-800 nm range. It was. Depolarization levels are low (representing an ideal film) and common model improvements such as surface non-uniformity and surface roughness do not improve model fits . Linear Bruggman and Maxwell-Garnet models with Cauchy as an option were used to obtain bandgap results. It should be noted that the optical bandgap measurement technique described above is exemplary and not limiting.

本発明の実施例に従う誘電体材料は、上に示した光学的バンドギャップ及び電子ドナー、二重結合電子を有する窒素そして誘電体材料としての機能を実現する他の材料を使用することができる。本発明の実施例においては、誘電体材料１０８は、例えば窒化シリコン（ＳｉｘＮｙ）、窒化ホウ素（ＢＮｘ）、シリコン・ボロン・ナイトライド（ＳｉＢＮｘ）、シリコン・ボロン・ナイトライド・カーボン（ＳｉＢｘＮｙＣｚ）及びカーボン・ボロン・ナイトライド（ＣＢｘＮｙ）であり、ここで、各成分のｘ及びｙの値は、上記光学的バンドギャップ及び電子ドナー、二重結合電子を有する窒素を達成するに必要な比率に依存して変動する。上述のように、誘電体キャップ層１００の幾つかの実施例は、炭素（Ｃ）の成分を含むが、これは必ずしも必要ではない。炭素を含む実施例においては、炭素は材料中の約１％乃至約４０原子組成％（％ ｂｙ ａｔｏｍｉｃ ｃｏｍｐｏｓｉｔｉｏｎ）の範囲である。高い光学的バンドギャップ（即ち、約３．０ｅＶよりも高い）及び銅拡散バリア特性（これは、拡散を減少するための銅―窒素錯体を形成する適切な窒素結合の存在を意味する）を有するセラミック特性の材料１０８との任意のイオン結合が本発明の範囲内であると考えられる。 Dielectric materials according to embodiments of the present invention can use the optical band gap and electron donor shown above, nitrogen with double bond electrons, and other materials that function as a dielectric material. In an embodiment of the present invention, dielectric material 108 may be, for example, silicon nitride (Si x N y ), boron nitride (BN x ), silicon boron nitride (SiBN x ), silicon boron nitride carbon. (SiB x N y C z ) and carbon boron nitride (CB x N y ), where the x and y values of each component are the optical band gap and electron donor, double bond electrons Varies depending on the ratio required to achieve nitrogen with As mentioned above, some embodiments of the dielectric cap layer 100 include a carbon (C) component, but this is not necessary. In embodiments that include carbon, the carbon ranges from about 1% to about 40 atomic percent composition of the material (% by atomic composition). Has a high optical band gap (ie, higher than about 3.0 eV) and copper diffusion barrier properties (which means the presence of suitable nitrogen bonds to form a copper-nitrogen complex to reduce diffusion) Any ionic bonds with the ceramic material 108 are considered within the scope of the present invention.

１つの実施例において、誘電体材料１０８は、高温で酸素（Ｏ２）と接触したときに酸素拡散バリア１１０を形成することにより高温における酸化を防止するシリコン−窒素（ＳｉＮ）、窒素−シリコン−炭素（ＮＳｉＣ）及びシリコン−炭素−窒素（ＳｉＣＮ）ボンディング構造の１つからなる。この場合、酸素拡散バリア１１０は、シリコン−窒素−酸素（ＳｉＮＯ）、窒素−シリコン−酸素−炭素（ＮＳｉＯＣ）又は酸素−シリコン−窒素−炭素（ＯＳｉＮＣ）であり得る。これらの場合において、酸素（Ｏ２）は、酸素拡散バリア１１０の約１乃至約２０原子組成％である。高温とは、誘電体が使用されている集積回路（ＩＣ）チップの最大動作温度、例えば、１２０℃（＋／−５℃）よりも高い。 In one embodiment, the dielectric material 108 is silicon-nitrogen (SiN), nitrogen-silicon-, which prevents oxidation at high temperatures by forming an oxygen diffusion barrier 110 when in contact with oxygen (O 2 ) at high temperatures. It consists of one of carbon (NSiC) and silicon-carbon-nitrogen (SiCN) bonding structures. In this case, the oxygen diffusion barrier 110 may be silicon-nitrogen-oxygen (SiNO), nitrogen-silicon-oxygen-carbon (NSiOC), or oxygen-silicon-nitrogen-carbon (OSiNC). In these cases, oxygen (O 2 ) is about 1 to about 20 atomic composition percent of oxygen diffusion barrier 110. High temperature is higher than the maximum operating temperature of an integrated circuit (IC) chip in which a dielectric is used, for example, 120 ° C. (+/− 5 ° C.).

他の実施例において、誘電体材料１０８は、高温で酸素（Ｏ２）に接触したときに酸素拡散バリア１１０を形成することにより高温における酸化を防止する四面体ボンディング構造（ｔｅｔｒａｈｅｄｒａｌ ｂｏｎｄｉｎｇ ｓｔｒｕｃｔｕｒｅ）を含む。ここで再び、酸素拡散バリア１１０は、シリコン−窒素−酸素（ＳｉＮＯ）、窒素−シリコン−酸素−炭素（ＮＳｉＯＣ）又は酸素−シリコン−窒素−炭素（ＯＳｉＮＣ）を含むことができる。又、高温とは、誘電体が使用されている集積回路（ＩＣ）チップの最大動作温度、例えば、１２０℃（＋／−５℃）よりも高い。 In other embodiments, the dielectric material 108 includes a tetrahedral bonding structure that prevents oxidation at high temperatures by forming an oxygen diffusion barrier 110 when in contact with oxygen (O 2 ) at high temperatures. . Here again, the oxygen diffusion barrier 110 may comprise silicon-nitrogen-oxygen (SiNO), nitrogen-silicon-oxygen-carbon (NSiOC), or oxygen-silicon-nitrogen-carbon (OSiNC). The high temperature is higher than the maximum operating temperature of an integrated circuit (IC) chip using a dielectric, for example, 120 ° C. (+/− 5 ° C.).

他の実施例において、誘電体材料１０８は、紫外線（ＵＶ）照射１２０又はＥビーム照射１２２に曝されたときに、約２００ＭＰａよりも高い圧縮応力を有する。 In other embodiments, the dielectric material 108 has a compressive stress greater than about 200 MPa when exposed to ultraviolet (UV) radiation 120 or E-beam radiation 122.

誘電体キャップ層１００は、前述の光学的バンドギャップ及び電子ドナー、二重結合電子を有する窒素を達成するように周知の技術を使用して形成され得る。本発明の実施例では、誘電体キャップ層１００を形成する方法が提供される。ＩＬＤ１０４は、例えば堆積のような周知の技術で形成される。前述のように、ＩＬＤ１０４は、例えば、多孔性の水素添加シリコン・オキシカーバイド（ｐ−ＳｉＣＯＨ、即ち、多孔性ＳｉＣＯＨ）、ｐ−ＳｉＣＯＨを含むスピン・オン型の低ｋ誘電体または有機及び無機ポリマのような周知の若しくは他の超低誘電率（ＵＬＫ）材料で形成され得る。導電体１０２は、例えば通常のダマシン・プロセスを使用してＩＬＤ１０４内に形成され得る。 The dielectric cap layer 100 may be formed using well-known techniques to achieve the aforementioned optical band gap and electron donor, nitrogen with double bond electrons. In an embodiment of the present invention, a method for forming a dielectric cap layer 100 is provided. The ILD 104 is formed by a known technique such as deposition. As described above, the ILD 104 may be, for example, a porous hydrogenated silicon oxycarbide (p-SiCOH, or porous SiCOH), a spin-on low-k dielectric or organic and inorganic polymer containing p-SiCOH. May be formed of known or other ultra low dielectric constant (ULK) materials such as Conductor 102 may be formed in ILD 104 using, for example, a conventional damascene process.

以下に詳細に説明するように、誘電体材料１０８はＩＬＤ１０４を覆って形成され、そしてこの誘電体材料１０８は、紫外線照射を実質的に遮断する光学的バンドギャップ及び電子ドナー、二重結合電子を有する窒素を有する。上述のように、光学的バンドギャップは、例えば約３．０電子−ボルト（ｅＶ）よりも大きい。誘電体材料１０８を形成するプロセスは、使用する材料によって変わる。１つの実施例において、誘電体材料１０８は、窒化シリコン（ＳｉｘＮｙ）で有り、ここで、ｘ＝１乃至３であり、ｙ＝１乃至４である。この場合、図２に示すように、誘電体材料層１０８の形成方法は、平行プレート型プラズマ増強化学蒸着（ＰＥＣＶＤ）反応器１３０内に前駆物質を与えることを含む。平行プレート型反応器１３０は、約８５ｃｍ２及び約７５０ｃｍ２の間の基板チャック（基板支持体）１３４の導電性領域（即ち、下側電極）１３２，並びに基板１１０及び上部電極１３６の間の約１ｃｍと約１２ｃｍの間のギャップＧを有する。基板チャック１３４の導電性領域１３２がＸの係数だけ変化されると、基板チャック１３４に印加されるＲＦパワー（高周波電力）も又Ｘの係数だけ変化する。前駆物質は、（ａ）（ｉ）シランと、（ｉｉ）ジシランと、（ｉｉｉ）シリコン（Ｓｉ）、窒素（Ｎ）及び水素（Ｈ）の原子、並びにヘリウム（Ｈｅ）及びアルゴン（Ａｒ）から成る群から選択された不活性キャリアを含む窒素含有シリコン前駆物質とから成る群から選択されたシリコンを主体とする前駆物質と、（ｂ）窒素含有前駆物質とを含み得る。代わりに、気相又は液相のアミノシラン・グループの材料も又使用され得る。窒素含有前駆物質の１つの例は、アンモニア（ＮＨ３）であるが、例えば、三弗化窒素（ＮＦ３）、ヒドラジン（Ｎ２Ｈ４）又は窒素（Ｎ２）のような他の物質もあり得る。約０．４５ＭＨｚと約２００ＭＨｚの間の周波数の第１高周波（ＲＦ）電力が、電極１３４及び１３６の一方に印加される。第１高周波（ＲＦ）電力密度は、例えば、約０．１Ｗ／ｃｍ２と約５．０Ｗ／ｃｍ２の間に、そして約５０Ｗと１０００Ｗの間にセットされ得る。随意的に、上記第１高周波（ＲＦ）電力よりも低い約０．０４Ｗ／ｃｍ２と約３Ｗ／ｃｍ２の間に、そして約２０Ｗと６００Ｗの間にセットされた、第２高周波（ＲＦ）電力が電極１３４及び１３６の一方に印加され得る。 As described in detail below, a dielectric material 108 is formed over the ILD 104, and the dielectric material 108 contains optical band gaps and electron donors, double bond electrons that substantially block ultraviolet radiation. Have nitrogen. As described above, the optical band gap is greater than, for example, about 3.0 electron-volts (eV). The process of forming the dielectric material 108 varies depending on the material used. In one embodiment, the dielectric material 108 is silicon nitride (Si x N y ), where x = 1 to 3 and y = 1 to 4. In this case, as shown in FIG. 2, the method of forming dielectric material layer 108 includes providing a precursor in a parallel plate plasma enhanced chemical vapor deposition (PECVD) reactor 130. Parallel plate reactor 130, conductive regions of the substrate chuck (substrate support) 134 between about 85cm 2 and about 750 cm 2 (i.e., lower electrode) of about between 132 and substrate 110 and the upper electrode 136 With a gap G between 1 cm and about 12 cm. When the conductive region 132 of the substrate chuck 134 is changed by a factor of X, the RF power (high frequency power) applied to the substrate chuck 134 also changes by the factor of X. The precursors are (a) (i) silane, (ii) disilane, (iii) silicon (Si), nitrogen (N) and hydrogen (H) atoms, and helium (He) and argon (Ar). A silicon-based precursor selected from the group consisting of a nitrogen-containing silicon precursor containing an inert carrier selected from the group consisting of: (b) a nitrogen-containing precursor. Alternatively, gas phase or liquid phase aminosilane group materials may also be used. One example of a nitrogen-containing precursor is ammonia (NH 3 ), although other materials such as nitrogen trifluoride (NF 3 ), hydrazine (N 2 H 4 ), or nitrogen (N 2 ) are also possible. possible. A first radio frequency (RF) power having a frequency between about 0.45 MHz and about 200 MHz is applied to one of the electrodes 134 and 136. The first radio frequency (RF) power density, for example, may be set between about 0.1 W / cm 2 and about 5.0 W / cm 2, and between about 50W and 1000W. Optionally, to the first radio frequency (RF) between the lower about 0.04 W / cm 2 to about 3W / cm 2 than the power, and is set between about 20W and 600W, the second radio frequency (RF) Power can be applied to one of the electrodes 134 and 136.

１つの実施例において、基板温度は約１００℃と約４２５℃の間にセットされ得る。例えば、ヘリウム（Ｈｅ）又はアルゴン（Ａｒ）のような不活性ガスの流量は、約１０ｓｃｃｍ（ｓｔａｎｄａｒｄ ｃｕｂｉｃ ｃｅｎｔｉｍｅｔｅｒｓ）と約５０００ｓｃｃｍの間にセットされる。反応器１３０内の圧力は、約１００ｍＴｏｒｒよ約１００００ｍＴｏｒｒの間にセットされ、そして１０００−１７００ｍＴｏｒｒの圧力が望ましいことが判った。 In one example, the substrate temperature can be set between about 100 ° C. and about 425 ° C. For example, the flow rate of an inert gas such as helium (He) or argon (Ar) is set between about 10 sccm (standard cubic centimeters) and about 5000 sccm. The pressure in reactor 130 was set between about 100 mTorr and about 10,000 mTorr, and a pressure of 1000-1700 mTorr was found desirable.

紫外線照射１２０を使用して誘電体材料１０８を硬化した結果、誘電体キャップ層１００が形成される。しかしながら、紫外線照射１２０を使用する硬化処理の間に、約３．０ｅＶよりも高いエネルギー・レベルを有する照射だけが誘電体キャップ層１００を透過する可能性がある。 As a result of curing the dielectric material 108 using ultraviolet radiation 120, the dielectric cap layer 100 is formed. However, during a curing process using ultraviolet radiation 120, only radiation having an energy level higher than about 3.0 eV may penetrate the dielectric cap layer 100.

上述の実施例に関して、付着ステップに使用される条件が、誘電体キャップ層１００に望まれる最終的な誘電率に依存して変動され得ることに注目されたい。 Note that with respect to the above-described embodiments, the conditions used for the deposition step can be varied depending on the final dielectric constant desired for the dielectric cap layer 100.

上述の材料及び方法は集積回路チップの製造において使用される。結果的にもたらされる集積回路チップは、ロウ・ウエハ（即ち、パッケージ前の多数のチップを有するシングル・ウエハ）の形で、ベア・ダイとして又はパッケージされた形で製造者から販売される。後者の場合、チップは、シングル・チップ・パッケージ（例えば、マザーボード又はより高いレベルのキャリアに固定された配線を有するプラスチック・キャリア）又はマルチチップ・パッケージ（例えば、片面又は両面の表面相互配線又は内部に埋め込まれた相互配線を有するセラミック・キャリア）にマウントされる。いずれの場合にも、チップは、（ａ）例えば、マザーボードのような中間製品又は（ｂ）最終製品の部分として、他のチップ、個別回路素子または他の信号処理デバイスあるいはこれらと集積化される。最終製品は、玩具及び他のロウ・エンドの用途から表示装置、キーボードまたは他の入力装置及び中央処理プロセッサを有する高級コンピュータ製品に至る集積回路チップを含む任意の製品である。 The materials and methods described above are used in the manufacture of integrated circuit chips. The resulting integrated circuit chip is sold by the manufacturer in the form of a raw wafer (ie, a single wafer with multiple chips prior to packaging), as a bare die or in packaged form. In the latter case, the chip can be a single chip package (eg, a plastic carrier with wiring fixed to a motherboard or higher level carrier) or a multi-chip package (eg, single or double sided surface interconnect or internal Mounted on a ceramic carrier having interconnects embedded therein. In any case, the chip is integrated with other chips, individual circuit elements or other signal processing devices or as part of (a) an intermediate product, for example a mother board or (b) an end product. . The final product is any product that includes integrated circuit chips, ranging from toy and other low end applications to high-end computer products with display devices, keyboards or other input devices and a central processing processor.

本発明の種々な態様に関する上述の説明は、本発明を説明するためのものである。これらは本発明を限定するものではなく、多くの変形が可能である。本発明の範囲から逸脱することなくこのような変形が可能であることが当業者により明らかであろう。 The above description of various aspects of the invention is provided to illustrate the invention. These do not limit the present invention and many variations are possible. It will be apparent to those skilled in the art that such modifications can be made without departing from the scope of the invention.

本発明は、半導体デバイスの分野特に半導体デバイスで使用される。誘電体キャップ層において有益である。 The present invention is used in the field of semiconductor devices, particularly semiconductor devices. Useful in dielectric cap layers.

１００ 誘電体キャップ層
１０２ 導電体
１０４ 中間レベルの誘電体層（ＩＬＤ）
１０８ 誘電体材料
１１０ 酸素拡散バリア
１２０ 紫外線照射
１２２ Ｅビーム照射
１３０ ＰＥＣＶＤ反応器
１３２ 導電性領域
１３４ 基板チャック
１３６ 上部電極 100 Dielectric Cap Layer 102 Conductor 104 Intermediate Level Dielectric Layer (ILD)
108 Dielectric material 110 Oxygen diffusion barrier 120 UV irradiation 122 E-beam irradiation 130 PECVD reactor 132 Conductive region 134 Substrate chuck 136 Upper electrode

Claims (11)

硬化処理の間に紫外線を実質的に遮断する光学的バンドギャップと、電子ドナー、二重結合電子を有する窒素とを有する誘電体材料（１０８）からなる誘電体キャップ層（１００）。   A dielectric cap layer (100) comprising a dielectric material (108) having an optical band gap that substantially blocks ultraviolet radiation during the curing process, and nitrogen having electron donors and double bond electrons. 前記光学的バンドギャップが、３．０電子−ボルト（ｅＶ）よりも大きい、請求項１に記載の誘電体キャップ層（１００）。 The dielectric cap layer (100) of claim 1, wherein the optical bandgap is greater than 3.0 electrons-volt (eV). 前記誘電体材料（１０８）が、高温での酸素（Ｏ２）との接触時に酸素拡散バリアを形成することにより高温での酸化を防止するためのシリコン−窒素（ＳｉＮ）、窒素−シリコン−炭素（ＮＳｉＣ）及びシリコン−炭素−窒素（ＳｉＣＮ）ボンディング構造から成る群から選択された１つを含む、請求項１に記載の誘電体キャップ層（１００）。 Silicon-nitrogen (SiN), nitrogen-silicon-carbon for preventing the oxidation at high temperature by forming an oxygen diffusion barrier when the dielectric material (108) is in contact with oxygen (O 2 ) at high temperature The dielectric cap layer (100) of claim 1, comprising one selected from the group consisting of (NSiC) and silicon-carbon-nitrogen (SiCN) bonding structures. 前記酸素拡散バリアが、シリコン−窒素−酸素（ＳｉＮＯ）、窒素−シリコン−酸素−炭素（ＮＳｉＯＣ）及び酸素−シリコン−窒素−炭素（ＯＳｉＮＣ）から成る群から選択された１つを含む、請求項３に記載の誘電体キャップ層（１００）。   The oxygen diffusion barrier comprises one selected from the group consisting of silicon-nitrogen-oxygen (SiNO), nitrogen-silicon-oxygen-carbon (NSiOC), and oxygen-silicon-nitrogen-carbon (OSiNC). 4. The dielectric cap layer (100) according to 3. 前記高温が、前記誘電体材料が使用されている集積回路チップ（ＩＣ）の最大動作温度よりも高い、請求項３に記載の誘電体キャップ層（１００）。 The dielectric cap layer (100) of claim 3, wherein the high temperature is higher than a maximum operating temperature of an integrated circuit chip (IC) in which the dielectric material is used. 前記高温が１２０℃よりも高い、請求項５に記載の誘電体キャップ層（１００）。   The dielectric cap layer (100) of claim 5, wherein the high temperature is greater than 120C. 前記誘電体材料（１０８）が、高温での酸素（Ｏ２）との接触時に酸素拡散バリアを形成することにより高温での酸化を防止するための四面体ボンディング構造を含む、請求項１に記載の誘電体キャップ層（１００）。 It said dielectric material (108) comprises a tetrahedral bonding structure to prevent oxidation at high temperatures by forming an oxygen diffusion barrier at the time of contact with oxygen (O 2) at elevated temperature, according to claim 1 Dielectric cap layer (100). 前記酸素拡散バリアが、シリコン−窒素−酸素（ＳｉＮＯ）、窒素−シリコン−酸素−炭素（ＮＳｉＯＣ）及び酸素−シリコン−窒素−炭素（ＯＳｉＮＣ）から成る群から選択された１つを含む、請求項７に記載の誘電体キャップ層（１００）。   The oxygen diffusion barrier comprises one selected from the group consisting of silicon-nitrogen-oxygen (SiNO), nitrogen-silicon-oxygen-carbon (NSiOC), and oxygen-silicon-nitrogen-carbon (OSiNC). The dielectric cap layer (100) of claim 7. 前記高温が、前記誘電体キャップ層（１００）が使用されている集積回路チップ（ＩＣ）の最大動作温度よりも高い、請求項７に記載の誘電体キャップ層（１００）。 The dielectric cap layer (100) of claim 7, wherein the high temperature is higher than a maximum operating temperature of an integrated circuit chip (IC) in which the dielectric cap layer (100) is used. 前記誘電体材料（１０８）が、窒化シリコン（ＳｉｘＮｙ）、窒化ホウ素（ＢＮｘ）、シリコン・ボロン・ナイトライド（ＳｉＢＮｘ）、シリコン・ボロン・ナイトライド・カーボン（ＳｉＢｘＮｙＣｚ）及びカーボン・ボロン・ナイトライド（ＣＢｘＮｙ）から成る群から選択された１つである、請求項１に記載の誘電体キャップ層（１００）。 The dielectric material (108) is silicon nitride (Si x N y ), boron nitride (BN x ), silicon boron nitride (SiBN x ), silicon boron nitride carbon (SiB x N y C). The dielectric cap layer (100) of claim 1, wherein the dielectric cap layer (100) is one selected from the group consisting of z ) and carbon boron nitride (CB x N y ). 前記誘電体材料（１０８）が、紫外線照射（ＵＶ）又はＥビーム照射に曝されたときに２００ＭＰａよりも大きな圧縮応力を有する、請求項１に記載の誘電体キャップ層（１００）。   The dielectric cap layer (100) of claim 1, wherein the dielectric material (108) has a compressive stress greater than 200 MPa when exposed to ultraviolet radiation (UV) or E-beam radiation.
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