JP2010503929A5 - - Google Patents

Claims (23)

A method of storing data in said memory in a non-volatile memory organized into a plurality of blocks, each comprising blocks for storing logical units of data that can be erased together,
Allocating up to a first predetermined number of blocks as simultaneously open update blocks for storing logical unit updates of data;
Providing a pool of up to a first predetermined maximum number of open update blocks simultaneously to store logical unit updates of data;
Providing a predetermined set of classes for classifying update blocks based on a set of attributes, each class supporting a subpool up to a predetermined maximum number of update blocks associated therewith;
Providing a corresponding set of replacement rules for the predetermined set of classes to identify the update block to be replaced in each sub-pool;
Grouping the updated blocks in the pool into corresponding sub-pools;
Whenever another update block of the same class is being introduced, the step of closing and deleting the least active update block in the sub-pool that contains the associated predetermined maximum number of update blocks, said deletion Update blocks to be selected are selected according to the corresponding replacement rules for the same class;
Including methods. The method of claim 1 , wherein
The method, wherein the set of attributes includes blocks that store data in a logically sequential order. The method of claim 1 , wherein
The method wherein the set of attributes includes blocks that store data in a logically discontinuous order. The method of claim 1 , wherein
The method wherein the set of attributes includes a block for storing system data associated with operating the memory. The method of claim 1 , wherein
The method wherein the memory is a flash EEPROM. The method of claim 1 , comprising:
The method wherein the memory has a NAND structure. The method of claim 1 , wherein
The method wherein the memory is on a removable memory card. The method of claim 1 , wherein
The nonvolatile memory has a memory cell having a floating gate structure. The method of claim 1 , wherein
The nonvolatile memory includes a memory cell having a dielectric layer structure. The method of claim 1-9 wherein,
The memory has a memory cell for storing 1-bit data. The method of claim 1-9 wherein,
The memory has a memory cell for storing data of 1 bit or more. Non-volatile memory,
Memory organized into blocks, each block being divided into erasable memory units, each memory unit being for storing a logical unit of data;
A pool up to a first predetermined maximum number of update blocks that are simultaneously open to store logical unit updates of data;
A set of predefined classes for classifying update blocks based on a set of attributes, each class supporting a sub-pool up to a predetermined maximum number of associated update blocks;
A set of replacement rules corresponding to the predetermined set of classes to identify the update block to be replaced in each subpool;
A set of subpools containing update blocks for each class, and
A controller for controlling the operation of the block, wherein the operation is:
Whenever another update block of the same class is being introduced, it closes and deletes the update block in the sub-pool that contains the associated predetermined maximum number of update blocks, and the deleted update block is the same A controller comprising being selected according to said corresponding replacement rule for a class of
A non-volatile memory comprising: The memory of claim 12 ,
The set of attributes is a memory that includes blocks that store data in a logically sequential order. The memory of claim 12 ,
The set of attributes is a memory that includes blocks that store data in a logically discontinuous order. The memory of claim 12 ,
The set of attributes is a memory that includes a block that stores system data associated with operating the memory. The memory of claim 12 , comprising:
The memory is a flash EEPROM. The memory of claim 12 ,
The memory is a memory having a NAND structure. The memory of claim 12 ,
The memory is a memory on a removable memory card. The memory of claim 12 ,
The nonvolatile memory includes a memory cell having a floating gate structure. The memory of claim 12 ,
The nonvolatile memory includes a memory cell having a dielectric layer structure. Non-volatile memory,
Memory organized into blocks, each block being divided into erasable memory units, each memory unit being for storing a logical unit of data;
A pool up to a first predetermined maximum number of update blocks that are simultaneously open to store logical unit updates of data;
A set of predefined classes for classifying update blocks based on a set of attributes, each class supporting a sub-pool up to a predetermined maximum number of associated update blocks;
A set of replacement rules corresponding to the predetermined set of classes to identify the update block to be replaced in each subpool;
A set of subpools containing update blocks for each class, and
Means for closing and deleting an update block in a sub-pool containing the associated predetermined maximum number of update blocks whenever the other update block of the same class is being introduced Means for selecting an update block according to the corresponding replacement rule for the same class;
A non-volatile memory comprising: The memory according to claim 12-21 .
The memory includes memory cells each storing 1-bit data. The memory according to claim 12-21 .
The memory includes memory cells each storing data of 1 bit or more.