JP2010287675A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a Fin transistor and its manufacturing method which can easily change its structure, according to its conductivity type. <P>SOLUTION: The semiconductor device includes: a substrate; a transistor activating region 104 constituted of a convex semiconductor prepared on the substrate; a gate insulating film 105a prepared on a portion of the side and top surfaces of the transistor activating region 104; and a gate electrode 350, prepared on the side surface and top surface of the transistor activating region 104, with the gate insulating film 105a pinched in between. Of the gate electrode 350, the structure of the portion prepared on the side surface of the transistor activating region 104 is mutually different from that of the portion prepared on the top surface of the transistor activating region 104. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a method of forming an optimum gate electrode for a three-dimensional transistor.

  2. Description of the Related Art In recent years, miniaturization of transistor size, particularly reduction of gate length, has been attempted for high integration, high functionality, and high speed of semiconductor integrated circuit devices. However, in the conventional planar transistor, as the gate length is shortened, an increase in the source-drain current (short channel effect) when the transistor operation is off becomes remarkable, and the device does not function as an element. In order to solve this problem, a three-dimensional transistor has been proposed.

  Hereinafter, a method for manufacturing a three-dimensional transistor will be described with reference to FIGS. Here, the case where a substrate (Silicon on Insulator: hereinafter referred to as “SOI substrate”) having a silicon layer on an oxide film formed on a semiconductor substrate made of silicon is described.

  7A to 7D and 8A to 8D are views showing a conventional method for manufacturing a semiconductor device.

  First, as shown in FIG. 7A, a transistor active region pattern 703 is formed on an SOI substrate having a silicon oxide film 701 and a silicon layer 702 formed on a silicon substrate (not shown).

  Next, as shown in FIG. 7B, the silicon layer 702 is etched using the transistor active region pattern 703 as a mask.

  Next, as shown in FIG. 7C, the transistor active region pattern 703 is removed, and a transistor active region 704 is formed. Subsequently, ion implantation is performed using the resist pattern formed by the photolithography process as a mask to form an n-type region and a p-type region in a part of the transistor active region 704 (not shown).

  Next, as shown in FIG. 7D, an insulating film 705 functioning as a gate insulating film and a metal film 706 serving as a gate electrode are sequentially deposited.

  Next, as shown in FIG. 8A, a gate electrode formation pattern 801 formed by a photolithography process is formed on the metal film 706. Next, as shown in FIG. 8B, the metal film 706 is etched using the gate formation pattern 801 to form a gate electrode 804 in the gate region.

  Next, as shown in FIG. 8C, the gate electrode formation pattern 801 is removed. Here, the regions 805 and 806 of the transistor active region 704 serve as a source region and a drain region of the transistor.

  FIG. 8D shows an image diagram when the three-dimensional transistor manufactured by the above manufacturing process is viewed obliquely from above. In FIG. 8D, the gate insulating film is not shown. Such a three-dimensional transistor is generally called a Fin transistor. In the following, as shown in FIG. 8D, the active layer region width of the upper surface portion of the Fin-like transistor active region 704 is W, and the side surface portion height of the transistor active region 704 is H. For example, when a Fin transistor is formed on an SOI substrate having a (100) plane orientation, the plane orientation of the side surface of the transistor active region 704 is (110). That is, the transistor active region 704 has two plane orientations (100) and (110).

K. Shin, et al. “Dual Stress Capping Layer Enhancement Study for Hybrid Orientation FinFET CMOS Technology”, IEDM2005

  In semiconductors, the band structure differs depending on the crystal plane orientation, so the electron mobility and hole mobility differ depending on the plane orientation. For example, the electron mobility in silicon is the largest in the (100) plane and the smallest in the (110) plane. On the other hand, the hole mobility is highest on the (110) plane and lowest on the (100) plane. That is, in the Fin transistor, since the transistor active region is controlled by the gate electrode from both the (100) plane and the (110) plane, the desired shape differs between the n-channel transistor and the p-channel transistor. For an n-channel transistor, W> H is desirable, and for a p-channel transistor, H> W is desirable.

  However, when a CMOS (Complementary Metal Oxide Semiconductor) is configured using Fin transistors, it is difficult to provide two types of transistors having different W and H on the same SOI substrate.

  In recent years, a so-called strain technique has been put into practical use, in which mobility is increased in a channel by applying stress to the channel of the transistor, thereby improving the performance of the transistor. The crystal plane orientation greatly affects the channel mobility in this strain technique. For example, in the (100) plane in the channel region, the optimum stress direction for the n-channel transistor is the tensile direction, and the optimum stress direction for the p-channel transistor is the compression direction. On the other hand, in the (110) plane in the channel region, the desired direction of the applied stress is the same as in the (100) plane, but the effect of improving the mobility is different. Therefore, even when improving the performance of a transistor by applying a strain technique, it is possible to simultaneously form an optimum structure for both an n-channel transistor and a p-channel transistor when a CMOS is formed using Fin transistors. Have difficulty.

  In view of the foregoing, it is an object of the present invention to provide a Fin transistor whose structure can be easily changed according to the conductivity type and a method for manufacturing the same.

  In order to achieve the above object, a semiconductor device of the present invention is provided on a substrate, a transistor active region made of a convex semiconductor provided on the substrate, and a part of a side surface and an upper surface of the transistor active region. A gate electrode provided on a side surface and an upper surface of a part of the transistor active region with the gate insulating film interposed therebetween, and the transistor active region of the gate electrode is included. The configuration of the portion provided on the side surface is different from the configuration of the portion provided on the upper surface of the transistor active region.

  The plane orientations of the semiconductor crystals are different between the upper surface and the side surface of the transistor active region, and a channel is formed near the upper surface and the side surface of the transistor active region. According to the above configuration, the configuration of the gate electrode is different from the configuration of the portion provided on the side of the transistor active region and the configuration of the portion provided above the transistor active region. By appropriately setting the portion formed above the transistor active region and the portion formed laterally of the transistor active region, the effective work functions of both portions can be set to different values. Therefore, the threshold value of the transistor having the gate electrode can be changed without changing the height or width of the transistor active region. Therefore, when an n-channel transistor and a p-channel transistor are formed on a substrate, the performance of both transistors can be made equal while maintaining the same height and width of the transistor active regions of both transistors.

  For example, the gate electrode is provided on a first gate electrode provided on a side surface and an upper surface of a part of the transistor active region with the gate insulating film interposed therebetween, and on the first gate electrode. A thickness of a portion of the first gate electrode provided above the transistor active region, and a thickness of the transistor active region of the first gate electrode. The film thickness of the portion provided on the side may be different from each other.

  More specifically, the film thickness of the portion of the first gate electrode provided above the transistor active region is the film thickness of the portion of the first gate electrode provided on the side of the transistor active region. It may be smaller than the thickness.

  The constituent material of the first gate electrode may be a metal material or a metal compound, and the constituent material of the second gate electrode may be polysilicon.

  The first gate electrode and the second gate electrode are electrically separated by the second gate insulating film, and the first gate electrode and the second gate electrode include gates independent of each other. A voltage may be applied.

  According to a first method of manufacturing a semiconductor device of the present invention, a step (a) of forming a first pattern on the semiconductor layer of a substrate having a semiconductor layer thereon, and the semiconductor layer using the first pattern as a mask. (B) forming a transistor active region composed of a semiconductor, (c) sequentially forming a first insulating film and a metal film on the substrate including the transistor active region, A step (d) of thinning a portion of the metal film provided above the transistor active region; and after the step (d), a step is performed so as to straddle the transistor active region above the transistor active region. Step (e) of forming a second pattern, and etching at least the metal film and the first insulating film using the second pattern as a mask, A gate insulating film formed on a part of the first insulating film, and a film thickness of a portion provided on the gate insulating film and above the transistor formation region. Includes a step (f) of forming a first gate electrode which is smaller than the film thickness of the portion provided on the side of the transistor formation region and which is a part of the metal film.

  According to this method, since the portion of the metal film provided above the transistor active region is thinned in the step (d), the film of the portion of the first gate electrode formed above the transistor active region. It becomes possible to adjust the thickness to an appropriate value. This makes it possible to adjust and align the characteristics of the n-channel transistor and the p-channel transistor without changing the height and width of the transistor active region.

  According to a second method of manufacturing a semiconductor device of the present invention, a first insulating film and a first metal film are sequentially formed on the semiconductor layer of a substrate having a semiconductor layer thereon, and then the first metal film is formed. And patterning the first insulating film and the semiconductor layer using the first metal film as a mask to etch the transistor active region made of a semiconductor, the transistor active region, and the first A step (b) of forming a first gate insulating film which is sandwiched between the first metal insulating film and part of the first insulating film; and on the substrate including the transistor active region, A step (c) of sequentially forming a second insulating film and a second metal film on the side surface and the upper surface of the first metal film; and a first step straddling the transistor active region on the second metal film. A step (d) of forming a gate electrode formation pattern of The second metal film, the second insulating film, the first metal film, and the first gate insulating film are etched using the first gate electrode formation pattern as a mask, and the transistor formation region is etched. A second gate insulating film which is provided on a part of the side surface, part of the side surface and the upper surface of the first metal film, and which is a part of the second insulating film; and the second gate insulating film A second gate electrode made of the second metal film, a side surface and an upper surface being surrounded by the second gate electrode with the second gate insulating film interposed therebetween, and the first metal A step (e) of forming a first gate electrode comprising a part of the film, and removing a portion of the second gate electrode and the second gate insulating film formed above the transistor active region And the second gate electrode is connected to the transistor active region. And and a step (f) to leave the side of said first gate electrode.

  According to this method, the first gate electrode located above the transistor active region and the second gate electrode located laterally of the transistor active region and electrically insulated from the first gate electrode are provided. Can be formed. Therefore, the material and film thickness of the first gate electrode and the second gate electrode can be suitable for the transistor. In addition, the threshold voltage of the transistor can be controlled by individually applying a gate voltage to the first gate electrode and the second gate electrode.

  The substrate may be a semiconductor substrate, but a so-called SOI substrate is preferably used.

  According to the semiconductor device and the manufacturing method thereof according to the present invention, the configuration of the gate electrode of the so-called Fin transistor is made different between the upper surface portion and the side surface portion, without changing the height and width of the transistor active region. The mobility in the channel and the effective work function of the gate electrode can be changed.

(A)-(d) is a figure which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment. (A)-(d) is a figure which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment. (A)-(d) is a figure which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment. (A)-(d) is a figure which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. (A)-(d) is a figure which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. (A), (b) is a figure which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. (A)-(d) is a figure which shows the manufacturing method of the conventional semiconductor device. (A)-(d) is a figure which shows the manufacturing method of the conventional semiconductor device.

(First embodiment)
A method for manufacturing a semiconductor device according to the first embodiment of the present invention will be described below with reference to the drawings.

  FIGS. 1A to 1D, FIGS. 2A to 2D, and FIGS. 3A to 3D are views showing a method for manufacturing a semiconductor device according to the first embodiment. 1A to 1D, FIGS. 2A to 3D, and FIGS. 3A to 3C, the left figure shows a cross section of the semiconductor device, and the right figure is viewed from above the substrate. The top view of the semiconductor device of is shown. In the plan view of FIG. 1D, the shape of the transistor active region 104 that is not actually seen is indicated by a dotted line so that the structure can be easily understood.

  First, as shown in FIG. 1A, a silicon oxide film (insulating film) 101 formed on a silicon substrate (not shown) having a (100) plane as a main surface and a silicon oxide film 101 are formed. An SOI substrate having a silicon layer (semiconductor layer) 102 is prepared. Subsequently, an active region pattern (first pattern) 103 for a transistor is formed on a predetermined region of the SOI substrate. Here, the thickness of the silicon layer 102 which becomes the height H of the active region in the Fin transistor is preferably about 30 nm to 100 nm.

  Next, as shown in FIGS. 1B and 1C, after the silicon layer 102 is etched using the active region pattern 103 as a mask, the active region pattern 103 is removed. Thereby, a transistor active region 104 made of a semiconductor such as silicon is formed. The transistor active region 104 has a convex shape (Fin shape) such as a rectangular parallelepiped, and in the right figure (plan view), for example, the length in the vertical direction (gate length direction of the transistor) is longer than the horizontal direction (gate width direction of the transistor). It has a long rectangular planar shape. Next, ion implantation of impurities is performed on the transistor active region 104 using a resist pattern formed by a photolithography process to form an n-type region and a p-type region (not shown). In the case of manufacturing an n-channel Fin transistor, the central part in the long side direction in the planar outline of the transistor active region 104 is a p-type region, and the rest is an n-type region. In the case of manufacturing a p-channel Fin transistor, the central portion in the long side direction in the planar outline of the transistor active region 104 is an n-type region, and the rest is a p-type region. In this embodiment, an example of manufacturing a p-channel Fin transistor is shown.

  Next, as shown in FIG. 1D, a HK insulating film (first insulating film) 105 containing a high-k material and functioning as a gate insulating film and a metal film 106 serving as a gate electrode are oxidized with silicon. It forms in order on the film | membrane 101 and on the side surface and upper surface of the transistor active region 104. As the HK insulating film 105, for example, a hafnium oxide film (eg, HfO) having a thickness of about 1.0 nm to 3.0 nm is used, and as the metal film 106, for example, a titanium nitride (TiN) film or a tantalum nitride (TaN) is used. A film or a laminated film thereof having a thickness of 15 nm to 30 nm is preferably used.

  Next, as shown in FIG. 2A, an organic insulating film (second insulating film) 201 is applied to the upper surface of the SOI substrate (the upper surface of the metal film 106). Thereafter, as shown in FIG. 2B, the organic insulating film 201 is planarized by chemical mechanical polishing (CMP), and the portion of the organic insulating film 201 formed on the transistor active region 104 is polished. I do. By this polishing, the thickness of the portion of the metal film 106 formed on the upper surface of the transistor active region 104 becomes smaller than the thickness of the portion formed on the side surface of the transistor active region 104. For example, the thickness of a portion of the metal film 106 formed on the upper surface of the transistor active region 104 is about 5 nm to 10 nm, and the thickness of a portion formed on the side surface of the transistor active region 104 is about 20 nm to 30 nm. Is preferable. In this step, the entire surface of the organic insulating film 201 is etched back instead of the chemical mechanical polishing, and the thickness of the portion of the metal film 106 formed on the upper surface of the transistor active region 104 is thinned (thinned). )

  Next, as shown in FIGS. 2C and 2D, after removing the organic insulating film 201, the film thickness is about 60 nm to 100 nm on the entire surface of the SOI substrate (on the upper surface of the metal film 106). A polysilicon film (conductive film) 203 is formed.

  Next, as shown in FIG. 3A, a gate electrode formation pattern (second pattern) 301 is formed on the polysilicon film 203 across the transistor active region 104 by a photolithography process. The gate electrode formation pattern 301 intersects with the transistor active region 104 when viewed from above the substrate, and extends in the short side direction of the transistor active region 104 in the right diagram of FIG.

  Next, as shown in FIG. 3B, the polysilicon film 203, the metal film 106, and the HK insulating film 105 are etched using the gate electrode formation pattern 301 as a mask. As a result, the gate insulating film 105a formed of a part of the HK insulating film 105 and the gate electrode 350 are formed on the side surface and the upper surface of a part of the transistor active region 104. Here, the gate electrode 350 is formed of a lower gate electrode (first gate electrode) 106a formed of a part of the metal film 106 and a part of the polysilicon film 203 located on the lower gate electrode 106a. And an upper gate electrode (second gate electrode) 303. The gate electrode 350 intersects with the transistor active region 104 when viewed from above the substrate, and extends in the short side direction of the transistor active region 104 in the right diagram of FIG.

  Next, as shown in FIG. 3C, the gate electrode formation pattern 301 is removed. Here, regions located on both sides of the gate electrode 350 in the transistor active region 104 are source / drain regions 304 and 305 of the transistor.

  FIG. 3D is a perspective view when the three-dimensional transistor manufactured by the above manufacturing process is viewed obliquely from above. In FIG. 3D, the upper gate electrode 303 and the gate insulating film 105a are not shown for easy understanding of the shape of the semiconductor device of this embodiment.

  As shown in FIGS. 3C and 3D, the semiconductor device of this embodiment includes, for example, a Fin-like transistor active region 104 formed on the upper surface (on the silicon oxide film 101) of the SOI substrate, and a silicon oxide film. 101 on the upper surface of the transistor 101, on the side surface and upper surface of the transistor active region 104, with the gate insulating film 105 a interposed therebetween, and on the both sides of the gate electrode 350 in the transistor active region 104. Source / drain regions 304 and 305 formed in the region to be formed. Both side surfaces of the transistor active region 104 in the gate width direction (the direction in which the gate electrode 350 extends when viewed from above the SOI substrate) are silicon (110) surfaces, and the upper surface of the transistor active region 104 is a silicon (100) surface. It has become. Channels are formed in the vicinity of both side surfaces of the portion surrounded by the gate electrode 350 in the transistor active region 104 and in the vicinity of the upper surface. The gate electrode 350 includes a lower gate electrode 106a made of metal or a metal compound, and an upper gate electrode 303 made of polysilicon or the like provided on the lower gate electrode 106a.

  In the semiconductor device of this embodiment, the structure of the gate electrode 350 above the transistor active region 104 is different from the structure of the gate electrode 350 on the side of the transistor active region 104. Specifically, in the Fin transistor, the thickness of the lower gate electrode 106a formed on the upper surface of the transistor active region 104 with the gate insulating film 105a interposed therebetween (upper surface gate electrode 306) is lower. The thickness of the gate electrode 106a is smaller than the thickness of the portion (side surface gate electrode 307) formed on the side surface of the transistor active region 104 with the gate insulating film 105a interposed therebetween.

  In a gate electrode having a polysilicon / metal laminated structure (MIPS structure), the height H and width of the transistor active region 104 are changed by changing the film thickness of the lower gate electrode 106a made of metal, as will be described below. The effective work function of the gate electrode can be changed without changing W.

  In a MOS transistor including a gate electrode having a MIPS structure, remote Coulomb scattering occurs due to electric charges formed near the metal film-polysilicon interface. Depending on the type of the metal film and the gate insulating film used, the fixed charge that causes remote Coulomb scattering may occur at the interface between the gate insulating film and the metal film or in the gate insulating film. The channel mobility is modulated by this remote Coulomb scattering. The magnitude of this modulation is inversely proportional to the distance between the metal film-polysilicon interface and the gate insulating film, that is, the metal film thickness. Therefore, the mobility of holes in the channel can be improved by reducing the thickness of the metal film (the lower gate electrode 106a in the semiconductor device of this embodiment). On the other hand, in an n-channel Fin transistor, even if the thickness of the metal film is reduced, the mobility of electrons in the channel is not improved, but the electrons easily travel due to fixed charges.

  The (100) plane, which is the upper surface of the transistor active region 104, has a hole mobility lower than that of the (110) plane, but negative charges are transferred from the metal film-polysilicon with the thickness of the upper gate electrode 306 being reduced. By causing it to occur at the interface, the mobility can be improved. Therefore, according to the present embodiment, even when the height H and width W of the transistor active region of the p-channel Fin transistor are set to optimum values for the n-channel Fin transistor, the p-type transistor characteristics Can be improved.

  In particular, in the semiconductor device manufacturing method of this embodiment, the mobility in the channel can be arbitrarily adjusted by adjusting the polishing amount of the metal film 106 in the step shown in FIG. In the MIPS structure, since the effective work function changes depending on the metal film thickness, the threshold voltage of the transistor can be arbitrarily adjusted in each substrate surface orientation.

  In the manufacturing method of this embodiment, in the steps shown in FIGS. 1B and 1C, the transistor active region for the n-channel transistor having the same size as the transistor active region 104 for the p-channel transistor is converted into the p-channel. It can be formed simultaneously with the transistor active region 104 for the type transistor. After that, by forming a gate electrode suitable for the n-channel transistor, the performance of the n-channel transistor and the p-channel transistor can be equalized without complicated processes. Therefore, it is possible to manufacture a CMOS transistor including a Fin transistor without providing restrictions such as layout.

  In the present embodiment, a distortion technique such as a technique for providing a stress film on the transistor for distorting the channel of the transistor, a technique for forming a source / drain region with SiGe, and distorting the channel, and the present embodiment. Although the method combined with this technique is not described, since the mobility modulation by the distortion technique and the modulation of the effective work function by the gate structure can be controlled independently, it can be combined with the distortion technique. That is, the mobility of the transistor can be further improved by combining the method of this embodiment and the distortion technique.

  In the above, an example in which a Fin transistor is provided on an SOI substrate including a silicon substrate having a (100) plane as a main surface has been described. However, another crystal plane such as the (110) plane or the (111) plane is set as a main plane. Even when a silicon substrate is used, the performance of the n-channel and p-channel Fin transistors can be easily aligned by the method of this embodiment.

  Further, even when a general silicon substrate (bulk silicon substrate) is used instead of the SOI substrate having the silicon layer on the upper portion, the above-described effects can be obtained according to the method of the present embodiment.

(Second Embodiment)
Hereinafter, a method for manufacturing a semiconductor device according to the second embodiment of the present invention will be described with reference to FIGS. 4, 5, and 6.

  4A to 4D, FIGS. 5A to 5D, and FIGS. 6A and 6B are views showing a method for manufacturing a semiconductor device according to the second embodiment. 4A to 4D, FIGS. 5A to 5D, and FIG. 6A, the left figure shows a cross section of the semiconductor device, and the right figure shows the semiconductor device as viewed from above the substrate. A plan view is shown. In the plan view of FIG. 4C, the shape of the transistor active region 405 that is not actually seen is shown by a dotted line so that the structure can be easily understood.

  First, as shown in FIG. 4A, a silicon oxide film 401 formed on a silicon substrate (not shown) having a (100) plane as a main surface, and a silicon layer (on the silicon oxide film 401) An SOI substrate having a semiconductor layer 402 is prepared. Subsequently, on the SOI substrate, a first HK insulating film 403 made of, for example, a high-k material and functioning as a first gate insulating film later, and a first metal film are sequentially formed by a known method. Next, the first metal film is selectively etched to form an active region pattern 404 for a transistor composed of a part of the first metal film. Here, the thickness of the silicon layer 402 is preferably about 30 nm to 100 nm, and the thickness when the first HK insulating film 403 is made of, for example, hafnium oxide (HfO or the like) is preferably about 2 nm to 3 nm. The first metal film is made of, for example, TiN, and the thickness is desirably about 10 nm to 30 nm.

  Next, as shown in FIG. 4B, the first HK insulating film 403 and the silicon layer 402 are etched using the active region pattern 404 as a mask, and the first gate insulating film 403a and a rectangular parallelepiped or other convex shape are formed. A (Fin-like) transistor active region 405 is formed. H of the transistor active region 405 is the same as the thickness of the silicon layer 402. Next, ion implantation of impurities is performed on the transistor active region 405 using a resist pattern formed by a photolithography process to form an n-type region and a p-type region (not shown). In the case of manufacturing an n-channel Fin transistor, the central portion in the long side direction in the planar outline of the transistor active region 405 is a p-type region, and the rest is an n-type region. In the case of manufacturing a p-channel Fin transistor, the central portion in the long side direction in the planar outline of the transistor active region 104 is an n-type region, and the rest is a p-type region.

  Next, as shown in FIG. 4C, on the upper surface of the SOI substrate, on the side surface of the transistor active region 104, on the side surface of the first gate insulating film 403a, on the side surface and on the upper surface of the active region pattern 404. Second HK insulating film 407 and second metal film 408 are sequentially formed. As the second HK insulating film 407, for example, a hafnium oxide film having a thickness of about 1.0 nm to 3.0 nm is used. As the second metal film 408, for example, a TaN film having a thickness of about 15 nm to 30 nm is used. Etc. can be used.

  Next, as shown in FIG. 4D, a gate electrode formation pattern 409 is formed on the second metal film 408.

  Next, as shown in FIG. 5A, the second metal film 408 and the second HK insulating film 407 are etched using the gate electrode formation pattern 409 as a mask, and then the gate electrode formation pattern 409 is formed. Remove. As a result, the second gate insulating film 407a is sandwiched between the silicon oxide film 401, the side surface of the transistor active region 405, the side surface of the first gate insulating film 403a, the side surface and the upper surface of the active region pattern 404. Then, a second gate electrode 503 is formed. The second gate electrode 503 intersects the transistor active region 405 when viewed from above the substrate, and extends in the short side direction of the transistor active region 405 in the right diagram of FIG. In this step, the active region pattern 404 on the transistor active region 405 located on both sides of the second gate electrode 503 and a part of the first gate insulating film 403a are also removed by etching. As a result, a first gate electrode 602 made of a part of the active region pattern (first metal film) 404 is formed.

  Thereafter, as shown in FIG. 5B, the gate electrode formation pattern 409 is removed.

  Next, as shown in FIGS. 5C and 5D, an organic insulating film 504 is applied to the upper surface of the SOI substrate and the upper surface of the second gate electrode 503, and then the organic insulating film 504 is planarized by CMP. And a part of the second gate electrode 503 and the second gate insulating film 407a are removed, and the upper surface of the first gate electrode 602 is exposed. By this step, the second gate electrode 503 remains on both sides of the transistor active region 405. In this step, the organic insulating film 504 is etched back instead of CMP, and is formed above the transistor active region 405 in the second gate electrode 503 and the second gate insulating film 407a. The portion may be removed. Alternatively, the first gate electrode 602 may be partially etched to adjust the thickness of the first gate electrode 602 to an appropriate value.

  Next, as shown in FIG. 6A, by removing the organic insulating film 504, the semiconductor device of this embodiment can be manufactured. Here, regions located on both sides of the gate electrode 350 in the transistor active region 405 are source / drain regions 604 and 605 of the transistor. The first gate electrode 602 and the second gate electrode 503 are insulated by the second HK insulating film 407. Hereinafter, the first gate electrode 602 and the second gate electrode 503 are collectively referred to as a “gate electrode 610”, and the first gate insulating film 403a and the second gate insulating film 407a are collectively referred to as “ It is expressed as “gate insulating film 615”.

  Next, after a polysilicon film is formed on the upper surface of the substrate (semiconductor device being fabricated), a second gate electrode formation pattern is formed, and this is used as a mask to form a gate electrode made of polysilicon. Also good.

  FIG. 6B is a perspective view when the three-dimensional transistor manufactured by the above manufacturing process is viewed obliquely from above. In FIG. 6B, the first gate insulating film 403a and the second gate insulating film 407a are not shown for easy understanding of the shape of the semiconductor device of this embodiment.

  As shown in FIGS. 6A and 6B, the semiconductor device of this embodiment includes, for example, a Fin-like transistor active region 405 formed on the upper surface (on the silicon oxide film 401) of the SOI substrate, and a silicon oxide film. The gate electrode 610 is provided on the upper surface of 401, on the side surface and the upper surface of the transistor active region 405 so as to sandwich the gate insulating film 615 therebetween, and the transistor active region 405 is positioned on both sides of the gate electrode 610. Source / drain regions 604 and 605 formed in the region to be formed. Both side surfaces of the transistor active region 405 in the gate width direction are silicon (110) surfaces, and the upper surface of the transistor active region 405 is a silicon (100) surface.

  As described above, the gate insulating film 615 includes the first gate insulating film 403a and the second gate insulating film 407a. The gate electrode 610 includes a first gate electrode 602 provided on the transistor active region 405 so as to sandwich the first gate insulating film 403a therebetween, and a second electrode on both side surfaces of the transistor active region 405. And a second gate electrode 503 provided so as to sandwich the gate insulating film 407a therebetween. Both the first gate electrode 602 and the second gate electrode 503 are made of a metal or a metal compound. However, the first gate electrode 602 and the second gate electrode 503 may be made of different conductive materials, one of which is made of polysilicon or a laminated film of polysilicon and metal, and the other is made of metal or You may be comprised with the metal compound. In the Fin transistor of this embodiment, channels are formed in the vicinity of both sides of the portion surrounded by the gate electrode 610 in the transistor active region 405 and in the vicinity of the top surface.

  According to the method for manufacturing a semiconductor device of this embodiment, in the Fin transistor, the thickness of the first gate electrode 602 provided above the transistor active region 405 and the second provided on the side of the transistor active region 405. The thickness of the gate electrode 503 can be set separately. In addition, the first gate electrode 602 and the second gate electrode 503 can be made of different materials. In this manner, by changing the metal material and thickness, the effective work functions of the first gate electrode 602 and the second gate electrode 503 can be changed, and a channel formed in the vicinity of the upper surface of the transistor active region 405 It is possible to separately set thresholds for flowing current to a channel formed in the vicinity of the side surface of the transistor active region 405. Therefore, both threshold values can be set to optimum values.

  Further, since the first gate electrode 602 and the second gate electrode 503 are insulated by the second gate insulating film 407a, it is possible to apply a voltage to both gate electrodes separately. For this reason, in the semiconductor device of this embodiment, it is possible to perform current control with a degree of freedom equal to or higher than changing the threshold value of the transistor. In addition, the Fin transistor can be driven in a new operation mode.

  In the present embodiment, a distortion technique such as a technique for providing a stress film on the transistor for distorting the channel of the transistor, a technique for forming a source / drain region with SiGe, and distorting the channel, and the present embodiment. Although the method combined with this technique is not described, since the mobility modulation by the distortion technique and the modulation of the effective work function by the gate structure can be controlled independently, it can be combined with the distortion technique.

  Note that the manufacturing method of this embodiment can be applied regardless of whether the Fin transistor is a p-channel type or an n-channel type.

  In the manufacturing method of this embodiment, the transistor active region 405 for the p-channel transistor and the transistor active region 405 for the n-channel transistor can be formed at the same time in the step shown in FIG. After that, a gate electrode having a structure suitable for each conductivity type transistor can be formed, so that a CMOS transistor can be manufactured without complicated processes. In particular, according to the manufacturing method of the present embodiment, the transistor threshold value is set to an optimum value according to the conductivity type of the transistor by appropriately forming the first gate electrode 602 and the second gate electrode 503. Therefore, the performances of the n-channel transistor and the p-channel transistor can be made equal. Therefore, a CMOS transistor composed of Fin transistors can be easily manufactured without providing restrictions such as layout.

  In the semiconductor devices according to the first and second embodiments described above, the transistor active regions 104 and 405 may further include a slope having a plane orientation different from that of the upper surface and the side surface, and the gate electrode May be further provided on this slope.

  Note that what has been described above is an example of an embodiment of the present invention, and the material, size, and the like of each member are not limited to the above-described embodiment, and the semiconductor device is within the scope of the present invention. The configuration and manufacturing method may be changed.

  As described above, the present invention is useful for improving the characteristics of a semiconductor device having Fin transistors and improving the manufacturing process.

101 Silicon oxide film 102, 402 Silicon layer 103, 404 Active region pattern 104, 405 Transistor active region 105 HK insulating film 105a, 615 Gate insulating film 106 Metal film 106a Lower gate electrode 201, 504 Organic insulating film 203 Polysilicon film 301 409 Gate electrode formation pattern 303 Upper gate electrodes 304, 305, 604, 605 Source / drain regions 306 Upper surface gate electrode 307 Side surface gate electrodes 350, 610 Gate electrode 401 Silicon oxide film 402 Silicon layer 403a First gate insulation Film 403 First HK insulating film 407 Second HK insulating film 407a Second gate insulating film 408 Second metal film 503 Second gate electrode 602 First gate electrode

Claims (14)

A substrate,
A transistor active region made of a convex semiconductor provided on the substrate;
A gate insulating film provided on a side surface and an upper surface of a part of the transistor active region;
A gate electrode provided on a side surface and an upper surface of a part of the transistor active region with the gate insulating film interposed therebetween,
A semiconductor device in which a configuration of a portion of the gate electrode provided on a side surface of the transistor active region and a configuration of a portion provided on an upper surface of the transistor active region are different from each other. The semiconductor device according to claim 1,
The gate electrode includes a first gate electrode provided on a side surface and an upper surface of a part of the transistor active region with the gate insulating film interposed therebetween, and a first gate electrode provided on the first gate electrode. Two gate electrodes,
The film thickness of the portion of the first gate electrode provided above the transistor active region and the film thickness of the portion of the first gate electrode provided on the side of the transistor active region are mutually different. A semiconductor device characterized by being different. The semiconductor device according to claim 2,
The thickness of the portion of the first gate electrode provided above the transistor active region is smaller than the thickness of the portion of the first gate electrode provided on the side of the transistor active region. A semiconductor device. The semiconductor device according to claim 1,
2. The semiconductor device according to claim 1, wherein the constituent material of the first gate electrode is a metal material or a metal compound, and the constituent material of the second gate electrode is polysilicon. The semiconductor device according to claim 1,
The gate electrode is provided on a side surface of the transistor active region with the gate insulating film interposed between the first gate electrode provided on the upper surface of the transistor active region with the gate insulating film interposed therebetween. And a second gate electrode made of a material different from that of the first gate electrode. The semiconductor device according to claim 5,
The gate insulating film is provided between the first gate insulating film provided between the first gate electrode and the transistor active region, and between the second gate electrode and the transistor active region. A semiconductor device comprising: a second gate insulating film. , The semiconductor device according to claim 6.
The semiconductor device, wherein the first gate insulating film and the second gate insulating film are made of different materials. The semiconductor device according to claim 6 or 7,
The first gate electrode and the second gate electrode are electrically separated by the second gate insulating film, and the first gate electrode and the second gate electrode include gates independent of each other. A semiconductor device, wherein a voltage is applied. Forming a first pattern on the semiconductor layer of the substrate having a semiconductor layer thereon (a);
Etching the semiconductor layer using the first pattern as a mask to form a transistor active region composed of a semiconductor;
(C) sequentially forming a first insulating film and a metal film on the substrate including the transistor active region;
A step (d) of thinning a portion of the metal film provided above the transistor active region;
After the step (d), a step (e) of forming a second pattern above the transistor active region so as to straddle the transistor active region;
Etching at least the metal film and the first insulating film using the second pattern as a mask, provided on a part of side surfaces and an upper surface of the transistor formation region, and from a part of the first insulating film And a film thickness of a portion provided on the gate insulating film and above the transistor formation region is smaller than a film thickness of a portion provided on the side of the transistor formation region, And (f) forming a first gate electrode made of a part of the metal film. In the manufacturing method of the semiconductor device according to claim 9,
The step (e) includes a step (e1) of forming a conductive film on the metal film and a step (e2) of forming the second pattern on the conductive film,
In the step (f), the conductive film is etched together with the metal film and the first insulating film using the second pattern as a mask, and a part of the conductive film is formed on the first gate electrode. A method for manufacturing a semiconductor device, comprising forming a second gate electrode. In the manufacturing method of the semiconductor device according to claim 9 or 10,
In the step (d), after forming a second insulating film on the metal film, the transistor active region is thinned together with etch back or chemical mechanical polishing of the second insulating film. A method for manufacturing a semiconductor device. (A) patterning the first metal film after sequentially forming a first insulating film and a first metal film on the semiconductor layer of the substrate having a semiconductor layer thereon;
The first insulating film and the semiconductor layer are etched using the first metal film as a mask, and sandwiched between a transistor active region made of a semiconductor, the transistor active region, and the first metal film (B) forming a first gate insulating film made of a part of the first insulating film;
A step (c) of sequentially forming a second insulating film and a second metal film on the substrate including the transistor active region, on a side surface and an upper surface of the first metal film;
A step (d) of forming a first gate electrode formation pattern straddling the transistor active region on the second metal film;
The second metal film, the second insulating film, the first metal film, and the first gate insulating film are etched using the first gate electrode formation pattern as a mask, and the transistor formation region is etched. A second gate insulating film provided on a part of the side surface, part of the side surface and the upper surface of the first metal film, and comprising a part of the second insulating film; and the second gate insulating film A second gate electrode made of the second metal film, a side surface and an upper surface being surrounded by the second gate electrode with the second gate insulating film interposed therebetween, and the first metal Forming a first gate electrode comprising a portion of the film (e);
A portion of the second gate electrode and the second gate insulating film formed above the transistor active region is removed, and the second gate electrode is formed on the transistor active region and the first gate electrode. A method of manufacturing a semiconductor device comprising a step (f) to be left laterally. In the manufacturing method of the semiconductor device according to claim 12,
After the step (f), after forming a conductive film on the substrate, on the first gate electrode, and on the second gate electrode, a second gate electrode formation pattern straddling the transistor active region Forming on the conductive film (g),
The conductive film is etched using the second gate electrode formation pattern as a mask, and a third gate electrode made of a part of the conductive film is formed on the first gate electrode and the second gate electrode. And a step (h) of forming a semiconductor device. In the manufacturing method of the semiconductor device according to claim 12 or 13,
In the step (f), a third insulating film is formed on the substrate, the first gate electrode, and the second gate electrode, and then the third insulating film is etched back or chemically mechanically polished. In addition, a method of manufacturing a semiconductor device, wherein a portion of the second gate electrode and the second gate insulating film formed above the transistor active region is removed.

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