JP2010287159A - Signal processing system, signal processing module, and method of operating them - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a signal processing system that uses a simplified procedure between a CPU module and a signal processing module for changing the processing content of the signal processing module. <P>SOLUTION: The signal processing system includes a control means for sending target data to be subjected to signal processing to which processing content identification information identifying the content of processing is added as added information, and a signal processing means for recognizing the processing content identification information added to the data sent, reconfiguring a signal processing circuit according to signal processing circuit configuration information corresponding to the recognized processing content identification information, and processing the target data included in the data sent by means of the reconfigured signal processing circuit. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a signal processing system that performs signal processing using a control device and a reconfigurable signal processing device.

  Image processing and signal processing require large amounts of data to be performed at high speed and in real time. When simple processing, which is a feature of signal processing, is repeated, the general-purpose CPU is inefficient in processing. Therefore, processing is performed by dedicated hardware using FPGA (Field Programmable Gate Array) or ASIC (Application Specific Integrated Circuit).

  FIG. 1 shows a processing flow of a conventional signal processing system 101. FIG. 2 shows a processing flow of the conventional signal processing system 1. FIG. 1 shows an example in which a DRP (Dynamic Reconfigurable Processor) is used as the signal processing module 103.

  First, the CPU (Central Processing Unit) module 102 instructs the signal processing module 103 that can reconfigure the signal processing circuit via the data bus 105 to reconfigure the signal processing circuit (S101). . For example, the CPU module 102 instructs the signal processing module 103 to reconfigure the signal processing circuit using the configuration information C1.

  When the signal processing module 103 receives the reconfiguration instruction from the CPU module 102, the signal processing device 104 reconfigures the circuit using the configuration information corresponding to the reconfiguration instruction (S102). When the circuit reconfiguration is completed, the signal processing module 103 notifies the CPU module 102 that the reconfiguration is completed (S103).

Steps S101 to S103 are repeated until the reconfiguration of the circuits of all the signal processing modules 103 that are to be changed in the circuit configuration of the signal processing device is completed (S104).
When the reconfiguration of the circuits of all the signal processing modules 103 is completed, the CPU module 102 transmits the processing data 111 to the signal processing module 103 (S105).

  When receiving the processing data from the CPU module 102, the signal processing module 103 executes processing on the processing data 111 (S106). After the processing is completed, the signal processing module 103 transmits a processing result 112 to the CPU module 102 (S107).

  As described above, a signal processing device such as DRP or FPGA can realize a plurality of functions by reconfiguring the signal processing circuit using circuit information (configuration data) held therein.

Japanese Patent Laid-Open No. 11-83559 JP 2001-7883 A JP 2006-18539 A JP 2008-90360 A

  However, when a plurality of functions are realized by dedicated hardware, more hardware resources are required, leading to an increase in the size of the apparatus and an increase in power consumption. Further, there has been a problem that it is not possible to easily add or change functions.

  As described with reference to FIGS. 1 and 2, when changing the processing contents of the signal processing module, the CPU module instructs the signal processing module in advance to reconfigure the circuit, It is necessary to restart the processing after the reconfiguration of the signal processing circuit inside the signal processing device is completed. Therefore, when performing signal processing simultaneously by a plurality of signal processing devices, the CPU module uses a plurality of signal processing modules such as a reconfiguration instruction to a plurality of signal processing modules and confirmation of a reconfiguration completion notification from the signal processing module. It was necessary to manage it separately. Therefore, the control at the time of reconfiguration of the signal processing circuit has been complicated (for example, Patent Document 1).

  In view of the above problems, the present invention provides a signal processing system that simplifies the procedure between a CPU module and a signal processing module in changing the processing content of the signal processing module.

  The signal processing system includes control means for adding processing content identification information for identifying processing content as additional information to target data to be subjected to signal processing, and transmitting the processing added to the transmitted data. The content identification information is determined, the signal processing circuit is reconfigured based on the configuration information of the signal processing circuit corresponding to the determined processing content identification information, and included in the data transmitted by the reconfigured signal processing circuit Signal processing means for processing the target data to be processed.

  A signal processing module used in a signal processing system including a control processing module obtains transmitted data by adding processing content identification information for identifying processing content as additional information to target data to be subjected to signal processing. An acquisition means and the processing content identification information added to the acquired data are discriminated, and the signal processing circuit is reconfigured based on the configuration information of the signal processing circuit corresponding to the discriminated processing content identification information. Signal processing means for processing the target data included in the transmitted data by a configured signal processing circuit.

  In the operation method of the signal processing system, the control module transmits the processing content identification information for identifying the processing content as additional information to the target data to be processed by the signal processing, and transmits the additional information by the signal processing module. The processing content identification information added to the data is determined, the signal processing circuit is reconfigured based on the configuration information of the signal processing circuit corresponding to the determined processing content identification information, and the reconfigured signal processing circuit To process the target data included in the transmitted data.

  In the operation method of the signal processing module used in the signal processing system including the control processing module, the data transmitted by adding the processing content identification information for identifying the processing content to the target data to be subjected to signal processing as additional information. , Determining the processing content identification information added to the acquired data, reconfiguring the signal processing circuit based on the configuration information of the signal processing circuit corresponding to the determined processing content identification information, The target data included in the transmitted data is processed by the configured signal processing circuit.

  According to the disclosed signal processing system, it is possible to simplify the procedure between the CPU module and the signal processing module when changing the processing content of the signal processing module.

The flow of the process of the conventional signal processing system 101 is shown. The processing flowchart of the conventional signal processing system 1 is shown. An example of the structure of the signal processing system 1 in 1st Embodiment is shown. It is an example of the structure information management table 10 which shows a response | compatibility of the structure information required with respect to the some process in 1st Embodiment. The structure of the processing data (transmission data 20) transmitted from the CPU module 2 to the signal processing module 3 in the first embodiment is shown. The flow of a process of the signal processing system 1 in 1st Embodiment is shown. The operation | movement flow of the signal processing system 1 in 1st Embodiment is shown. The internal structure of the signal processing module 3 in 1st Embodiment is shown. An example of the structure of the signal processing system 51 in 2nd Embodiment is shown. The structure of the processing data (transmission data 60) transmitted from the CPU module 2 to the signal processing module 3 or the signal processing module 3 to another signal processing module in the third embodiment is shown. The operation | movement flow of the signal processing system 1 in 3rd Embodiment is shown.

<First Embodiment>
FIG. 3 shows an example of the configuration of the signal processing system 1 in the present embodiment. In the signal processing system 1, the CPU module 2 and the signal processing modules 3 (3-1 to 3 -n) are connected by a data bus (for example, a PCI bus) 5. Note that m, n, and o are arbitrary integers.

  In FIG. 3, the CPU module 2 has processing data 11 (11-1 to 11-m). The signal processing modules 3-1 to 3-n have configuration information of configuration information C 1 to Co. The configuration information is circuit information (configuration data) of the logic circuit. By reconfiguring the circuit using such internal circuit information, the signal processing module 3 can realize a plurality of functions.

  The processing data 11 (11-1 to 11-m) is transferred from the CPU module 2 to the signal processing module 3 via the data bus 5. The signal processing module 3 executes processing on the transmitted processing data 11. The processing result is transferred from the signal processing module 3 to the CPU module 2.

  The signal processing module 3 includes a signal processing device (for example, DRP) 4 (4-1 to 4-n) for performing signal processing and a plurality of pieces of configuration information C (C1 to Co) for performing signal processing. .

  FIG. 4 is an example of the configuration information management table 10 showing the correspondence between the processing to be performed by the signal processing module and the configuration information necessary for each processing in the present embodiment. The configuration information management table 10 is stored in the memory in the CPU module 2. In the configuration information management table 10, information for identifying each configuration information, that is, processing content identification information is set in the processing content identification information 1, 2, 3.

  In the case of FIG. 4, when executing the process P1, for example, it is assumed that the configuration information C1 and C2 are necessary. Further, when executing the process P2, for example, it is assumed that the configuration information C3, C4, and C5 are necessary. When executing the process P3, for example, it is assumed that the configuration information C6 is necessary.

  In this case, as shown in FIG. 4, for the process P1, the process content identification information ID-C1 corresponding to the configuration information C1 is preset in the process content identification information 1. In the processing content identification information 2, processing content identification information ID-C2 corresponding to the configuration information C2 is set in advance. As the number of process content identification information, the number “2” of process content identification information in the process P1 is set in advance.

  For process P2, process content identification information ID-C3 corresponding to configuration information C3 is set in advance in process content identification information 1. In the processing content identification information 2, processing content identification information ID-C4 corresponding to the configuration information C4 is set in advance. In the processing content identification information 3, processing content identification information ID-C5 corresponding to the configuration information C5 is set in advance. The number of process content identification information “3” in the process P2 is set in advance as the number of process content identification information.

  For process P3, process content identification information ID-C6 corresponding to configuration information C6 is set in advance in process content identification information 1. As the number of process content identification information, the number “1” of process content identification information in process P3 is set in advance.

  FIG. 5 shows the structure of the processing data (transmission data 20) transmitted from the CPU module 2 to the signal processing module 3 in this embodiment. The transmission data 20 includes header information 21 and processing data 11. The header information 21 includes a processing content identification information number 22, processing content identification information 1 to n (23), a processing result storage address 24, and a transmission destination address (not shown).

  As the processing content identification information number 22, the number of processing content identification information 23 set in the header information 21 is set. The processing content identification information 23 is processing content identification information read from the configuration information management table 10. The processing result storage address 24 stores an address (for example, an address on the memory of the CPU module 2) of the storage destination of the processing result processed and output by the signal processing module 3.

FIG. 6 shows a processing flow of the signal processing system 1 in the present embodiment. FIG. 7 shows an operation flow of the signal processing system 1 in the present embodiment.
The memory in the CPU module 2 has one or more memories having areas for storing the processing data 11, the processing result data 12, and the configuration information management table 10. In this memory, processing data 11 and a configuration information management table 10 are stored in advance.

  The signal processing module 3 includes a signal processing device 4 that is a part for reconfiguring a circuit, a plurality of memories, and the like. The signal processing device 4 includes a plurality of arithmetic units, wiring portions of those arithmetic units, a reconfiguration control circuit that controls the circuit configuration, and the like. In these memories, wiring information (configuration information) C1, C2,..., Cn between arithmetic units for circuit reconfiguration is stored.

  First, the CPU module 2 searches for a signal processing module 3 that is not executing processing (S1). When the signal processing module 3 that is not executing processing is searched, the CPU module 2 searches the configuration information management table 10 for the number of processing content identification information and the processing content corresponding to the configuration information C of the signal processing circuit required for the processing to be executed. Identification information is acquired (S2). For example, in FIG. 4, when the process P1 is performed, the CPU module 2 determines from the configuration information management table 10 that the number of process content identification information “2” and the process content identification information “ID-C1” and “ID-C2”. To get.

  As described with reference to FIG. 5, the CPU module 2 stores information acquired from the configuration information management table 10 (processing content identification information, number of processing content identification information) and processing results for the processing data 11. Information is added as header information 21 (S3). For example, the CPU module 2 has “2” as the processing content identification information number 22, “ID-C1” and “ID-C2” as the processing content identification information 23, and a predetermined memory in the CPU module 2 as the processing result storage address 24. Header information 21 in which the address is set is generated. Then, the CPU module 2 adds the generated header information 21 to the processing data 11.

  The CPU module 2 transmits the processing data 11 with the header information 21 added thereto as transmission data 20 to the signal processing module 3 searched in S1 via the data bus 5 (S4).

  If a plurality of signal processing modules 3 that are not being processed are searched in S1, the CPU module 2 performs S2-S4 on each signal processing module 3 in accordance with a predetermined order and transmits the transmission data 20. .

  The signal processing module 3 receives the transmission data 20 and reads the header information 21 (S5). Based on the header information 21, the signal processing module 3 determines processing content identification information. The signal processing module 3 reads configuration information C corresponding to the determined processing content identification information from its own memory.

  For example, the signal processing module 3 reads the processing content identification information sequentially from the head side of the header information 21 and determines the first processing content identification information “ID-C1”. Then, the signal processing module 3 reads the configuration information C1 corresponding to the processing content identification information “ID-C1” from the memory in the signal processing module 3.

  The signal processing module 3 reconfigures the circuit of the signal processing device 4 based on the read configuration information C (S6). In the case of the above example, the signal processing module 3 uses the configuration information C1 to change the wiring state between the arithmetic units in the signal processing device 4 and reconfigure the circuit of the signal processing device 4.

  After completion of the reconfiguration processing, the signal processing module 3 extracts the processing data 11 from the transmission data 20, and uses the reconfigured signal processing device 4 to execute processing using the processing data 11 as input data (S7). .

  The processing of S6 to S7 is performed for all the configuration information corresponding to each processing content identification information in the header information 21 (S8). For example, in the case of the above example, the signal processing module 3 processes the processing data 11 by the signal processing device 4 reconfigured using the configuration information C1, and outputs the processed data 11-C1 after the processing. . Thereafter, the signal processing module 3 performs processing on the processing data 11-C1 by the signal processing device 4 reconfigured using the configuration information C2 corresponding to the processing content identification information “ID-C2”. The processing data 11-C2 is output as processing result data.

  After completing the processing for all the configuration information corresponding to each processing content identification information in the header information, the signal processing module 3 sends the processing result data 12 to the processing result storage address 24 of the header information 21 via the data bus 5. Is transmitted to the CPU module 2 (S9). The CPU module 2 receives the processing result data, and stores the processing result data 12 in a predetermined area on the memory specified by the processing result storage address.

  FIG. 8 shows an example of the internal configuration of the signal processing module 3 in the present embodiment. The signal processing module 3 includes a memory 31, an input data transfer control circuit 34, a signal processing device 4, and an output data transfer control circuit 35.

  The memory 31 includes a configuration information storage area 32 and a processing data storage area 33. The configuration information storage area 32 stores the processing content identification information and configuration information C (C1 to Cm) for reconfiguring the signal processing circuit corresponding to the processing content identification information. In the processing data storage area 33, the transmission data 20 transmitted from the CPU module 2 can be stored in a state of being divided into header information 21-1 to 21-n and processing data 11-1 to 11-n. .

The input data transfer control circuit 34 transfers the transmission data 20 input from the data bus 5 to the signal processing device 4.
The signal processing device 4 reconfigures a circuit in the signal processing device 4 using configuration information corresponding to the processing content identification information of the transmission data 20. Then, the signal processing device 4 inputs the processing data 11 of the transmission data 20 to the reconfigured circuit and performs processing.

  The signal processing device 4 includes a data input processing circuit 41, a signal processing circuit 42, a data output processing circuit 43, a reconfiguration control circuit 44, and a configuration information storage area 45 for storing configuration information. The configuration information C that cannot be stored in the configuration information storage area 45 is stored in the configuration information storage area on the memory 31.

  The data input processing circuit 41 divides the transmission data 20 input from the input data transfer control circuit 34 into header information 21 and processing data 11 and transfers them to the memory 31. The header information 21 and the processing data 11 transferred to the memory 31 are stored in the processing data storage area 33, respectively.

  The reconfiguration control circuit 44 determines the processing content identification information of the header information 21 read from the processing data storage area 33 and stores the configuration information C corresponding to the processing content identification information in the configuration information storage area 45 or the configuration information storage. Obtained from area 32. The reconfiguration control circuit 44 reconfigures the signal processing circuit 42 using the acquired configuration information C.

  The signal processing circuit 42 includes a plurality of arithmetic units and a wiring portion of the arithmetic units. The signal processing circuit 42 is reconfigured under the control of the reconfiguration control circuit 44 based on the configuration information C. The reconfigured signal processing circuit 42 reads the processing data 11 corresponding to the header information 21 read from the processing data storage area 33 and executes processing on the processing data 11. The signal processing circuit 42 reconfigured based on the configuration information C corresponding to each processing content identification information included in the header information 21 reconfigures and reconfigures the signal processing circuit 42 until the processing data is processed. The signal processing for the processed data by the signal processing circuit 42 is repeated. The processing result data is output to the data output processing circuit 43.

  The data output processing circuit 43 generates header information with the processing result storage address of the header information 21 corresponding to the processing result data as the transmission destination address. The data output processing circuit 43 adds the generated header information 21 to the processing result data and transmits it to the output data transfer control circuit 35.

  The output data transfer control circuit 35 outputs the processing result data transmitted from the data output processing circuit 43 to the data bus 5. The processing result data is transmitted to the transmission destination based on the transmission address of the generated header information.

  The data input processing circuit 41, the signal processing circuit 42, and the data output processing circuit 43 can operate independently. Therefore, the data input processing circuit 41 can receive new processing data even while the signal processing circuit 42 is executing processing. Even when the processing result by the data output processing circuit 43 is being output, the reconfigured signal processing circuit 42 can start a new process.

  As described above, the signal processing module 3 holds the configuration information of the signal processing circuit necessary for all processes. Then, the CPU module 2 adds the header information 21 including the processing content identification information and the address information for storing the processing result to the processing data 11 and transmits it to the signal processing module 3 as transmission data 20. The signal processing module 3 that has received the transmission data 20 discriminates the processing content identification information from the header information 21, reconfigures the signal processing device using the corresponding circuit configuration information C, and then processes the received data. Do.

  For example, a DRP, which is one of signal processing devices, can be reconfigured instantaneously even during operation, unlike an FPGA that reads configuration data at startup or reset. Therefore, when assigning the processing data to the signal processing module, it is not necessary to reconfigure the signal processing device in advance.

  Further, in such a signal processing circuit system, the CPU module instructs the reconfigurable signal processing module to reconfigure the signal processing device, confirms completion of the reconfiguration of the signal processing device, etc. It is not necessary to individually manage a plurality of reconfigurable signal processing modules. Therefore, in the implementation of a plurality of signal processing, the CPU module reduces management of these signal processing modules when assigning the processing data to each signal processing module.

  In addition, when a signal processing module such as DRP is used, it is possible to realize a signal processing system that can handle processing using a plurality of functions on the same hardware. In addition, by providing such a signal processing module with a plurality of pieces of information as identification information of processing contents, a plurality of processes can be executed in one data transfer.

<Second Embodiment>
In the first embodiment, the signal processing system in which the CPU module 2 and the signal processing module 3 are connected by the data bus 5 has been described. On the other hand, in the second embodiment, a signal processing system in which the CPU module 2 and the signal processing module 3 are connected via a network will be described. In addition, about the structure and process same as 1st Embodiment, the same code | symbol is attached | subjected and the description is abbreviate | omitted.

FIG. 9 shows an example of the configuration of the signal processing system 51 in the present embodiment. 9 is obtained by replacing the data bus 5 connecting the CPU module 2 and the signal processing module 3 in the signal processing system 1 of FIG. 3 with a network 52 such as Ethernet (registered trademark). is there.
As a result, the same effects as those of the first embodiment can be obtained for a large-scale signal processing system 51 via a network.

<Third Embodiment>
In the third embodiment, a signal processing system will be described in which a plurality of processing content identification information and processing result storage address information are added to header information, and pipeline processing is performed using a plurality of signal processing modules. The configuration of the signal processing system is the same as that of the first or second embodiment. In addition, about the structure and process same as 1st or 2nd embodiment, the same code | symbol is attached | subjected and the description is abbreviate | omitted.

  FIG. 10 shows the structure of processing data (transmission data 60) transmitted from the CPU module 2 to the signal processing module 3 or from one signal processing module 3 to another signal processing module in the present embodiment.

  The transmission data 60 is composed of header information 61 and processing data 11. The header information 61 includes a header size 62, a plurality of pairs of processing content identification information 63 (63-1 to 63-n), and processing result storage addresses (64-1 to 64-n).

In the header information 62, the sum of data sizes of a plurality of pairs of processing content identification information 63 (63-1 to 63-n) and processing result storage addresses (64-1 to 64-n) is set.
The processing content identification information 63 (63-1 to 63-n) is processing content identification information read from the configuration information management table 10. Each processing result storage address 63-i (1 ≦ i ≦ n) stores processing data after being processed by the signal processing device reconfigured based on the configuration information corresponding to the paired processing content identification information. The destination address is set. Note that the address of the signal processing module to be reconfigured first based on the configuration information corresponding to the processing content identification information 63-1 is also included in the header information 61 although not shown.

  FIG. 11 shows an operation flow of the signal processing system 1 in the present embodiment. First, the CPU module 2 searches for a signal processing module 3 that is not executing processing (S11). The signal processing module has a predetermined priority order.

  When the signal processing module 3 that is not executing processing is searched, the CPU module 2 acquires from the configuration information management table 10 processing content identification information corresponding to the configuration information C of the signal processing circuit required for the processing to be executed ( S12).

  As described with reference to FIG. 10, the CPU module 2 adds the information acquired from the configuration information management table 10 and the address information in which the processing result is stored to the processing data 11, and creates the transmission data 60 (S13). .

  That is, when a plurality of signal processing modules 3 that are not being processed are searched, the CPU module 2 sets the order of the signal processing modules 3 in accordance with the priority order, and as described with reference to FIG. A pair of (1 ≦ i ≦ n) and the processing result storage address 63-i is added to the header information. In the processing result storage address 63-i (1 ≦ i ≦ n), the storage destination of the processing data after being processed by the signal processing device reconfigured based on the configuration information corresponding to the paired processing content identification information Address is set. Note that the address of the signal processing module to be reconfigured first based on the configuration information corresponding to the processing content identification information 63-1 (that is, the first signal processing module 3 in the order set above) is also invalid. Although shown, it is included in the header information 61. In addition, the processing result storage address n stores an address of a final processing result storage destination (for example, an address on the memory of the CPU module 2).

The CPU module 2 transmits the processing data 11 to which the header information 61 created in S11 is added as transmission data 60 via the data bus 5 (S14).
The signal processing module 3 receives the transmission data 60 and reads the header information 61 (S15). Based on the header information 61, the reconfiguration control circuit 44 in the signal processing module 3 determines the top processing content identification information. The reconfiguration control circuit 44 reads the configuration information C corresponding to the determined processing content identification information from the configuration information storage area 45 or the configuration information storage area 32.

The reconfiguration control circuit 44 reconfigures the circuit of the signal processing circuit 42 based on the read configuration information C (S16).
The reconfigured signal processing circuit 42 reads the processing data 11 corresponding to the header information 61, and executes processing on the processing data 11 (S17). The processing result data is output to the data output processing circuit 43.

  The data output processing circuit 43 deletes the first pair of processing content identification information 63-1 and the processing result storage address 64-1 from the header information 61, and the second pair of processing content identification information 63-2 and the processing. A result storage address 64-2 at the head and the header size recalculated is generated as new header information 61 (S19). Note that the destination address is the processing result storage address 64-1 deleted above. The data output processing circuit 43 adds the generated header information 61 to the processing result data and transmits it to the output data transfer control circuit 35.

  The output data transfer control circuit 35 outputs the processing result data transmitted from the data output processing circuit 43 to the data bus 5. The processing result data is transmitted to the other signal processing module 3 that is the transmission destination based on the transmission address of the generated header information (S20).

The processing of S15 to S20 is performed for all the configuration information corresponding to each processing content identification information in the header information 61 (S18).
After the processing for all the configuration information corresponding to each processing content identification information in the header information is completed, the signal processing module 3 that has performed the processing lastly stores the processing result data 12 in the processing result storage address of the header information 61, The data is transmitted to the CPU module 2 via the data bus 5 (S21). The CPU module 2 receives the processing result data, and stores the processing result data in a predetermined area on the memory specified by the processing result storage address.

  According to the present embodiment, the same effect as that of the first embodiment can be obtained even when the predetermined processing data is sequentially processed by a plurality of reconfigurable signal processing modules.

  Although the DRP is used as the signal processing device in the first to third embodiments, the present invention is not limited to this. For example, an FPGA that can be reconfigured only in the signal processing circuit or a CPLD (Complex Programmable Logic Device) is used. It may be used.

As described above, the signal processing system in the first to third embodiments includes a control unit and a signal processing unit.
The control means adds processing content identification information for identifying processing content as additional information to the target data to be subjected to signal processing, and transmits it. For example, the control means corresponds to the CPU module 2 in the above embodiment. The control means includes storage means for storing process content identification information for identifying configuration information for configuring a signal processing circuit corresponding to each of one or more signal processes constituting a predetermined process. For example, the storage means corresponds to the configuration information management table 10 in the above embodiment.

The signal processing means determines the processing content identification information added to the transmitted data. Then, the signal processing means reconfigures the signal processing circuit based on the configuration information of the signal processing circuit corresponding to the determined processing content identification information. Further, the signal processing means processes the target data included in the transmitted data by the reconfigured signal processing circuit.
The signal processing means corresponds to the signal processing module 3 in the above embodiment, for example.
With this configuration, the procedure between the CPU module and the signal processing module when changing the processing contents of the signal processing module can be simplified.

  According to the first embodiment, the control unit can add a plurality of pieces of processing content identification information as additional information to the target data. In this case, the signal processing means sequentially determines the processing content identification information included in the additional information. Then, the signal processing means identifies the processing content identification determined next for the target data processed by the signal processing circuit reconfigured based on the configuration information of the signal processing circuit corresponding to the determined processing content identification information. Processing can be performed by the signal processing circuit reconfigured based on the configuration information of the signal processing circuit corresponding to the information.

  More specifically, the signal processing means includes acquisition means, configuration information storage means, signal processing circuit, and reconfiguration control means. The acquisition unit acquires data transmitted from the control unit. The acquisition means corresponds to the input data transfer control circuit 34 in the above embodiment, for example.

  The configuration information storage means stores the processing content identification information and the configuration information of the signal processing circuit corresponding to the processing content identification information. The configuration information storage means corresponds to, for example, the configuration information storage area 32 or the configuration information storage area 45 in the above embodiment.

  The signal processing circuit can reconfigure a circuit that performs signal processing, and processes the target data using the reconfigured circuit. For example, the signal processing circuit corresponds to the signal processing circuit 42 in the above embodiment.

  The reconfiguration control unit sequentially determines processing content identification information included in the additional information of the acquired data, acquires configuration information corresponding to the determined processing content identification information from the configuration information storage unit, and acquires the acquired The reconfiguration of the signal processing circuit is controlled using the configuration information. For example, the reconstruction control means corresponds to the reconstruction control circuit 44 in the above embodiment.

In this case, the signal processing circuit after the reconfiguration can process the target data processed by the signal processing circuit before the reconfiguration.
With this configuration, by adding a plurality of process content identification information to the header information, it is possible to execute a plurality of processes with one transfer of process data.

  According to the second embodiment, the control means and the signal processing means are connected via a network. With this configuration, even for a large-scale signal processing system 51 via a network, a plurality of processing content identification information is added to the header information, so that a plurality of processings can be executed by transferring processing data once. can do.

  According to the third embodiment, the control means stores the processing content identification information and the storage destination address of the target data after processing by the signal processing circuit reconfigured based on the configuration information corresponding to the processing content identification information. Can be used as additional information. In this case, the signal processing means determines the processing content identification information included in the additional information. Then, the signal processing means pairs the target data processed by the signal processing circuit reconfigured based on the configuration information of the signal processing circuit corresponding to the determined processing content identification information with the processing content identification information. Can be transmitted to the processing result storage address.

  More specifically, the signal processing means includes acquisition means, configuration information storage means, signal processing circuit, reconstruction control means, additional information editing means, and transmission means. The acquisition unit acquires data transmitted from the control unit. The acquisition means corresponds to the input data transfer control circuit 34 in the above embodiment, for example.

  The configuration information storage means stores the processing content identification information and the configuration information of the signal processing circuit corresponding to the processing content identification information. The configuration information storage means corresponds to, for example, the configuration information storage area 32 or the configuration information storage area 45 in the above embodiment.

  The signal processing circuit can reconfigure a circuit that performs signal processing, and processes the target data using the reconfigured circuit. For example, the signal processing circuit corresponds to the signal processing circuit 42 in the above embodiment.

  The reconfiguration control unit determines processing content identification information included in the additional information of the acquired data, acquires configuration information corresponding to the determined processing content identification information from the configuration information storage unit, and acquires the acquired configuration The signal processing circuit is reconfigured using the information. For example, the reconstruction control means corresponds to the reconstruction control circuit 44 in the above embodiment.

  After the processing of the target data by the reconfigured signal processing circuit, the additional information editing means, from the additional information, processing content identification information corresponding to the configuration information that is the basis of the reconfiguration, and the processing content identification It is possible to edit the additional information by deleting the processing result storage address paired with the information, and add the edited additional information to the processed target data. The additional information editing means corresponds to the data output processing circuit 43 in the above embodiment, for example.

  The transmission means can transmit the processed target data to which the edited additional information is added to the deleted processing result storage address. For example, the transmission means corresponds to the output data transfer control circuit 35 in the above embodiment.

Furthermore, when the signal processing means receives the target data transmitted to the processing result storage address, it determines the processing content identification information. The signal processing means pairs the target data processed by the signal processing circuit reconfigured based on the configuration information of the signal processing circuit corresponding to the determined processing content identification information with the processing content identification information. It can be transmitted to the processing result storage address.
With this configuration, the processing can be sequentially performed by a plurality of reconfigurable signal processing modules with one transfer of processing data.

  According to the first to third embodiments, when the processing data is processed by each reconfigurable signal processing module, the procedure for reconfiguring the processing contents does not have to be taken separately. Reconfiguration can be performed. That is, by adding a plurality of process content identification information to the header information, a plurality of processes can be executed by transferring the process data once. As a result, overhead during data transfer can be reduced.

  Further, in the system for reconfiguring the signal processing circuit according to the first to third embodiments, a signal processing device reconfiguration instruction to a plurality of signal processing modules, confirmation of reconfiguration completion notification from the signal processing module, etc. The CPU module does not have to manage a plurality of signal processing modules individually. Instead, the signal processing module side determines the processing content requested by the CPU module.

Therefore, the CPU module does not need to individually manage the reconfiguration of the signal processing module, and can transmit data having different processing contents to the signal processing module. Therefore, it is possible to realize a signal processing system that can efficiently use hardware resources and can easily change the internal configuration of the signal processing device.
The present invention is not limited to the above-described embodiment, and various configurations or embodiments can be taken without departing from the gist of the present invention.

Regarding the above embodiment, the following additional notes are disclosed.
(Appendix 1)
Control means for adding processing content identification information for identifying processing content as additional information to target data to be subjected to signal processing;
The processing content identification information added to the transmitted data is determined, a signal processing circuit is reconfigured based on configuration information of the signal processing circuit corresponding to the determined processing content identification information, and the reconfigured Signal processing means for processing the target data included in the transmitted data by a signal processing circuit;
A signal processing system comprising:
(Appendix 2)
The control means adds a plurality of the processing content identification information as additional information to the target data,
The signal processing means sequentially determines the processing content identification information included in the additional information, and performs processing by the signal processing circuit reconfigured based on the configuration information of the signal processing circuit corresponding to the determined processing content identification information. The signal processing system according to claim 1, wherein the target data is processed by a signal processing circuit reconfigured based on configuration information of the signal processing circuit corresponding to the processing content identification information determined next. .
(Appendix 3)
The signal processing means includes
Obtaining means for obtaining data transmitted from the control means;
Configuration information storage means for storing the processing content identification information and configuration information of a signal processing circuit corresponding to the processing content identification information;
A signal processing circuit that can reconfigure a circuit that performs signal processing, and that processes the target data using the reconfigured circuit;
Processing content identification information included in the additional information of the acquired data is sequentially determined, configuration information corresponding to the determined processing content identification information is acquired from the configuration information storage means, and the acquired configuration information is used to Reconfiguration control means for controlling reconfiguration of the signal processing circuit;
With
The signal processing system according to appendix 2, wherein the reconfigured signal processing circuit processes the target data processed by the pre-reconstructed signal processing circuit.
(Appendix 4)
The control means includes the processing content identification information, a processing result storage address that represents a storage destination address of target data after processing by a signal processing circuit reconfigured based on configuration information corresponding to the processing content identification information, And the additional information as a pair,
The signal processing means determines the processing content identification information included in the additional information and is processed by a signal processing circuit reconfigured based on the configuration information of the signal processing circuit corresponding to the determined processing content identification information. The signal processing system according to appendix 1, wherein the target data is transmitted to a processing result storage address paired with the processing content identification information.
(Appendix 5)
The signal processing means includes
Obtaining means for obtaining data transmitted from the control means;
Configuration information storage means for storing the processing content identification information and configuration information of a signal processing circuit corresponding to the processing content identification information;
A signal processing circuit that can reconfigure a circuit that performs signal processing, and that processes the target data using the reconfigured circuit;
Processing content identification information included in the additional information of the acquired data is determined, configuration information corresponding to the determined processing content identification information is acquired from the configuration information storage means, and the signal is generated using the acquired configuration information. Reconfiguration control means for reconfiguring the processing circuit;
After processing the target data by the signal processing circuit after the reconfiguration, processing content identification information corresponding to the configuration information that is the basis of the reconfiguration from the additional information, and processing paired with the processing content identification information Additional information editing means for deleting the result storage address and editing the additional information, and adding the edited additional information to the processed target data;
Transmitting means for transmitting the processed target data to which the edited additional information is added to the deleted processing result storage address;
The signal processing system according to claim 4, further comprising:
(Appendix 6)
When receiving the target data transmitted to the processing result storage address, the signal processing means determines the processing content identification information, and based on the configuration information of the signal processing circuit corresponding to the determined processing content identification information The signal processing system according to appendix 5, wherein the target data processed by the reconfigured signal processing circuit is transmitted to a processing result storage address that is a pair of the processing content identification information.
(Appendix 7)
The control means includes storage means for storing process content identification information for identifying configuration information for configuring a signal processing circuit corresponding to each of one or more signal processes constituting a predetermined process. The signal processing system according to any one of supplementary notes 1 to 6.
(Appendix 8)
The signal processing system according to any one of appendices 1 to 7, wherein the control unit and the signal processing unit are connected via a network.
(Appendix 9)
A signal processing module used in a signal processing system including a control processing module,
Acquisition means for acquiring data transmitted by adding processing content identification information for identifying processing content as target information to target data to be subjected to signal processing;
The processing content identification information added to the acquired data is determined, a signal processing circuit is reconfigured based on configuration information of the signal processing circuit corresponding to the determined processing content identification information, and the reconfigured signal Signal processing means for processing the target data included in the transmitted data by a processing circuit;
A signal processing module comprising:
(Appendix 10)
The signal processing means sequentially discriminates a plurality of processing content identification information included in the additional information, and a signal processing circuit reconfigured based on the configuration information of the signal processing circuit corresponding to the determined processing content identification information. The signal processing according to appendix 9, wherein the processed target data is processed by a signal processing circuit reconfigured based on configuration information of the signal processing circuit corresponding to the processing content identification information determined next. module.
(Appendix 11)
The signal processing module further includes:
Configuration information storage means for storing the processing content identification information and configuration information of a signal processing circuit corresponding to the processing content identification information;
With
The signal processing means includes
A signal processing circuit that can reconfigure a circuit that performs signal processing, and that processes the target data using the reconfigured circuit;
Processing content identification information included in the additional information of the acquired data is sequentially determined, configuration information corresponding to the determined processing content identification information is acquired from the configuration information storage means, and the acquired configuration information is used to Reconfiguration control means for controlling reconfiguration of the signal processing circuit;
With
The signal processing module according to appendix 10, wherein the reconfigured signal processing circuit processes the target data processed by the signal processing circuit before the reconfiguration.
(Appendix 12)
The additional information includes the processing content identification information, a processing result storage address indicating an address of a storage destination of target data after processing by a signal processing circuit reconfigured based on configuration information corresponding to the processing content identification information, and Are configured in pairs,
The signal processing means determines the processing content identification information, and the target data processed by the signal processing circuit reconfigured based on the configuration information of the signal processing circuit corresponding to the determined processing content identification information, The signal processing module according to appendix 9, wherein the signal is transmitted to a processing result storage address which is a pair of the processing content identification information.
(Appendix 13)
The signal processing module further includes:
Configuration information storage means for storing the processing content identification information and configuration information of a signal processing circuit corresponding to the processing content identification information;
With
The signal processing means includes
A signal processing circuit that can reconfigure a circuit that performs signal processing, and that processes the target data using the reconfigured circuit;
Processing content identification information included in the additional information of the acquired data is determined, configuration information corresponding to the determined processing content identification information is acquired from the configuration information storage means, and the signal is generated using the acquired configuration information. Reconfiguration control means for reconfiguring the processing circuit;
After processing the target data by the signal processing circuit after the reconfiguration, processing content identification information corresponding to the configuration information that is the basis of the reconfiguration from the additional information, and processing paired with the processing content identification information Additional information editing means for deleting the result storage address and editing the additional information, and adding the edited additional information to the processed target data;
Transmitting means for transmitting the processed target data to which the edited additional information is added to the deleted processing result storage address;
The signal processing module according to appendix 12, characterized by comprising:
(Appendix 14)
When receiving the target data transmitted to the processing result storage address, the signal processing means determines the processing content identification information, and based on the configuration information of the signal processing circuit corresponding to the determined processing content identification information 14. The signal processing module according to appendix 13, wherein the target data processed by the reconfigured signal processing circuit is transmitted to a processing result storage address that is a pair of the processing content identification information.
(Appendix 15)
By the control module, processing content identification information for identifying processing content is added as additional information to the target data to be subjected to signal processing, and transmitted.
The signal processing module determines the processing content identification information added to the transmitted data, reconfigures the signal processing circuit based on the configuration information of the signal processing circuit corresponding to the determined processing content identification information, An operation method of a signal processing system, wherein the target data included in the transmitted data is processed by the reconfigured signal processing circuit.
(Appendix 16)
The control module adds a plurality of the processing content identification information as additional information to the target data,
The processing content identification information included in the additional information is sequentially determined by the signal processing module, and processed by the signal processing circuit reconfigured based on the configuration information of the signal processing circuit corresponding to the determined processing content identification information. The signal processing system according to claim 15, wherein the target data is processed by a signal processing circuit reconfigured based on configuration information of the signal processing circuit corresponding to the processing content identification information determined next. How it works.
(Appendix 17)
By the control module, the processing content identification information, and a processing result storage address indicating a storage destination address of target data after processing by the signal processing circuit reconfigured based on the configuration information corresponding to the processing content identification information; And the additional information as a pair,
The processing content identification information included in the additional information is sequentially determined by the signal processing module, and processed by the signal processing circuit reconfigured based on the configuration information of the signal processing circuit corresponding to the determined processing content identification information. The signal processing system operating method according to appendix 15, wherein the target data thus transmitted is transmitted to a processing result storage address paired with the processing content identification information.
(Appendix 18)
With the signal processing module,
Determining processing content identification information included in the additional information of the transmitted data;
Reconfiguring the signal processing circuit using configuration information corresponding to the determined processing content identification information;
After processing the target data by the signal processing circuit after the reconfiguration, processing content identification information corresponding to the configuration information that is the basis of the reconfiguration from the additional information, and processing paired with the processing content identification information Delete the result storage address, edit the additional information, add the edited additional information to the target data after the processing,
The operation method of the signal processing system according to appendix 17, wherein the processed target data to which the edited additional information is added is transmitted to the deleted processing result storage address.
(Appendix 19)
When the target data transmitted to the processing result storage address is received by the signal processing module, the processing content identification information is determined, and based on the configuration information of the signal processing circuit corresponding to the determined processing content identification information 19. The signal processing system operating method according to appendix 18, wherein the target data processed by the reconfigured signal processing circuit is transmitted to a processing result storage address which is a pair of the processing content identification information.
(Appendix 20)
An operation method of a signal processing module used in a signal processing system including a control processing module,
Process data identification information for identifying the processing content is added as additional information to the target data subject to signal processing to obtain the transmitted data,
Determining the processing content identification information added to the acquired data;
Reconfiguring the signal processing circuit based on the configuration information of the signal processing circuit corresponding to the determined processing content identification information;
A method of operating a signal processing module, comprising: processing the target data included in the transmitted data by the reconfigured signal processing circuit.

DESCRIPTION OF SYMBOLS 1 Signal processing system 2 CPU module 3 (3-1 to 3-n) Signal processing module 4 (4-1 to 4-n) Signal processing device 5 Data bus 10 Configuration information management table 11 (11-1 to 11-m) ) Processing data 12 Processing result data 20 Transmission data 21 Header information 22 Number of processing content identification information 23 Processing content identification information 24 Processing result storage address 31 Memory 32 Configuration information storage area 33 Processing data storage area 34 Input data transfer control circuit 35 Output data Transfer control circuit 41 Data input processing circuit 42 Signal processing circuit 43 Data output processing circuit 44 Reconfiguration control circuit 45 Configuration information storage area 51 Signal processing system 52 Network

Claims (8)

Control means for adding processing content identification information for identifying processing content as additional information to target data to be subjected to signal processing;
The processing content identification information added to the transmitted data is determined, a signal processing circuit is reconfigured based on configuration information of the signal processing circuit corresponding to the determined processing content identification information, and the reconfigured Signal processing means for processing the target data included in the transmitted data by a signal processing circuit;
A signal processing system comprising: The control means adds a plurality of the processing content identification information as additional information to the target data,
The signal processing means sequentially determines the processing content identification information included in the additional information, and performs processing by the signal processing circuit reconfigured based on the configuration information of the signal processing circuit corresponding to the determined processing content identification information. The signal processing according to claim 1, wherein the processed target data is processed by a signal processing circuit reconfigured based on configuration information of the signal processing circuit corresponding to the processing content identification information determined next. system. The control means includes the processing content identification information, a processing result storage address that represents a storage destination address of target data after processing by a signal processing circuit reconfigured based on configuration information corresponding to the processing content identification information, And the additional information as a pair,
The signal processing means determines the processing content identification information included in the additional information and is processed by a signal processing circuit reconfigured based on the configuration information of the signal processing circuit corresponding to the determined processing content identification information. The signal processing system according to claim 1, wherein the target data is transmitted to a processing result storage address paired with the processing content identification information. A signal processing module used in a signal processing system including a control processing module,
Acquisition means for acquiring data transmitted by adding processing content identification information for identifying processing content as target information to target data to be subjected to signal processing;
The processing content identification information added to the acquired data is determined, a signal processing circuit is reconfigured based on configuration information of the signal processing circuit corresponding to the determined processing content identification information, and the reconfigured signal Signal processing means for processing the target data included in the transmitted data by a processing circuit;
A signal processing module comprising: The signal processing means sequentially discriminates a plurality of processing content identification information included in the additional information, and a signal processing circuit reconfigured based on the configuration information of the signal processing circuit corresponding to the determined processing content identification information. 5. The signal according to claim 4, wherein the processed target data is processed by a signal processing circuit reconfigured based on configuration information of the signal processing circuit corresponding to the processing content identification information determined next. Processing module. The additional information includes the processing content identification information, a processing result storage address indicating an address of a storage destination of target data after processing by a signal processing circuit reconfigured based on configuration information corresponding to the processing content identification information, and Are configured in pairs,
The signal processing means determines the processing content identification information, and the target data processed by the signal processing circuit reconfigured based on the configuration information of the signal processing circuit corresponding to the determined processing content identification information, The signal processing module according to claim 4, wherein the signal is transmitted to a processing result storage address that is a pair of the processing content identification information. By the control module, processing content identification information for identifying processing content is added as additional information to the target data to be subjected to signal processing, and transmitted.
The signal processing module determines the processing content identification information added to the transmitted data, reconfigures the signal processing circuit based on the configuration information of the signal processing circuit corresponding to the determined processing content identification information, An operation method of a signal processing system, wherein the target data included in the transmitted data is processed by the reconfigured signal processing circuit. An operation method of a signal processing module used in a signal processing system including a control processing module,
Process data identification information for identifying the processing content is added as additional information to the target data subject to signal processing to obtain the transmitted data,
Determining the processing content identification information added to the acquired data;
Reconfiguring the signal processing circuit based on the configuration information of the signal processing circuit corresponding to the determined processing content identification information;
A method of operating a signal processing module, comprising: processing the target data included in the transmitted data by the reconfigured signal processing circuit.

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