JP2010286372A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To detect a current flowing through a power N type MOSFET and conventionally detected from a voltage drop in an external resistor by a hall voltage V<SB>H</SB>generated in a hall element. <P>SOLUTION: In a semiconductor device, an insulating film 7a is disposed directly below a source wiring layer 8 wired toward a ground line, and has a thickness of several tens of nanometers. A magnetic flux density B is generated in an area directly below the source wiring layer 8 or a N type layer 1 on both side faces of the source wiring layer 8, and increased by a source current I. The high hall voltage V<SB>H</SB>is generated by disposing the hall element H in the area in which the high magnetic flux density B is generated even if the source current I of the power N type MOSFET is several amperes. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device. In particular, the present invention relates to a configuration in which a current flowing in a wiring layer of a power device is detected by a Hall element formed in the same semiconductor substrate.

A magnetic field based on Ampere's law is generated around the current flowing in the wiring. A current detection device including a Hall element that detects a magnetic field, generates a Hall voltage proportional to the magnetic flux density, and relatively detects a current flowing through the wiring is disclosed in the following prior art documents. . In either case, the current flowing outside the Hall element is detected from the magnetic flux density B generated by the current. Assuming that the current flowing through the wiring is a linear current, the Hall voltage V _H generated in the Hall element can be expressed as follows.

When a semiconductor substrate through which a hole current flows has a width b, a thickness t, an electron concentration n, an electron charge q, a magnetic flux density B generated by a linear current, and a hole current I _H that flows through the Hall element, a Hall voltage V _H = BI _H / qnt. That is, by measuring V _H , an unknown value of B is found. The relationship between the magnetic flux density B and the measured current I is B∝μI / r. Here, μ is the magnetic permeability of the region surrounding the current, and r is the distance between the current I and the position where the magnetic flux density B is measured. Usually, a Hall element is arranged near the wiring through which a current flows, r is made as small as possible, and a Hall element is arranged in a high magnetic flux density B so that a high Hall voltage V _H can be obtained.

  In this case, even if r is reduced, the Hall element substrate and the package are thick, so that the wiring and the Hall element cannot be brought closer to each other. From the relationship of B∝μI / r, the distance r between the wiring and the Hall element increases in inverse proportion to the magnetic flux density B, and the magnetic flux density B inside the Hall element cannot be sufficiently increased. In view of this, a contrivance has been made such that a magnetic flux collecting plate made of ferrite or the like is attached immediately above the Hall element to collect magnetic flux to improve the magnetic flux density B.

JP2003-130895 JP 2003-262650 A JP 2008-267832 A

  As described above, a relatively large current flowing in a specific wiring can be detected by replacing the Hall voltage generated in the Hall element by arranging the Hall element adjacent to the vicinity thereof. However, when a current of about several A of power devices formed in an integrated circuit or the like is detected and fed back to the input terminal of the power device to make the current of the power device constant, the current shown in FIG. As described above, an external resistor is simply provided in series with the wiring layer of the power device, and feedback is applied to the gate input terminal by a voltage generated at both ends of the resistor.

  In recent years, small portable devices such as mobile phones are increasingly required to be lighter, thinner, and smaller, and it is essential to incorporate external components and the like into a semiconductor substrate. If the resistor is incorporated in the semiconductor substrate, power is consumed in the resistor portion and power loss due to heat generation occurs. In order to minimize the power loss, it is necessary to make the resistance low, but in this case, the area occupied by the resistance becomes large, and it is difficult to accurately form a low resistance, so it is difficult to accurately detect the current. Occurs. There is also a problem that the power supply voltage cannot be used effectively due to the voltage drop at the resistor.

As shown in FIG. 1 (B), drawn out of the package, the lead frame for connecting to the wiring layer of the power device, to place the Hall element in proximity, the Hall current I _H from the constant current source IDD A method of measuring the Hall voltage V _H generated by the electromagnetic force f between the current I flowing and the magnetic flux density B generated from the current I flowing through the wiring layer of the power device is also conceivable. At most, it is about several A, and it is difficult to generate a sufficient Hall voltage V _H. In addition, such a method goes against the flow of thinness and miniaturization.

However, as described above, the magnetic flux density B generated around the source current I increases as the distance r between the measurement position of the magnetic flux density B and the source current I decreases. By utilizing this property, a higher magnetic flux density B can be generated by forming the Hall element H together with the power device in the N-type layer 1 near the source wiring layer 8. As a result, a high Hall voltage V _H can be obtained, and the source current I can be substituted and detected. Suitable for light, thin and small flow.

  Therefore, it becomes a problem to develop a Hall element H that can easily detect the current I flowing through the power device without consuming excessive power.

  The semiconductor device according to the present invention is insulated on a Hall element having a current terminal and a voltage terminal formed on a surface of a first conductivity type semiconductor layer and on the Hall element or on the semiconductor layer adjacent to the Hall element. It is composed of a wiring layer of a power device formed through a film, and the Hall element generates a Hall voltage by a magnetic field generated from a current flowing through the wiring layer.

  In the semiconductor device of the present invention, the Hall element is formed in a semiconductor layer on a side surface of the wiring layer, and a Hall current flowing through the Hall element flows in a direction perpendicular to the side surface of the wiring layer.

  In the semiconductor device of the present invention, the Hall current flowing in a direction perpendicular to the wiring layer is formed on the opposite side of the wiring layer from the current input end of the Hall element formed on one side of the wiring layer. Further, the current flows continuously to the current output terminal of the Hall element.

  Furthermore, the semiconductor device of the present invention is characterized in that the Hall element is formed on a side surface of the wiring layer, and a Hall current flowing through the Hall element flows in a direction parallel to the wiring layer.

  In the semiconductor device of the present invention, the Hall current flowing in a direction parallel to the wiring layer is formed on the opposite side of the wiring layer from the current input end of the Hall element formed on one side of the wiring layer. Further, the current flows continuously to the current output terminal of the Hall element.

  The semiconductor device of the present invention is characterized in that the current terminal is of a second conductivity type, and a region sandwiched between the two current terminals is formed of the second conductivity type.

  Further, in the semiconductor device of the present invention, the Hall current flows directly under the wiring layer in parallel with the wiring layer, and the one voltage terminal formed of the second conductivity type immediately under the wiring layer; One voltage terminal connected to a lead electrode of the first conductivity type connected to the buried layer of the first conductivity type in the semiconductor substrate is provided.

  In the semiconductor device of the present invention, one of the current terminals is connected to a first conductivity type lead electrode connected to a first conductivity type buried layer formed in the semiconductor substrate, and the current terminal The hole current flowing in from the current flows out to the one current terminal immediately below the wiring layer.

  Furthermore, the semiconductor device of the present invention is characterized in that the input of the power device is controlled by the Hall voltage, and the current flowing through the power device is made constant.

  According to the present invention, it is possible to detect a current flowing through a wiring layer of a power device without causing a disadvantage such as an increase in manufacturing process, an increase in heat generation in a semiconductor layer, and an increase in chip size. it can. Moreover, it is possible to apply appropriate feedback to the input terminal of the power device based on the detection result, and the current flowing through the power device can be made constant.

It is a circuit diagram which shows the measuring method of the source current of power N type MOSFET. It is a figure which shows the area | region which forms the Hall element near a source wiring layer in order to measure the source current of power N type MOSFET. It is a figure which shows the direction of the magnetic force which the direction of the magnetic flux generated from a source current, the direction of Hall current, and the electromagnetic force which a Hall current receives. It is a figure which shows the direction of the magnetic force which the direction of the magnetic flux generated from a source current, the direction of Hall current, and the electromagnetic force which a Hall current receives. It is a figure which shows arrangement | positioning of the Hall element of the source wiring vicinity in the 1st Embodiment of this invention. It is a figure which shows the mode of generation | occurrence | production of the Hall voltage in the 1st Embodiment of this invention. It is a figure which shows the mode of generation | occurrence | production of the Hall voltage in the 1st Embodiment of this invention. It is a figure which shows the mode of generation | occurrence | production of the Hall voltage in the 2nd Embodiment of this invention. It is a figure which shows the mode of generation | occurrence | production of the Hall voltage in the 3rd Embodiment of this invention. It is a figure which shows the mode of generation | occurrence | production of the Hall voltage in the 4th Embodiment of this invention.

The current I flowing through the power N-type MOSFET is at most several A as described above. Assuming that the current I is a linear current of 1 A, a clockwise magnetic flux density B generated in the direction in which the current I flows, a magnetic permeability μ _r of the silicon semiconductor forming the Hall element H _{, a} vacuum magnetic permeability μ ₀ , When the distance between the measurement positions of the current I and the magnetic flux density B is r, the relationship is B = μ _r μ ₀ I / 2πr. Therefore, the magnetic flux density is B = 0.4 gauss when r = 10 μm, B = 4 gauss when r = 1 μm, B = 40 gauss when r = 100 nm, and B = 400 gauss when r = 10 nm. Is obtained.

Even if the Hall element is brought close to the lead frame through which the source current I flows, the magnetic flux density B that is difficult to be brought close to 10 μm or less is weak as 0.4 gauss or less in consideration of the thickness of the package. I must. The flux concentrator such as ferrite enhances the focused flux density B of sticking to the magnetic field lines immediately above the Hall elements, but means to increase the Hall voltage V _H is used, still there is a possibility of insufficient. Moreover, even if such a ferrite or the like is attached and the Hall voltage V _H can be increased, it goes against the trend of making the portable device lighter and thinner.

However, as described above, the Hall voltage V _H = BI _H / qnt can be expressed, and the relationship between the magnetic flux density B and the measured current I can be expressed by B∝μI / r. By reducing the distance r of the position where the current I _H flows to the limit, as described above, even when the current I to be measured is only a few A, a large magnetic flux density B is generated and a large Hall voltage V _H can be obtained. It becomes possible. Extreme case the magnetic flux density by bringing the r to around zero if B, can be brought close to the Hall voltage V _H to infinity.

For this purpose, as described below, if the Hall element H is formed in the semiconductor layer in the vicinity immediately below the wiring layer through which the source current of the power N-type MOSFET flows, r can be minimized. In FIG. 2A and FIG. 2B, the Hall element formation region 10 is indicated by a circle. FIG. 2A shows a plan view of a power N-type MOSFET formation region together with a source wiring layer 8 directed to a ground line (not shown). FIG. 2B is a cross-sectional view taken along line XX in FIG. Since the Hall voltage _VH is not related to the Hall element size (excluding the thickness t) as expressed by the above formula, it can be easily formed in a small region near the source wiring layer. When a sufficiently large Hall voltage V _H cannot be obtained, an amplifier circuit can be formed in the semiconductor substrate, and the generated Hall voltage V _H can be amplified and increased.

However patterning during machining accuracy problem, the problem of heat generation due to the hole current I _H, the problems such as the dielectric breakdown due to the Hall voltage V _H, smallest dimension is naturally limited. Through a predetermined process in the N-type semiconductor layer 1, a P + type source layer 2, a P− type drift layer 3b, a P + type drain layer 3a, an N + type back gate contact layer 4, a gate insulating film 5, a gate electrode 6, and a source A wiring layer 8 and a drain wiring layer 9 are formed. A source current I flows from the P + type source layer 2 to the earth line (not shown) via the source wiring layer 8.

3A, 3B, 4A, and 4B, the direction of the magnetic flux density B generated from the source current I in the cross section taken along the line XX of FIG. indicating the direction of force f applied from the direction and the magnetic field of the Hall current I _H electron of N-type semiconductor layer 1 which constitutes the hole current I _H. When the direction of the magnetic flux density B and the Hall current I _H is orthogonal, the electrons move to the flow in the opposite direction of the current is subjected to maximum electromagnetic force f. The direction of the magnetic flux density B is generated from Ampere's law, for example, around the source current I flowing from the back side to the front side, as shown in FIGS. 3 and 4, counterclockwise on the paper surface. As shown in FIGS. 3 and 4, the magnetic flux density B in the N-type semiconductor layer 1 is from the top to the bottom on the left of the source wiring layer 8 and from the bottom to the top on the right. Directly below the source wiring layer 8, it faces right.

In this case, the case where the magnetic flux density B and the Hall current _{I H} are orthogonal FIG. 3 (A), the FIG. 3 (B), the FIG. 4 (A), the conceivable 4 types in FIG. 4 (B). In FIG. 3A, the magnetic flux density B in the vertical direction of the paper and the hole current I _H from the left to the right of the paper are orthogonal to each other. Figure 3 (B) the hole current I _H toward the back from the magnetic flux density B and the paper sheet toward the up and down direction are orthogonal. In FIG. 4A, the magnetic flux density B from the left to the right of the paper is perpendicular to the hole current I _H from the front to the back of the paper. In FIG. 4B, the magnetic flux density B from the left to the right of the paper and the bottom from the top of the paper. Hall current I _H towards the perpendicular.

  As a result, due to the Hall effect, electrons receive an electromagnetic force f from the front side to the back side of the drawing on the left side of the source wiring layer 8 in FIG. In FIG. 3B, the electrons receive electromagnetic force f facing left on the left side of the source wiring layer 8 and facing right on the right side. Further, in FIG. 4A, the electrons receive an electromagnetic force f from the top to the bottom of the page, and in FIG. 4B, the electrons are directed from the front to the back of the page.

By receiving the electromagnetic force f, electrons having a negative charge are accumulated at the destination of the movement of electrons, and positively charged donor ions which are shells of electrons are generated on the opposite side. A hole electric field is generated by these electrons and donor ions, a force opposite to the electromagnetic force f due to the magnetic flux density acts on the electrons, and a hole current I _H flows in a state where the electromagnetic force f and the force due to the electric field are balanced.

These four specific embodiments will now be described with reference to the drawings.
[First Embodiment]
The first embodiment will be described based on FIGS. 5 and 6. The first embodiment corresponds to FIG. 3A, and as shown in FIG. 3A, the first embodiment is perpendicular to the magnetic flux density B formed perpendicular to the side surface of the source wiring layer 8. The hole current _IH is flowing from the left side of the drawing to the right side. FIG. 5 shows an example of the configuration of the Hall element. 5A is a plan view of the Hall element portion, FIG. 5B is a diagram showing a cross-sectional structure taken along line XX, and FIG. 5C is a cross-sectional view taken along line YY. It is.

  In FIG. 5A, the Hall elements H1 and H2 are formed on both sides of the source wiring layer 8, but may be formed only on one side when there is no empty area. When formed on both sides of the source wiring layer 8, an interlayer insulating film 15 is formed on the source wiring layer 8 as shown in FIGS. 5A and 5C, and the Hall voltage is formed so as to straddle it. By forming the electrode 11c, the Hall elements H1 and H2 formed on both sides of the source wiring layer 8 can be connected in series. In order to connect the Hall elements H1 and H2 in series, the Hall voltage contact layer 14c and the Hall voltage contact layer 14d shown in FIG. 4A may be formed integrally with the N-type layer 1.

As shown in FIG. _6A , the hole current I _H passes from the hole current electrode 10a to the hole current contact layer 12b through the hole current contact layer 12a, through the hole current path 13, and finally to the hole current contact layer 12b. It flows to the electrode 10b. 6A, the Hall voltage V _H is generated between the Hall voltage contact layer 14a and the Hall voltage contact layer 14c in the Hall element H1 on the left side of the source wiring layer 8, and the Hall element H2 on the right side. Then, it occurs between the Hall voltage contact layer 14d and the Hall voltage contact layer 14b.

The hole current path 13 shown immediately below the source wiring layer 8 is a low resistance layer made of an N + type semiconductor layer. Hole current path 13, on the one hand forms the output terminal of the Hall current I _H of the Hall elements H1, it plays the role of input terminals of the Hall current I _H of the Hall element H2 in the other.

Now, how the Hall voltage V _H is generated in the first embodiment will be described with reference to FIGS. 6 (A) and 6 (B). FIG. 6A is a plan view of a semiconductor substrate on which Hall elements and the like are formed. FIG. 6B is a diagram illustrating a cross-sectional view taken along line XX in FIG. In FIG. 6A, the source current I flows through the source wiring layer 8 from the bottom to the top of the page. In FIG. 6B, it flows from the front to the back of the page. In addition, the current flowing from the constant current source IDD into the Hall element, that is, the Hall current I _H flows from the Hall current electrode 10a to the Hall current contact layer 12a, passes through the Hall current path 13, and then passes through the Hall current contact layer 12b and the Hall current electrode 10b. On the other hand, in terms of paper, it flows from the left to the right in FIG.

From the direction in which the source current 8 flows, a clockwise magnetic flux density B surrounding the source wiring layer 8 is generated according to Ampere's law, as shown in FIG. In this case, the magnetic flux density B in the N-type semiconductor layer 1 can be increased by making the insulating film 7a below the source wiring layer 8 as thin as possible. As shown in FIG. 6A, the magnetic flux density B is directed from the back of the drawing to the front on the left side of the source wiring layer 8, and from the front to the back of the drawing on the right side of the source wiring layer 8. In FIG. 6B, the left side of the source wiring layer 8 is from the bottom to the top and the left side is from the top to the bottom. When the hole current I _H flows through the magnetic field having the magnetic flux density B, the charge constituting the hole current I _H receives the electromagnetic force f in the direction perpendicular to the current and the magnetic field according to Fleming's left-hand rule. As shown in FIG. 6 (A), they are integrated on the side surface of the current path.

A semiconductor substrate of the first embodiment charges constituting the N-type semiconductor layer 1 so Hall current I _H becomes electron a negative charge, flows in a direction opposite to the direction of flow of the hole current I _H. As shown in FIG. 6 (A), the electrons that have received the electromagnetic force f travel from the top to the bottom of the paper in the Hall element H1 on the left side of the source wiring layer 8, and from the bottom to the top in the Hall element H2 on the right side. Receive f. 6B, the left side of the source wiring layer 8 receives the electromagnetic force f from the back of the paper to the front and the right side from the front to the back. As a result, as shown in FIG. 6A, in the Hall element H1 on the left side of the source wiring layer 8, electrons are accumulated on the Hall voltage contact layer 14a side and positively on the opposite Hall voltage contact layer 14c side. Charged donor ions appear.

In the Hall element H2 on the right side of the source wiring layer 8, contrary to the left side, electrons are accumulated on the Hall voltage contact layer 14d side, and positively charged donor ions appear on the opposite Hall voltage contact layer 14b side. As a result, a hall voltage _VH is generated in each of the hall elements H1 and H2. Since both Hall elements H1, H2 can be connected in series with the Hall voltage electrode 11c, the Hall voltage electrodes 11b positive, the Hall voltage electrodes 11a and negative electrode, to obtain twice the Hall voltage V _H of a single Hall element Can do. When the Hall element H1 is formed only on one side of the source wiring layer 8 due to space or the like, naturally, the Hall voltage _{VH corresponding} to the generation of the Hall element H1, the Hall voltage electrode 11c as the positive electrode, and the Hall voltage electrode 11a. Can be obtained as a negative electrode.

As shown in FIG. 7, the path of the hole current I _H flowing in the N-type layer 1 from the left of the source wiring layer 8 shown in FIG. 6 (A) to the right to form a plurality, on both sides of the source wiring layer 8, corresponding Then, if each of the plurality of Hall elements is formed in series, the Hall voltage V _H generated by the plurality of Hall elements H1 to H4 connected in series is added between the Hall voltage electrode 11a and the Hall voltage electrode 11b. Further, a higher Hall voltage V _H can be obtained. A hole current I _H can be secured, and an effective means is provided if there is a region where a plurality of Hall elements H can be formed. Of course, if there is a place restriction or process restriction, one or a plurality of Hall elements H may be formed on one side of the source wiring layer 8.

Further, the hole current contact layer 12a, 12b is formed from N + -type layer, the current path of hole current I _H between the two hole current contact layer 12a, 12b is composed of a low concentration of N-type layer 1. Hall voltage V _H, as represented by the above equation, is inversely proportional to the impurity concentration of the N-type layer 1 is a current path of the Hall current I _H. Therefore, in order to realize a high Hall voltage V _H , it is conceivable that the impurity concentration in that portion is compensated and reduced by ion-implanting a reverse conductivity type impurity. However, in this case, the hole current I _H diverges and flows to the N-type layer 1 having a higher concentration, which is not implanted with ions, and it is difficult to secure a sufficient hole voltage V _H.

Another problem is that the hole current I _H flowing from the hole current contact layer 12a to the hole current contact layer 12b flows not only in the direction perpendicular to each of the hole current contact layer 12a and the hole current contact layer 12b, but also around it. Also flows. Furthermore, it also flows in the depth direction of the N-type layer 1. Contribution to the Hall voltage V _H of the current component flowing through these lateral and depth directions is low. Therefore, hole current electrodes 12a, 12b were formed in the P + -type layer, both hole current electrodes 12a, by the current path of the Hall current I _H sandwiched 12b to the low concentration P-type layer, also, the hole current By restricting the current path of I _H within the P-type layer and reducing useless current components, a larger Hall voltage V _H can be generated.

  Next, a method for manufacturing the Hall element according to the first embodiment will be described. The cross-sectional views are shown in FIGS. 5 (B) and 5 (C). From this, it can be seen that the N + type hole current contact layer 10a of the Hall element can be formed simultaneously with the formation of the N + type contact layer 4 such as the power N type MOSFET shown in FIG. The insulating layer 7, the source wiring layer 8, and the like, and the interlayer insulating film 15 are the same as the constituent elements such as the power N-type MOSFET. Since the insulating film 7a immediately below the source wiring layer 8 is preferably thin enough to increase the magnetic flux density due to the source current I, it is formed simultaneously with the power N-type MOSFET or the gate oxide film 5 of a normal MOSFET. Things are desirable.

As a guideline, a magnetic flux density B of 40 gauss is obtained when the source current I is about 1 A and the thickness of the insulating film 7a immediately below the source wiring layer 8 is 100 nm as approximated by a linear current as described above. things can, was able to generate a Hall voltage V _H of a few mV. Since the potential of the source wiring layer 8 is directly connected to the earth line and becomes the ground potential, the film thickness of the insulating film 7a can be further reduced and can be about several tens of nm or less. In this case, a higher Hall voltage _VH can be obtained.

  Further, in FIG. 5 and FIG. 6A, the hole voltage contact layers 14a, 14b, 14c, and 14d are shown with their ends separated from the side surface of the source wiring layer 8 for easy understanding. It is desirable to form at a position overlapping the side surface of the layer 8. This is because the closer to the side surface of the source wiring layer 8, the stronger the magnetic flux density B penetrating from the surface of the N-type semiconductor layer 1 shown in FIG.

Further, in order to increase the hole voltage V _H by reducing the impurity concentration of the current path of the hole current I _H , the hole current electrodes 12a and 12b and the region sandwiched between them are respectively formed as a P + type layer and a P type layer. As described above, the process for forming these also does not need to be specially prepared, and is formed simultaneously with the P + type source layer formation of the P type MOSFET, or simultaneously with the ion implantation process such as boron for adjusting the threshold value. I can do it.

  In order to form the Hall element H1 and the like in this manner, in principle, it is not necessary to add a new process, and it is only necessary to modify a part of the photomask pattern at the time of manufacturing a normal MOSFET or the like. In addition, since the Hall element formation region 10 is sufficiently small in the vicinity of the source wiring layer 8, it is not necessary to increase the overall chip size by forming the Hall element H1 and the like.

[Second Embodiment]
Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 8A is a plan view showing the arrangement of the Hall elements H 1 and H 2 and the source wiring layer 8. FIG. 8B is a cross-sectional view taken along line XX in FIG. The second embodiment corresponds to the above-described FIG. 3B, and as shown in FIG. 8, the magnetic flux density penetrating the side surface of the source wiring layer 8 from the surface of the N-type semiconductor layer 1 to the inside thereof. and B, is to utilize an electromagnetic force f between the hole current I _H crossing perpendicularly it horizontally. The Hall elements H1 and H2 are formed on both side surfaces of the source wiring layer 8 as in the first embodiment.

Also in this case, the Hall element H1 may be formed only on one side of the source wiring layer 8 as in the first embodiment. Different from the first embodiment is the direction of flow of the hole current I _H. Hall elements H1 to the left of the source wiring layer 8, hole current _{I H} is, flows from the hole current electrode 10a, through the hole current contact layer 12a, flows from the Hall current contact layer 12c in the hole current electrode 10c. That is, that the source current 8 and the hole current I _H flows in parallel is different from the first embodiment.

Further, the magnetic flux density B generated from the source current I is directed from the front side to the back side on the left side of the source wiring layer 8 when the source current I flows from the top to the bottom as shown in FIG. . As a result, the electrons constituting the hole current I _H receive a left electromagnetic force f, and the electrons are focused on the left hole voltage contact layer 14a side shown in FIGS. Positively-charged donor ions appear on the side of the hole voltage contact layer 14c immediately below the side surface. As a result, the Hall voltage V _H is generated between the Hall voltage contact layer 14a and the Hall voltage contact layer 14c, it adopts a configuration for detecting the Hall voltage V _H with Hall voltage electrode 11a and the Hall voltage electrode 11c.

8, further, to form a Hall element H2 to the right of the source wiring layer 8 to ensure high Hall voltage V _H. With respect to the left Hall element H1, all of the magnetic flux density B, the Hall current I _H , and the electromagnetic force f received by the electrons are directed in opposite directions. Accordingly, positive donor ions appear on the Hall voltage contact layer 14b side, and electrons collect on the Hall voltage contact layer 14c side. Hall current I _H flowing through the Hall elements H1 on the left flows through the hole current contact layer 12c formed extending to the right from the left side of the source wiring layer 8 to reach the right side of the hole current contact layer 12c, From there, the right Hall element H2 flows to the Hall current contact layer 12b.

In FIG. 8A, the Hall current I _H flows from the left Hall element H1 to the right Hall element H2 via the Hall current contact layer 12c, but is not limited thereto. It may flow through a wiring layer formed on the wiring layer 8 via an interlayer insulating film. In this case, the Hall voltage V _H generated by the two Hall elements H1, H2, as shown in FIG. 8 (A), are connected in series with the Hall voltage electrode 11c, as the sum of each of the Hall voltage V _H, Hall The voltage electrode 11b is a positive electrode and the Hall voltage electrode 11a is a negative electrode, and is generated between the Hall voltage electrodes 11b and 11a. When forming the Hall elements H1 only one side of the source wiring layer 8, using the Hall voltage V _H generated between the Hall voltage electrodes 11a and the Hall voltage electrode 11c.

Also in the second embodiment, although the illustrated explanation is omitted, as shown in FIG. 7 for the first embodiment, it is possible to arrange a plurality of Hall elements on both sides of the source wiring layer 8. There, the Hall voltage V _H generated in each by further connected in series, can generate a higher Hall voltage V _H. In this case, as compared with the first embodiment, the hall current I _H is characterized by a single current path.

  The manufacture of the Hall element of the second embodiment is the same as that of the first Hall element. In principle, the Hall element can be manufactured at the same time as a normal MOSFET manufacturing process only by correcting the photomask pattern.

[Third Embodiment]
The third embodiment will be described with reference to FIGS. 9A and 9B, which is an embodiment corresponding to FIG. 4A. FIG. 9A is a plan view showing an example of the configuration of the Hall element H3 in the third embodiment. The hole current contact layers 12 a and 12 b and the hole voltage contact layers 14 b and 14 e extend to the N-type layer 1 immediately below the source wiring layer 8. The Hall voltage electrodes 11a and 11b and the Hall current electrodes 10a and 10b are connected to each. Referring to FIG. 9B, which is a cross-sectional view taken along line XX in FIG. 9A, the hole voltage contact layer 14e is formed of a P + type layer, and the hole voltage contact layer 14b is formed according to another embodiment. As well as an N + type layer.

In the third embodiment, the hole current I _H flows from the hole current electrode 10a as shown in FIG. 9B, passes through the hole current contact layer 12a, and directly below the source wiring layer 8 to the hole current contact layer 12a. 9B flows horizontally from the left side to the right side in FIG. In this case, most of the hole current I _H when the Hall voltage contact layer 14e is that it N + -type layer will flow resistance low Hall voltage contact layer 14e made of N + -type layer, the Hall voltage V is inversely proportional to the concentration of the current path _H becomes low. Therefore, the hole voltage contact layer 14e is formed of a P + type layer to prevent electrons from flowing into the high concentration hole voltage contact layer 14e.

In the third embodiment, as shown in FIGS. 9B and 9C, the source current I flowing through the source wiring layer 8 causes the semiconductor layer immediately below the source wiring layer 8 to be connected to the semiconductor layer shown in FIG. ) In the direction from the back of the paper to the front, and in FIG. 9C, which is a cross-sectional view of the YY line in FIG. 9A, the magnetic flux density in the direction from the left to the right of the paper. B is generated. In this case, the electrons constituting the Hall current I _H receive the electromagnetic force f that goes downward from the top of the page. As a result, in FIGS. 9B and 9C, negatively charged electrons are terminated on the N + type buried layer 17 side formed on the P type semiconductor substrate 0, and a hole voltage contact made of the P + type layer is formed. Donor ions composed of positive charges appear on the layer 14e side.

That is, the hole voltage V _H is generated between the hole voltage contact layer 14 e of the N-type layer 1 and the N + type buried layer 17. There is no problem because the potential of the Hall voltage contact layer 14e is extracted to the outside by the Hall voltage electrode 11a, but the potential on the N + type buried layer 17 side is inside the N-type layer 1, and means for extracting to the outside is required. . Therefore, an N + C contact layer 16 is formed as a contact layer with the N + buried layer 17, and the potential on the N + type buried layer 17 side is drawn out to the hole voltage electrode 11b by connecting the N + C contact layer 16 and the hole voltage contact layer 14b. .

By adopting such a configuration, it is possible to obtain a Hall voltage V _H having the positive electrode on the Hall voltage electrode 11a side and the negative electrode on the Hall voltage electrode 11b side. Such a configuration is possible when the N-type layer 1 is thin. When the bipolar IC manufacturing process is adopted, the Hall element according to the present embodiment can be manufactured simultaneously with the existing process work without adding a new process. However, since the N + C contact layer 16 can be made shallow by forming the N + buried layer 17 as shallow as possible, the N + buried layer 17 is formed at a shallow position by ion implantation from the surface of the N-type layer 1. Is desirable.

[Fourth Embodiment]
Next, a fourth embodiment will be described with reference to FIGS. 10 (A) and 10 (B). This embodiment corresponds to the embodiment of FIG. FIG. 10A is a plan view showing the arrangement of the Hall element H4 and the source wiring layer 8. FIG. FIG. 10B is a sectional view taken along line XX. A hole current I _H is caused to flow from the hole current electrodes 10 a on both sides of the source wiring layer 8. Hall current _{I H} flowing from the hole current electrode 10a flows into the low resistance N + C contact layer 16 shown as Figure 10 (B) a hole current contact layer 12a. Most of the hole current I _H flowing into the N + C contact layer 16 flows into the N + buried layer 17 which is a low resistance layer, and from there through the N-type layer 1, as shown in FIG. It flows out to the layer 12b.

With such a configuration, the hole current I _H is generated immediately below the source wiring layer 8 from the N + buried layer 17 toward the hole current contact layer 12 b formed immediately below the source wiring layer 8. It flows with a component that crosses the magnetic flux density B from the left to the right in FIG. Electrons having negative charges constituting the hole current I _H from the magnetic flux density B, receiving the electromagnetic force f from top to bottom in terms of the FIG. 10 (A), the focusing into the hole electrode contact layer 14b side. On the opposite side of the hole electrode contact layer 14a, donor ions which are positive charges are generated. As a result, a Hall voltage _VH is generated with the Hall voltage electrode 11a side as the positive electrode and the Hall voltage electrode 11b side as the negative electrode.

In this case, a part of the hole current I _H flowing from the hole current contact layer 12a to N + C contact layer 16, as shown in FIG. 10 (B), directly laterally from the N + C contact layer 16, the source wiring layer 8 It flows toward the hole current contact layer 12b formed immediately below. The hole current I _H component, it is necessary to reduce does not occur effectively Hall voltage V _H. For this purpose, it is necessary to keep the hole current contact layer 12a and the N + C contact layer 16 as far as possible from the hole current contact layer 12b. Further, the N + buried layer 17 is formed at a position as shallow as possible by ion implantation, the distance between the hole current contact layer 12b and the N + buried layer 17 is reduced, and the hole current I _H passes from the N + C contact layer 16 via the N + buried layer 17. Therefore, it is desirable that the hole current contact layer 12b easily flows.

  Although not shown, the Hall elements H may be formed on both sides of the source wiring layer 8 in the fourth embodiment as in the first and second embodiments. In this case, the hole current contact layer 12b immediately below the source wiring layer 8 is divided into two and formed in the lower regions on both sides of the source wiring layer 8, and the hole voltage contact layers 14a and 14b and the hole voltage electrodes 11a and 11b are also formed. Each of them is divided into two, and one pair is formed on both sides of the source wiring layer 8. Needless to say, when there is no space, it can be formed only on one side of the source wiring layer 8.

  In principle, the Hall element H4 according to the fourth embodiment can be formed at the same time when a manufacturing process of a normal integrated circuit or the like is performed.

For each embodiment, a suitable one for the manufacturing process of each integrated circuit or the like may be selected. Generally speaking, the magnetic flux density B generated by the source current I and the hall current _IH are set to the highest possible magnetic flux. if configured as many hole current I _H density B crosses the vertical, can be obtained a high Hall voltage V _H. From this point of view, it seems that the first and fourth embodiments satisfy this condition to some extent. In terms of the first embodiment, because the majority of the hole current I _H crosses the vertical high magnetic flux density B on the sides of the source wiring layer 8.

In terms of the fourth embodiment is the magnetic flux density B directly under the source wiring layer 8, from bottom to top the majority of the hole current I _H, since flows with components across the vertical magnetic flux density B. In contrast, in the second embodiment, as shown in FIG. 8A, the hole current I _H flowing near the high magnetic flux density B on the side surface of the source wiring layer 8 is a part of the whole, and the source wiring layer Since many hole currents I _H flow through the portion where the magnetic flux density B decreases as the distance from 8 increases, it is disadvantageous for generating the Hall voltage V _H. In this case, as described above, this can be dealt with by forming a plurality of Hall elements on both sides of the source wiring layer 8 and adding and increasing the Hall voltage V _H generated in each Hall element.

  In the present embodiment, the power N-type MOSFET has been described. However, the present invention is not limited to this, and it goes without saying that the present invention can be applied not only to the power P-type MOSFET but also to the emitter current detection of a bipolar power transistor. .

1 N-type layer P + 2 type source layer 3a P + type drain layer
3b P− type drift layer 4 N + type back gate contact layer 5 Insulating film
6 Gate electrode 7 Insulating film 7a Insulating film 8 Source wiring layer
8a Source wiring layer 9 Drain wiring layer 10 Hall element formation region
I source current I _H Hall current B magnetic flux density f electromagnetic force
H, H1-H4 Hall element 10a, 10b Hall current electrode
11a, 11b, Hall voltage electrode 12a, 12b Hall current contact layer
13 Hall current path
14a, 14b, 14c, 14d, 14e Hall voltage contact layer
15 Interlayer insulation film 16 N + C contact layer 17 N + buried layer

Claims (9)

A Hall element having a current terminal and a voltage terminal formed on the surface of the first conductivity type semiconductor layer;
A wiring layer of a power device formed through an insulating film on the Hall element or on the semiconductor layer adjacent to the Hall element;
The Hall element generates a Hall voltage by a magnetic field generated from a current flowing through the wiring layer. 2. The semiconductor according to claim 1, wherein the Hall element is formed in the semiconductor layer on a side surface of the wiring layer, and a Hall current flowing through the Hall element flows in a direction perpendicular to the side surface of the wiring layer. apparatus. The Hall current flowing in the direction perpendicular to the wiring layer is from the current input end of the Hall element formed on one side of the wiring layer to the current output end of the Hall element formed on the opposite side of the wiring layer. The semiconductor device according to claim 2, wherein the semiconductor device flows continuously. The semiconductor device according to claim 1, wherein the Hall element is formed in the semiconductor layer on a side surface of the wiring layer, and a Hall current flowing through the Hall element flows in a direction parallel to the wiring layer. The Hall current flowing in a direction parallel to the wiring layer is from the current input end of the Hall element formed on one side of the wiring layer to the current output end of the Hall element formed on the opposite side of the wiring layer. The semiconductor device according to claim 3, wherein the semiconductor device flows continuously. 6. The semiconductor device according to claim 1, wherein the current terminal is of a second conductivity type, and a region sandwiched between the two current terminals is formed of the second conductivity type. The Hall current flows directly below the wiring layer in parallel with the wiring layer, the one voltage terminal formed in the second conductivity type immediately below the wiring layer, and the first conductivity type in the semiconductor substrate 2. The semiconductor device according to claim 1, further comprising: one of the voltage terminals connected to a contact lead electrode of a first conductivity type connected to the buried layer. One of the current terminals is connected to a first conductive type contact lead electrode connected to a first conductive type buried layer formed in the semiconductor substrate, and a hole current flowing from the current terminal is connected to the wiring layer. The semiconductor device according to claim 1, wherein the semiconductor device flows out to the one current terminal directly below. 9. The semiconductor device according to claim 1, wherein an input of a power device is controlled by the Hall voltage, and a current flowing through the power device is made constant. 10.

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