JP2010283742A - Semiconductor device, signal transmission system, and signal transmission method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device, a system, and a method that optimize determinations of a termination resistance value of a receiver and an on resistance of a driver, and decrease the number of processes required for the determinations. <P>SOLUTION: The termination resistance value (RTT) of the receiver and the on resistance Ron of the driver are adjusted so that the DC voltage level of a transmission signal equals the level at one end of amplitude of an AC voltage. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a signal transmission technique for a semiconductor device, and more particularly to a semiconductor device including a receiver, a signal transmission system, and a signal transmission method.

  In a high-speed digital signal transmission system, an on-chip termination resistor circuit represented by ODT (On Die Termination) such as DDR (Double Data Rate) 2 and DDR 3 DRAM (Dynamic Random Access Memory) has a plurality of terminations prepared in advance. A termination resistance value is selected and used from among the resistance values according to the system configuration, for example, at the time of system initialization. The same applies to the ON resistance Ron of the driver chip.

  FIG. 1 is a diagram showing a typical example of a system configuration at the time of DDR3 DQ system READ. Referring to FIG. 1, the DRAM 1 includes a driver 11 and a termination resistor (ODT) 12 commonly connected to pins (input / output pins) of the DRAM package. The receiver is not shown. The driver 11 of the DRAM 1 is shown in an equivalent circuit model with a signal source (voltage source) (SG1) connected in series to the on-resistance Ron, and is connected to the input / output pins of the DRAM package (PKG) via the switch SW1. Has been. The other end of the termination resistor (one end is connected to the termination voltage (1/2) (VDDQ)) of the ODT 12 is connected to the input / output pin of the DRAM package (PKG) via the switch SW2. The ODT generally has a Thevenin termination, but is shown as an equivalent circuit in the figure.

  The memory controller 2 includes a driver 21 and a termination resistor (ODT) 22 commonly connected to the input / output pins of the package. The receiver is not shown. The driver 21 is shown by an equivalent circuit model using a signal source (voltage source) (SG2) connected in series to the on-resistance Ron, and is connected to an input / output pin of the package (PKG) via the switch SW3. The other end of the termination resistor (one end is connected to the termination voltage (1/2) (VDDQ)) of the ODT 22 is connected to the input / output pin of the package (PKG) via the switch SW4. Since the example shown in FIG. 1 is a configuration at the time of READ, the switch SW1 of the driver 11 of the DRAM 1 is turned on and the switch SW2 of the ODT 12 is turned off. The switch SW3 of the driver 21 of the memory controller 2 is turned off, and the switch SW4 of the ODT 22 is turned on. The output of the driver 11 of the DRAM 1 is transmitted to the package (PKG) of the memory controller 2 via a DRAM package (PKG), a DIMM (Dual Inline Memory Module) substrate 3 and a motherboard substrate 4.

  Patent Document 1 discloses a configuration including a comparison circuit that compares an output level of an output buffer and a reference voltage as an impedance matching circuit that automatically matches an output impedance and a transmission line impedance.

JP-A-11-27132

  The analysis according to the invention is given below.

  In determining the termination resistance value of the receiver and the resistance value of the on-resistance Ron of the driver, a technique of selecting a good SI (Signal Integrity) from an empirical rule and a simulation result is used. For this reason, man-hours are required for the determination, and the optimal one cannot always be selected.

  In order to solve one or more of the above-described problems, the present invention is generally configured as follows.

  According to the present invention, there is provided a method for suppressing jitter of a transmission signal by matching the DC voltage level of the transmission signal and the AC amplitude voltage level by adjusting the termination resistance value of the receiver and the on-resistance of the driver.

  According to the present invention, a semiconductor device is provided in which the jitter of a transmission signal is suppressed by matching the DC voltage level of the transmission signal with the AC amplitude voltage level by adjusting the termination resistance value of the receiver.

  According to the present invention, there is provided a semiconductor device that suppresses jitter of a transmission signal by matching the DC voltage level of the transmission signal with the AC amplitude voltage level by adjusting the on-resistance of the driver.

  According to the present invention, it is possible to reduce the man-hours required for determining the termination resistance value of the receiver and the on-resistance of the driver. Further, according to the present invention, the termination resistance value of the receiver and the on-resistance of the driver can be optimized.

It is a figure which shows the system structural example at the time of DDR3 DQ type | system | group READ. It is a figure explaining the 1st Example of this invention. It is a figure explaining the 2nd Example of this invention. It is a voltage waveform of the DQS strobe signal when the AC voltage level does not coincide with the DC voltage level. It is a voltage waveform of the DQS strobe signal when the AC voltage level and the DC voltage level are matched. FIG. 5 is a diagram showing an eye pattern when the voltage level of FIG. 4 and the DC voltage level do not match. It is a figure which shows the eye pattern at the time of making the voltage level and DC voltage level of FIG. 5 correspond. It is a voltage-time waveform when the on-resistance Ron is adjusted to make the DC level and the AC level coincide. It is the waveform which made the waveform when the AC amplitude voltage level and DC voltage level of FIG. 8 correspond correspond to the eye pattern display. It is a figure which shows the structure which performs ODT training which makes an AC voltage level and DC voltage level correspond at the time of system initialization. It is a flowchart explaining the setting of the optimal ODT value.

  In the present invention, in the signal transmission system, the termination resistance value is determined using the DC voltage level as the guideline to match the AC amplitude voltage level of the input signal waveform obtained by simulation or actual measurement.

  FIG. 2 is a diagram for explaining the first embodiment of the present invention, where a system from a driver LSI to a receiver LSI via a transmission path consisting of a DIMM wiring, a socket, and a motherboard wiring is constructed with a simulation model. It is a figure which shows the example of a structure. FIG. 2A illustrates a driver simulation model 5, a transmission line simulation model 7, and a receiver simulation model 6. The simulation is executed while changing the resistance value RTT of the termination resistance model 62 of the receiver simulation model 6, and from the voltage-time waveform of the pin portion of the receiver LSI package (PKG) (simulation waveform of FIG. 2B), AC An amplitude voltage level (AC voltage level) and a DC voltage level are obtained, and a termination resistance value RTT that matches these is selected. The following description starting with FIG. 2 is described at the time of Read (reading), but the same applies at the time of Write.

  FIG. 3 is a diagram for explaining a second embodiment of the present invention. As shown in FIG. 3A, in this embodiment, a system from the driver LSI 5 ′ to the receiver LSI 6 ′ via the transmission path 7 ′ including the DIMM wiring, socket, and motherboard wiring is constructed with an actual machine. .

  While changing the resistance value RTT of the terminating resistor 62 ′, a signal transmission test is performed, the pin portion of the receiver LSI 6 ′ is observed with the signal measuring probe 8, and from the observed waveform (actually measured waveform in FIG. 3B), An AC amplitude voltage level and a DC voltage level are obtained, and a termination resistance value that matches them is selected.

  When changing the on-resistance of the driver, similarly to FIG. 2 or FIG. 3, a simulation or a signal transmission test is executed, and the AC amplitude voltage level and DC are calculated from the voltage-time waveform of the pin portion of the receiver LSI 6 ′. A voltage level is obtained, and a driver-on resistance value Ron that matches both is selected.

  4 shows the voltage-time waveform of the DQS (data strobe) signal when the AC amplitude voltage level and the DC voltage level do not match (signal measurement probe 8 of the DQS strobe signal at the package pin of the receiver LSI 6 ′ in FIG. 3). Monida waveform). This waveform is represented by DQS-DQS # of the differential strobe signal composed of DQS and DQS #. The same applies to the following waveforms.

  There is a difference between the DC voltage level of the portion where the driver output of the voltage-time waveform (output of the driver LSI 5 ′ in FIG. 3) is fixed low and the AC voltage level of the lower limit portion of the amplitude after the driver output starts pulse transmission. Can be easily observed. At this time, the driver on resistance Ron is 34 ohms, the RTT is 60 ohms, that is, the ODT is 60 ohms.

  A circuit (not shown) capable of observing the DC voltage level and the AC amplitude level is incorporated in the receiver portion (receiver LSI 6 'in FIG. 3), and the termination at which the DC voltage level and the AC amplitude level coincide automatically at system initialization. The resistance value may be determined. This will be described later with reference to FIGS.

  FIG. 5 is a diagram in a case where the AC amplitude voltage level (low voltage at the lower end of the amplitude) and the DC voltage level are matched by adjusting the termination resistance value (RTT) of the receiver LSI 6 ′ in FIG. 3. At this time, the driver on resistance Ron is 34 ohms, and the ODT is 35 ohms.

  FIG. 6 shows a waveform in which the AC amplitude voltage level and the DC voltage level in FIG. 4 do not coincide with each other in an eye pattern in which the jitter of the transmission signal can be easily observed. In a system in which the AC amplitude voltage level and the DC voltage level do not match, the jitter is as large as 122 ps (pico second).

  FIG. 7 is a waveform in which the waveform when the AC amplitude voltage level and the DC voltage level in FIG. Thus, by adjusting the termination resistance value (RTT) and matching the AC amplitude voltage level with the DC voltage level, the jitter can be greatly reduced to 51 ps.

  Note that changing the DCLow voltage level VOL (LOW bell output voltage) can also be realized by changing the resistance value of the on-resistance Ron of the driver, as can be seen from Equation (1). In Expression (1), Rs is a stub resistor, RTT is a termination resistor, Ron is a driver-on resistance, and VTT is a termination power supply voltage. Here, for simplicity, the level of a single-ended signal of DQS alone will be described.

（１）

(1)

  However, when the resistance value of the on-resistance Ron of the driver is increased in order to increase the DC level, the rising transition level Vr of the first DQS signal decreases as can be seen from the equation (2).

（２）

(2)

Here, Z ₀ is the characteristic impedance of the DIMM wiring, and V _out is the output transition level of the driver when there is no load. For this reason, the influence of ISI (intersymbol interference) remains, and the adjustment of the on-resistance Ron of the driver may reduce the jitter amount little.

  FIG. 8 is a voltage-time waveform when the resistance value of the on-resistance Ron of the driver is adjusted to make the DC voltage level coincide with the AC voltage level. As described above, it is possible to make the AC amplitude voltage level and the DC voltage level coincide with each other even if the on-resistance Ron of the driver is adjusted, but the Ron resistance value is as small as 5 ohms.

  FIG. 9 is a waveform in which the waveform when the AC amplitude voltage level and the DC voltage level in FIG. As described above, the jitter can be reduced to 90 ps even by adjusting the on-resistance Ron of the driver, but the jitter reduction effect is small as compared with the case where the termination resistance value RTT is adjusted (51 ps).

  10 and 11 are diagrams for explaining still another embodiment of the present invention. FIG. 10 shows a system configuration for performing ODT training for matching the AC voltage level and the DC voltage level at the time of system initialization. FIG. 11 is a flowchart for explaining the operation flow. Referring to FIG. 10, a signal from the output circuit 101 of the driver LSI 10 is input to the receiver LSI 20. A first comparator 204 that compares the input signal with the output of the rising voltage generation circuit 205, a voltage storage circuit 206, a second comparator 207 that compares the AC voltage Vac and the DC voltage Vdc of the voltage storage circuit 206, and An ODT control circuit 202 that receives the output of the second comparator 207 and the output of the optimum ODT setting control circuit 208 and an ODT circuit 201 that receives the output of the ODT control circuit 202 are provided. Next, the operation will be described.

  First, the resistance value of the ODT 12 of the receiver LSI 20 is set to the maximum value of the receiver LSI 20 (step S1).

  Thereafter, a toggle pulse of 01010... Is output from the driver LSI 10 (step S2).

  In this state, a voltage that gradually increases from 0 V is generated from the rising voltage generation circuit 205 (step S3), and the output of the driver LSI 10 and the output of the rising voltage generation circuit 205 are input to the first comparator 204.

  When the voltage of the rising voltage generation circuit 205 reaches the low level of the toggle pulse, the output of the first comparator 204 is inverted. The output voltage (AC voltage level Vac) of the rising voltage generation circuit 205 at this time is stored in the voltage storage circuit 206 (step S4).

  Next, the output of the driver LSI 10 is set to Low (step S5).

  In this state, the rising voltage generation circuit 205 again generates a voltage that gradually increases from 0 V (step S6), and inputs both to the first comparator 204.

  When the output voltage of the rising voltage generation circuit 205 reaches the Low level of the driver LSI 10, the output of the first comparator 204 is inverted. The output voltage (DC voltage level Vdc) of the rising voltage generation circuit 205 at this time is stored in the voltage storage circuit 206 (step S7).

  Vac and Vdc are input to the second comparator 207, and the magnitude relationship between Vac and Vdc is compared (step S18).

  Initially, Vdc is lower than Vac, so the value of ODT12 of the receiver LSI 20 is set to a value that is one step smaller (step 19), the process returns to step S2, and the processes of steps S2, S3, S4, S5, S6, and S7 are performed. repeat.

  If Vdc> = Vac, the training is terminated (step S20), and the set ODT value (resistance value of the termination resistor RTT) is used in the system.

  Instead of the rising voltage generation circuit 205 that outputs a voltage that monotonously increases from 0 V at a predetermined slew rate, a voltage generation circuit that outputs a voltage that gradually decreases from a predetermined potential at a predetermined slew rate is provided. The output of the generation circuit may be input to the first comparator 204 and compared with the DC voltage and the AC amplitude voltage.

  It should be noted that the disclosures of the above patent documents are incorporated herein by reference. Within the scope of the entire disclosure (including claims) of the present invention, the embodiments and the embodiments can be changed and adjusted based on the basic technical concept. Various combinations and selections of various disclosed elements are possible within the scope of the claims of the present invention. That is, the present invention of course includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the technical idea.

1 DRAM
2 Memory controller 3 DIMM board 4 Motherboard board 5 Driver simulation model 5 'Driver LSI
6 Receiver simulation model 6 'Receiver LSI
7 Transmission path simulation model 7 'Transmission path 8 Signal measurement probe 10 Driver LSI
11 Driver 12 ODT
20 Receiver LSI
21 Driver 22 ODT
51 Driver ON resistance (Ron)
62 Terminating resistor model 62 ′ Terminating resistor 101 Output circuit 201 ODT circuit 202 ODT control circuit 203 Input circuit 204 Comparator 1
205 rising voltage generation circuit 206 voltage storage circuit 207 comparator 2
208 Optimal ODT setting control circuit

Claims (14)

A receiver with a terminating resistor;
Means for adjusting the resistance value of the termination resistor;
And the resistance value of the termination resistor is adjusted so that the DC voltage level of the input signal waveform in the receiver matches the level of one end of the amplitude of the AC voltage. The receiver is
A voltage generation circuit that changes the output voltage at a predetermined slew rate; and
A first comparator for comparing an input signal of the receiver and an output voltage of the voltage generation circuit;
A voltage storage circuit that holds the output voltage of the voltage generation circuit when the output of the first comparator is inverted;
In the first comparator, a comparison is made between the level of one end of the amplitude when the input signal is an AC voltage and the output voltage of the voltage generation circuit, and the DC voltage level and the voltage generation when the input signal is a DC voltage. A second comparator for comparing two voltages respectively stored in the voltage storage circuit by comparison with an output voltage of the circuit;
A control circuit for controlling a resistance value of the termination resistor based on an output of the second comparator;
The semiconductor device according to claim 1, further comprising: It has a driver that outputs a signal,
A semiconductor device, wherein the on-resistance of the driver is adjusted so that a DC voltage level of a signal waveform output from the driver and received by a receiver matches a level of one end of an AC voltage amplitude. A driver that outputs a signal;
A receiver that matches the DC voltage level of the input signal waveform from the driver with the level of one end of the amplitude of the AC voltage by adjusting the resistance value of the termination resistor;
A signal transmission system comprising: The receiver is
A voltage generation circuit that changes the output voltage at a predetermined slew rate; and
A first comparator for comparing an input signal and an output voltage of the voltage generation circuit;
A voltage storage circuit that holds the output voltage of the voltage generation circuit when the output of the first comparator is inverted;
In the first comparator, a comparison is made between the level of one end of the amplitude when the input signal is an AC voltage and the output voltage of the voltage generation circuit, and the DC voltage level and the voltage generation when the input signal is a DC voltage. A second comparator for comparing two voltages respectively stored in the voltage storage circuit by comparison with an output voltage of the circuit;
A control circuit for controlling a resistance value of the termination resistor based on an output of the second comparator;
The signal transmission system according to claim 4, further comprising: Set the receiver's termination resistance value to its maximum value,
From the driver, output a toggle pulse that alternately takes binary levels,
In this state, the voltage generation circuit generates a voltage from a predetermined potential at a predetermined slew rate, and compares the first level of the toggle pulse input from the driver with the output voltage of the voltage generation circuit by the first comparator. When the voltage of the voltage generation circuit reaches the first level of the toggle pulse, the output of the first comparator is inverted, and the output voltage of the voltage generation circuit at this time is used as an AC voltage in the voltage storage circuit. Store and
Next, the output of the driver is set to a first level DC voltage. In this state, the voltage generation circuit generates a voltage from a predetermined potential at a predetermined slew rate, and the DC voltage level input from the driver is The output voltage of the voltage generation circuit is compared with the first comparator, and when the output voltage of the voltage generation circuit reaches the DC voltage level from the driver, the output of the first comparator is inverted. The output voltage of the voltage generation circuit is stored as a DC voltage in the voltage storage circuit,
The two voltages of the AC voltage and the DC voltage stored in the voltage storage circuit are input to the second comparator and compared in magnitude.
When the DC voltage is lower than the AC voltage, the resistance value of the termination resistor is set to a small value, and a series of processes from the toggle pulse output from the driver is performed again.
6. The signal transmission system according to claim 5, wherein when the DC voltage is equal to or higher than the AC voltage, training is terminated and a set termination resistance value is used. A receiver having a terminating resistor and receiving a signal transmitted from the driver;
A driver for adjusting the DC voltage level of the input signal waveform at the receiver and the level of one end of the amplitude of the AC voltage by adjusting the on-resistance;
A signal transmission system comprising:   A signal transmission method comprising adjusting a resistance value of a termination resistor of the receiver so that a DC voltage level of a signal waveform transmitted from a driver and inputted to the receiver matches a level of one end of an amplitude of the AC voltage. .   A signal transmission method comprising adjusting a resistance value of an on-resistance of the driver so that a DC voltage level of a signal waveform transmitted from a driver and inputted to a receiver matches a level of one end of an amplitude of an AC voltage. . A simulation is performed for a transmission system in which the termination resistance value of the receiver is changed,
9. The signal transmission method according to claim 8, wherein an AC voltage level and a DC voltage level are obtained from an input signal waveform in the receiver, and a termination resistance value that matches them is selected. Perform a signal transmission test on the transmission system after changing the termination resistance value of the receiver,
9. The signal transmission method according to claim 8, wherein an AC voltage level and a DC voltage level are obtained from an input signal waveform shape in the receiver, and a termination resistance value that matches them is selected. A simulation is performed for a transmission system in which the on-resistance of the driver is changed,
The signal transmission method according to claim 9, wherein an AC voltage level and a DC voltage level are obtained from an input signal waveform in the receiver, and an on-resistance value that matches these is selected. Perform a signal transmission test on the transmission system after changing the on-resistance value of the driver,
10. The signal transmission method according to claim 9, wherein an AC voltage level and a DC voltage level are obtained from an input signal waveform shape in the receiver, and an on-resistance value that matches these is selected. (A) The termination resistance value of the receiver is set to its maximum value,
(B) A toggle pulse that alternately takes binary levels is output from the driver. In this state, a voltage that monotonously changes from a predetermined potential is generated from the voltage generation circuit, and the first toggle pulse input from the driver is generated. The level and the output voltage of the voltage generation circuit are compared by a first comparator. When the output voltage of the voltage generation circuit reaches the first level of the toggle pulse, the output of the first comparator is inverted. The output voltage of the voltage generation circuit is stored as an AC voltage in a voltage storage circuit,
(C) The output of the driver is fixed to a DC voltage of a first level, and in this state, a voltage that monotonously changes from a predetermined potential is generated from the voltage generation circuit, and the DC voltage input from the driver and the voltage The output voltage of the voltage generation circuit is compared by the first comparator, and when the output voltage of the voltage generation circuit reaches the DC voltage from the driver, the output of the first comparator is inverted, The output voltage of the voltage generation circuit is stored in the voltage storage circuit as a DC voltage,
(D) The two voltages of the AC voltage and the DC voltage stored in the voltage storage circuit are compared by a second comparator,
(E) As a result of comparison, when the DC voltage is lower than the AC voltage, the resistance value of the termination resistor is set to a small value, and again, a series of toggle pulse outputs from the driver of (b) is set. Process,
(F) If the DC voltage is equal to or higher than the AC voltage, the training is terminated and the set termination resistance value is used.
The signal transmission method according to claim 8.

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