JP2010282651A - Processing activity masking in data processing system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data processing system having resistance against security attacks. <P>SOLUTION: Within a data processing systems supporting conditional write processing operations, a trash register is provided such that when non-write conditions are encountered a register write is made to the trash register rather than the data register specified by the conditional write operation. Thus it becomes unable to observe the power fluctuation associated with whether or not a register write does or does not occur from the outside. The trash register may be programmable enabled and disabled by a configuration parameter stored within a system configuration register. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to the field of data processing systems. In particular, the present invention relates to a mask of processing operations within a data processing system, for example to increase security.

  It is known to provide a data processing system that handles secure data, and therefore it is desirable to ensure a high degree of security. As an example, it is known to provide a smart card, which includes a data processing system that handles secure data, such as a secret cryptographic key, and keeps this data secret to prevent counterfeiting. I have to keep it.

  As a method of attacking the security of such a system, a method including timing analysis and power analysis is known. By observing the timing behavior and power consumption behavior of this type of system in response to input, information about the processing being performed and the data being processed can be determined so that security can be compromised. It is very advantageous to have resistance against security attacks.

A data processing device provided as one aspect of the present invention includes:
A result data value generation circuit operable to generate a result data value when performing a data processing operation;
A data processing register into which the result data value is written,
At least one data processing operation executed by the result data generation circuit is a conditional write data processing operation, and the result data value for the conditional write data processing operation is a data processing register when a non-write condition is satisfied Is not written to
Further, the data processing apparatus includes a trash register that can write a result data value when a conditional write data processing operation is executed when a non-write condition is satisfied.

  The present invention recognizes that the power consumption associated with writing to the data processing registers is characteristic and, therefore, information regarding the data processing being performed can be observed from the outside accompanying the conditional write data processing operation. Yes. The information here is information regarding whether or not conditional writing has occurred. The present invention addresses this problem and writes a result value (preferably a true value) to the trash register when a conditional write data processing operation satisfies its non-write condition. In other cases, writing will not occur. Therefore, a register write to a true register or a trash register always occurs regardless of whether a write condition or a non-write condition is satisfied. This increases the security of this system.

  The data register that is normally written when the write condition is satisfied is preferably a register bank including a plurality of such registers. In this environment, a common trash register (s) can be used for dummy writing regardless of how many real data registers are provided in the register bank.

  The trash register is preferably physically provided as part of the register bank. This is because information leakage is prevented by observing which part of the circuit is operating at an arbitrary predetermined time.

The present invention is applicable to a wide range of systems, such as microprocessor-based systems and digital signal processing systems, for example, but the present invention is particularly well suited for systems that include a processor core that responds to data processing instructions. These instructions often include conditional write instructions that cause potential vulnerabilities addressed by this technology.
It will be appreciated that when certain conditions are met, a conditional write operation may or may not occur.

  It will be appreciated that reducing power consumption as much as possible is a normal technical desire in this field. Thus, it would normally be considered that it would be an advantageous feature not to perform a register write when a conditional write operation is not required. This is because it reduces power consumption. The technique of the present invention counters this technical desire in this field and consumes power by carefully performing a trash register write even if it is not necessary for the actual processing operation of the system. .

  In the preferred embodiment of the present invention, the operation of the trash register can be selectively enabled and disabled according to control signals stored in the system configuration register. This allows programmable operation of the trash register operation, and can save power by disabling this function when unsafe processing is occurring. Furthermore, security when necessary, such as when processing encryption keys and decrypting passwords, is improved.

  As mentioned above, the trash register can be physically located in the register bank along with the normal data registers, but in the preferred embodiment, the trash register cannot be specified by any program instruction. Not mapped to Therefore, it is not visible as a register from the programmer's model. However, in the preferred embodiment, the trash register appears such that its operation can be enabled or disabled by a configuration parameter.

A data processing method provided as another aspect of the present invention includes:
A step of generating a result data value upon execution of the data processing operation, wherein at least one data processing operation to be executed is a conditional write data processing operation, and when the non-write condition is satisfied, the result data value is stored in the data processing register This is a data processing method in which data is not written to the trash register, but is written to the trash register instead.

1 shows an outline of a data processing system operable in a fixed timing mode and a variable timing mode. Outlines conditional programming instructions. 6 is a flow diagram that outlines some of the processing operations performed by an instruction decoder that operates in accordance with the techniques of the present invention. An outline of execution of a conditional branch instruction in the fixed timing mode is shown. 1 shows an overview of a data processing system including a plurality of circuit portions that can selectively enable a mandatory processing operation or a dummy processing operation. FIG. 2 shows an outline of a circuit portion capable of responding to both an essential enable signal and a random dummy operation enable signal, and an accompanying dummy operation enable circuit. FIG. 1 shows a schematic of a linear feedback shift register that can be used as a pseudo-random signal generator. It is a flowchart which shows the outline of control of the circuit part which performs essential processing operation and dummy processing operation. Fig. 2 schematically shows part of a register bank including a plurality of data processing registers, a plurality of dummy registers, a plurality of shared dummy registers and an unmapped trash register RT. When the conditional write operation fails the condition code, a dummy register write is performed to the trash register RT. 6 is a flow diagram illustrating an overview of a register write control circuit that works to balance the number of times a low-to-high transition occurs from high to low when a register write occurs. FIG. 6 is a table showing the relationship between bit transitions for specific bits in the data register and those for the three additional registers. These registers are configured to balance the high to low and low to high transitions associated with register writes. 6 is a flowchart showing an outline of control for writing to a trash register when a write operation fails its condition code. 1 shows an overview of a system having multiple instruction execution mechanisms for one instruction and a pseudo-random selection of execution mechanisms employed for at least some instructions. It is a flowchart which shows the outline of control of the system shown in FIG.

Next, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 shows a data processing system 2 including a processor core 4, a coprocessor 6 and a memory 8.
In operation, the processor core 4 fetches instructions and data from the memory 8. The instructions are sent to the instruction pipeline 10, where they execute pipeline stages such as, for example, fetch, decode, execute, store and write back one after another in successive processing cycles. Pipelined processors themselves are well known as a way to efficiently execute the instructions of several programs with partial overlap in order to improve processing performance.

  The data value read from the memory 8 by the processor core 4 is sent to the register bank 12, from which it is processed under the control of program instructions using one or more of the multiplier 14, shifter 16 and adder 18. . Other data manipulation circuits such as AND, OR, and circuits that perform logical operations such as count leading zeros can also be provided.

  FIG. 1 also includes an instruction decoder 20 in the processor core 4. This is supplied to various processing elements such as register bank 12, multiplier 14, shifter 16 and adder 18 in response to program instructions in instruction pipeline 10 to control the execution of data processing operations. Generating an execution control signal. As an example, an appropriate operand is read from the register bank 12 by a control signal generated by the decoder 20, supplied to an appropriate one of the multiplier 14, the shifter 16, and the adder 18, and written to the register bank 12. Results in being backed up.

  Coprocessor 6 is a system configuration coprocessor that includes a number of configuration registers 22. This register is written to set configuration control parameters under program control. These configuration control parameters can specify a number of points regarding the configuration of the data processing system 2 such as, for example, endianess. One of these configuration control registers 22 includes a bit that specifies whether the processor core should operate in a fixed timing mode or a variable timing mode. Although this bit is shown as an input to the instruction decoder 20, this bit can also be supplied to those points as needed to control the operation of various other points within the processor core 4. It will be understood. Depending on the fixed / variable bits, the processor core 4 operates in either a fixed timing mode or a variable timing mode. When operating in fixed timing mode, at least one program instruction having variable timing (ie, requiring a variable number of processing cycles to complete) when in variable timing mode is forced to have fixed timing instead. (E.g., requiring the most possible number of processing cycles to complete). This is done whether or not it could have been suppressed entirely or whether it could have been completed in fewer processing cycles. Since the instruction decoder 20 is primarily responsible for decoding program instructions and commanding the operation of other elements of the processor core 4, the instruction decoder 20 operates in either a fixed timing mode or a variable timing mode. It can play a major role in controlling the core 4. It is not necessary to have all variable timing instructions if operating in a fixed timing mode type.

  It will be understood from the above description that one bit in the configuration register 22 is shown as switching between a fixed timing mode and a variable timing mode. Instead, the configuration register 22 is provided with a plurality of bits to individually perform fixed or variable timing operations for various instructions, such as conditional instruction operations, uniform branch operations, disable early termination, etc. It may be enabled and disabled.

  FIG. 2 shows a schematic diagram of conditional instructions. This conditional instruction may be part of an instruction set that includes only some conditional instructions or only a part of an instruction set such as the ARM instruction set that is substantially fully conditional. Condition code 26 encodes a set of processor state conditions whether the associated instruction is executed or not. For example, the condition code 26 indicates that the instruction 24 will not be executed if a condition code currently set in the system indicates zero, a carry has occurred, an overflow has occurred, etc. It can be configured to prescribe. This type of instruction can be used for efficient program coding. The instruction executes regardless of its condition code, but the fixed / variable bits at least partially suppress conditional operations in that the result is not written so that the result affects the state of the processor.

  FIG. 3 shows an overview of a portion of the processing operations performed by the instruction decoder 20. Although FIG. 3 illustrates these processing operations as a logical sequence, in practice, these processing operations may be performed at least partially in parallel or in a different order.

  In step 28, instruction decoder 20 waits for a new instruction to be executed. When a new instruction is received, the process proceeds to step 30 where the condition code associated with the new instruction is read. In step 32, these condition codes are compared with the condition codes currently in the system. These condition codes that are now in the system are the result of previous processing activity in either the immediately preceding instruction or the most recent instruction that would have updated these condition codes.

  In step 34, a check is performed to check the condition code 26 of the instruction currently being executed and the existing condition code. If not, the process proceeds to step 36 and execution of the current instruction starts. Although FIG. 3 shows a system that executes when there is no match, in another embodiment it could be a system that runs when there is a match.

  Following step 36, the process proceeds to step 38, where a check is made as to whether the instruction can be terminated early. This premature termination occurs, for example, because one of the operands has a specific value such as zero or one, or during the next processing cycle where a specific partial result has occurred. If early termination is possible, the process proceeds to step 40 where a check is made as to whether the processor core 4 is now operating in a fixed timing mode or a variable timing mode. If the processor is in variable timing mode, processing proceeds to step 42, the instruction returns the result appropriately and ends prematurely, and processing returns to step 28.

  If the determination in step 40 indicates that the system is in fixed timing mode, processing proceeds to step 44 regardless of whether early termination is possible. Step 44 can proceed even if it is determined in step 38 that early termination is not possible, but the instruction is executed for one cycle. In the case of multi-cycle instructions such as multiply, divide, add or subtract, these generally require several cycles to execute, so after step 44 processing proceeds to step 46 where there is the largest number of cycles for that instruction. A determination is made as to whether has already been executed. If the largest number of cycles have been executed, the result will have occurred. If early termination is possible and the system was forcibly executing the next processing cycle, step 46 will execute this forced execution when the maximum number of processing cycles for this type of instruction has been reached. Will still show that it should stop. If the maximum number of processing cycles has not yet been executed, processing returns to step 38.

  If the collation result in step 34 is positive, the process proceeds to step 48. In this example, affirmative in the collation in step 44 indicates that execution of a specific instruction should be suppressed. Step 48 determines whether the system is currently in forced execution mode. If in forced execution mode, processing proceeds to step 50 where a forced dummy execution of the instruction will be performed. When the dummy execution is performed, the result is written in the trash register (see the trash register 51 in FIG. 1), not the destination specified in the instruction itself. This is to prevent the system status from being modified by certain program instructions. The program instructions should have been suppressed while maintaining substantially unchanged power consumption and should not be executed. If it is determined in step 48 that the system is not in the forced execution mode but in the variable timing mode, the process bypasses step 50 and returns to step 28. At this time, the program instruction is suppressed in a normal manner.

  It will be appreciated that FIG. 3 illustrates a typical system in which dummy execution is applied to failed instructions for all condition codes so that all early termination of instructions is suppressed. In fact, it is possible to apply these techniques to conditional instructions and a subset of instructions that can be prematurely terminated. The above multi-configuration control bits can be used to selectively activate features such as early termination suppression, but to other things such as dummy execution following a condition code failure (fail). Will not apply.

  FIG. 4 shows an overview of executing a conditional branch instruction in fixed timing mode. The sequence of instructions A and B is executed until a conditional branch instruction BEQ (branch upon equal) is reached. This instruction encodes the behavior that a particular branch is executed if the flag is set to indicate that the result is the same as the previous process, and is suppressed if this flag is not set. To do. If the condition code passes, that is, if the condition codes match, a branch is taken and processing proceeds to instructions X, Y, etc. If the condition code is unsuccessful, the BEQ instruction executes a branch to the next instruction C instead of suppressing the whole code. This is the same instruction that would have been reached if the BEQ instruction was already suppressed and not executed at all. However, in fixed timing mode, the BEQ would have consumed the same number of processing cycles, regardless of whether the condition code passed or failed. This helps to blur the results of previously performed data processing operations for those who are seeking access to secure data.

  FIG. 5 shows an overview of a data processing device 52 in the form of a programmable processor core. This processes data D in response to program instruction I. The data processor 52 includes a register bank 54, a multiplier 56, a shifter 58, an adder 60, an arithmetic logic unit 62, a load store unit 64, a data pipeline 66, an instruction decoder 68, and a random clock gating circuit 70. . A system configuration coprocessor CP1572 is connected to the processor core. The system configuration coprocessor CP15 72 has a system configuration register 74, which holds a plurality of flag values, each of which is a pseudo-random dummy for various circuit portions included in the data processing system 52. Serves to enable or disable operation. It will be appreciated that the data processing system 52 generally includes more circuit elements, which are omitted from the figure for clarity.

  Associated with multiplier 56 is a dummy activity enable circuit 76, which serves to enable dummy operations within multiplier 56 when appropriate. Alternatively, when the executing program instruction executes the request, it serves to move the multiplier 56 by passing a signal that enables the required operation. As previously described, similar dummy operation enable circuits 78, 80, 82, 84 are associated with the other circuit portions 58, 60, 62, 64, respectively.

  In operation, instructions to be executed are sent through instruction pipeline 66 to instruction decoder 68, generating enable signals driven by the instructions, and these signals being applied to the respective circuit portions. These enable signals select the data path through the data processing system 52, move the circuit portions to read their inputs, perform specific processing, and generate respective output signals. As an example, a multiplier accumulation operation could read data values from register bank 54, add them to multiplier 56 and adder 60, and write the result back to register bank 54. Accordingly, register bank 54, multiplier 56 and adder 60 will all follow the mandatory operation enable signal. These signals enabled the operation of these circuits and selected them, forming a complete data path. Different circuits have different power consumption characteristics and timing characteristics. By observing those parameters, it will be possible to observe externally which instruction is being executed. Accordingly, pseudo-random dummy operations of other circuits that are not required for the instruction being executed are also enabled. In this way, even if the shifter 58 is not used during execution of a particular multiplier's accumulation instruction, it is pseudo-random enabled to save power by shifting whatever value is applied to its input. Will consume. To avoid this dummy operation that changes the state of the circuit to an undesired state, the latch of its output will not be enabled. The dummy operation may interfere with the required operation, for example a circuit may pretend to sustain the output value. The dummy operation is enabled in a period that coincides with the normal operation timing with respect to the related circuit.

  Random clock gating circuit 70 receives a plurality of pseudo-random enable signals for various respective circuits, gates them and applies them to the respective circuits. This is done under the control of configuration parameters read from the system configuration register 74 in the system configuration coprocessor 72. These configuration flags indicate that dummy operations should be enabled for shifter 58, ALU 62 and multiplier 56, and not for adder 60 or load store unit 64. Show. Various pseudo-random dummy enable signals allow various pseudo-random dummy characteristics to be added so that they can be matched with their respective circuit portions involved. As an example, there may be another minimum enable time associated with the normal timing of the various circuit portions.

  Overall, it will be appreciated that the instruction decoder 68 acts as a circuit that enables the required operations. This enables the circuitry necessary to perform the data processing operation specified by the currently executing instruction. Overlapping this essential operation, various dummy operations will be enabled in other circuit portions. These are stimulated by dummy operation control circuits provided in the remaining portions of the data processing system 52. The dummy operation serves to mask the power consumption and timing characteristics associated with the required operation.

  FIG. 6 shows an outline of a circuit portion 86 that is controlled by both the essential enable signal en and the dummy enable signal ran. This circuit portion 86 can be thought of as a sequence of latches, during which processing logic processes data values. When genuine required operation is required, all latches that provide a data path through the circuit portion 86 will be enabled and any necessary processing will be performed between the input and output latches. When the dummy operation is instructed, only the input latch and the intermediate latch are enabled. Thus, a data path through all circuit portions is not provided and the output value produced by that circuit portion remains unchanged.

  FIG. 7 shows a linear feedback shift register of the type used to generate a pseudo-random clock signal. These clock signals can be provided to the random clock gating circuit 72 of FIG. Separate pseudo-random signal generators can be provided for the various circuit portions. The fixed clock frequency associated with the various pseudo-random generators can be changed to match the characteristics of this circuit portion and to further obscure the masking operation as needed.

  FIG. 8 shows an outline of control of the enable signal for the circuit portion. In step 88, it is determined whether or not the enable signal en is received from the instruction decoder 68. If such an enable signal has been received, processing proceeds to step 90. The enable signal received from the instruction decoder 68 indicates that an essential processing operation is required according to the genuine program instruction being decoded. Thus, step 90 enables input, output and clock signals for the circuit portion. If no enable signal en has been received from the instruction register at step 88, the process proceeds to step 92 where it is determined whether dummy operation of the circuit portion is allowed. If dummy operations are allowed, processing proceeds to step 94 where the input and clock for that circuit portion are enabled but the output from that circuit portion is not enabled. Then the circuit part takes on the dummy operation. If it is determined at step 92 that the dummy operation is not allowed as indicated by the system configuration parameter, the process ends by bypassing step 94.

  It will be appreciated that the process illustrated in FIG. 8 is in the form of a sequential flowchart. In fact, this control can be performed in different sequences, using circuit elements deployed in the data processing system 52. Although the operations are shown to be performed sequentially, in practice they can be performed in parallel or the control functions can be modified. Overall, when individual circuit portions are enabled, they will perform regular and mandatory operations in response to appropriate program instructions. It will then perform a dummy operation when allowed by the accompanying configuration parameters.

  FIG. 9 shows an outline of the register bank 96. This register bank is based on the ARM processor programmers model for user mode operation according to a processor designed by ARM, Cambridge, UK. In fact, additional registers may be provided for other processor modes, but these are omitted for clarity. Ordinary registers R0 to R15 are provided to hold data values. Registers R13, R14 and R15 generally serve to store program counter values, branch return address values and stack pointers. These tend to be data values unrelated to security. Therefore, transition balance at the time of data writing is not necessary for R13, R14, and R15. A trash register RT is provided in the register bank 96. This is used in conjunction with a conditional write that failed the condition code. Thus, a conditional write instruction that fails the condition code will typically not do any writing. However, using this system, even if the condition code fails, the failed conditional write instruction writes a data value to the trash data register RT. Any difference in power consumption or timing may accompany the condition code failure or condition code path of a conditional write operation, which masks the difference. The trash data register RT does not appear in the programmer's model so that it can be addressed with an operand that identifies the register in the instruction.

  Similar to the trash data register RT, additional registers 98 and 100 are also provided for the purpose of balancing the transition from high to low and from low to high. A dedicated dummy register 98 is provided for the data registers R0 to R12, similar to the trash data register RT. A shared dummy register 100 is provided for storing an exclusive OR inversion value and an exclusive OR value. It operates in response to each write to the data register according to the transition balance technique. The register write control circuit 102 serves to generate appropriate data values to be written to the additional registers 98, 100 in response to writing data values to the data registers. This symmetric write control is selectively enabled and disabled by appropriate system configuration control flags originating from the system configuration coprocessor 72.

  FIG. 10 is a flowchart showing an outline of the operation of the register write control circuit 102. In step 104, the circuit waits for a register write operation to be commanded. In step 106, it is determined whether this register write is for one of the data registers to which the symmetric write control system is applied or for one of the trash data registers RT. If the register write is not for these registers, the process proceeds to step 108, where the requested data value X is simply written to one of the registers R13, R14 and R15.

  If the register being written is capable of following a symmetric register write, step 110 serves to determine whether this function is currently enabled. If this feature is not currently enabled, processing proceeds to step 108. If this function is enabled, processing proceeds to step 112.

  At step 112, the register control circuit calculates the position of each bit in the data value. The value is the exclusive exclusive OR of the current bit being written at that location and the bit previously stored at that location. Then, an exclusive OR with the previously stored dummy register value is taken for that bit position (see FIG. 11). Register control circuit 102 also calculates the inverse of the decision as well. The inverted value of the bit is written as the data value to the data register. These values are calculated for all bits being written (eg, three dummy 32-bit values).

  In step 14, the data value is written to the data register in the same manner as in step 108. In step 116, the three additional values determined for each bit position in the register are written to the three additional registers. Steps 114 and 116 occur simultaneously. As will be described later with reference to FIG. 11, as a result, the number of transitions from high to low and from low to high is balanced and power is consumed.

  FIG. 11 shows a table of possible bit values before and after a data write operation. A data value is written to the register Rn. This register is a register to which a symmetric write operation is applied. Values at time t and time t + 1 are shown. The inverse of these values is simply determined. A dedicated dummy register 98 is supplied to each data register according to this symmetrical operation, and the dummy register 98 stores an inverted value of the data value currently held in the data register.

  The shared dummy register 100 is shown as Rd in FIG. For each bit position in the shared dummy register Rd, a new value to be written to the bit position when data writing occurs is determined by the function shown in the lower part of FIG. This function ensures that if the data value and the inverted value of the data value do not change, the corresponding bit in the shared dummy register and the inverted value will change. This table shows the change in the shared dummy register that occurs when the data value does not change and the shared value of the dummy register that does not change when the data value changes. Therefore, a fixed number of transitions is guaranteed for each write, ie, the number of transitions from high to low and from low to high are equally balanced.

  FIG. 12 is a flow diagram illustrating the operation of the dummy data register RD that writes when a write operation fails its condition code. At step 118, the control logic unit waits for an instruction to receive. This control logic unit may be an instruction decoder 68 or other logic unit. Step 120 determines whether the instruction has failed its condition code. If the instruction has not failed its condition code, the instruction is successfully executed at step 122 and writes to the register specified by the register operand in the instruction. If the instruction has failed its condition code, processing proceeds to step 124 where a determination is made as to whether dummy register writing is enabled. If they are not enabled, the process ends. If dummy register write is enabled, the process proceeds to step 126. In step 126, even if the condition code has failed, the data value calculated by the instruction whose condition code has failed is written to the trash data register RT. This balances power consumption and timing regardless of whether the condition code passes or fails. It will be appreciated that the trash data register RT also follows the transition balance mechanism described above.

  FIG. 13 shows a data processing system 128 in which at least some instructions have multiple instruction execution mechanisms. Data processing system 128 is of a type that supports native execution of at least some Java® bytecode instructions. This type of data processing system and native execution is described in published PCT patent application number WO-A-02 / 29555. All of this published application and, in particular, a description of software emulation of native hardware implementation and more complex Java bytecode selectivity are incorporated herein by reference.

  The Java (registered trademark) bytecode decoder 130 is selectively enabled and disabled by an input signal. If the Java bytecode decoder 130 is disabled, the received bytecode will trigger an exception. The exception initiates execution of software emulation code to manipulate Java bytecode using the native ARM sum instruction set. This support code is stored in the memory in the area 132 as shown. A Java® bytecode program 134 is also stored in the memory. When it is desired to blur the nature of Java program execution, the Java byte code decoder 130 can follow a pseudo-random signal. This signal selectively enables and disables this element so that the instruction execution mechanism for Java bytecode efficiently switches between a mixed hardware and emulation execution mechanism and a pure emulation mechanism. To be able to. The configuration control value in the system configuration register 136 indicates whether or not the Java (registered trademark) decoder 130 exists and whether or not the random enable and disable of the Java (registered trademark) decoder 130 is permitted. Is identified.

FIG. 14 shows an outline of processing of the received Java (registered trademark) bytecode. In step 138, Java® bytecode is received. Step 140 determines whether the Java decoder 130 is enabled. The pseudo-random enable and disable of the Java decoder 130 enables an efficient branch to either step 142 or 146. In step 142, the bytecode is always emulated, and in step 146, an attempt is made to execute the instruction in hardware. This obscures / masks the power characteristics associated with bytecode execution. If it is determined in step 146 that the particular Java® bytecode is not supported by the Java® decoder 130, this Java® bytecode is also emulated in software in step 142. I will. However, if Java® bytecode is supported in hardware, it is executed in hardware in step 146.

Claims (2)

In a data processing device,
A result data value generation circuit operable to generate a result data value when executing a data processing operation, and a data processing register into which the result data value is written;
At least one data processing operation executed by the result data generation circuit is a conditional write data processing operation, and the result data value for the conditional write data processing operation is the data when the non-write condition is satisfied Not written to the processing register
And a trash register that can write a result data value when the conditional write data processing operation is executed when the non-write condition is satisfied. In the data processing method,
Generating a result data value upon execution of the data processing operation, wherein at least one data processing operation to perform is a conditional write data processing operation;
A data processing method in which when a non-write condition is satisfied, the result data value is not written to the data processing register, but instead is written to the trash register

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