JP2010282359A - Method, device and program for circuit analysis, and recording medium with circuit analysis program recorded thereon - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To estimate an error with high accuracy when operating numerical analysis by using a two-stage diagonally implicit Runge Kutta method, and to shorten a calculation time by using the estimated error. <P>SOLUTION: A circuit analysis method includes: executing circuit equation setting processing for setting dy/dt=f(y) as the circuit equation of an electronic circuit including a switching element based on the characteristic information of the circuit element of the electronic circuit; executing analysis processing to solve the circuit equation by using an (a) formula and (b) formula by a two-stage diagonally implicit Runge Kutta method, and to calculate a solution y<SB>n</SB>in the n-th step (n is a natural number); and executing error estimation processing to calculate coefficients a<SB>1</SB>and a<SB>2</SB>of a (d) formula, and to calculate coefficients b<SB>1</SB>, b<SB>2</SB>and b<SB>3</SB>of an (e) formula, and to calculate an (f) formula to estimate an error ε of the solution y<SB>n</SB>by substituting the coefficients b1, b2, and b3 into a difference between an analytic solution y*<SB>n</SB>at a time t<SB>n</SB>obtained by using Taylor development of a solution y<SB>n-1</SB>and the solution y<SB>n</SB>of the (e) formula, and to estimate the error ε by the (f) formula. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a circuit analysis method, a circuit analysis device, a circuit analysis program, and a recording medium on which the circuit analysis program is recorded.

  In recent years, semiconductor power conversion devices that convert voltage, current, frequency, etc. in the use of electrical energy have been applied to various devices in the consumer, industrial, and transportation fields, and are important technologies for achieving high performance. It has become. On the other hand, in the field of development of semiconductor power converters, numerical analysis (simulation) is indispensable as a means of reducing the number of costly model tests and analyzing the behavior of semiconductor power converters. It has become a thing.

  In particular, when analyzing a transient phenomenon of an electronic circuit including a switching element such as a transistor, it is necessary to perform a simulation in consideration of the characteristics of the switching element in detail. In general, when a highly accurate simulation is performed, there is a problem that the calculation load increases and the calculation time increases.

  Therefore, there is a method of estimating the local truncation error and making the time step width at the time of executing the simulation variable so that this error becomes a predetermined value or less (see, for example, Patent Document 1). For example, since the time required for the switching operation is about several tens of nanoseconds, in that time, the time step width is about several nanoseconds, and at other times, about 100 nanoseconds to about 1 microsecond, Overall, the calculation time can be shortened.

  Here, the two-stage diagonal implicit Runge-Kutta method (hereinafter also referred to as 2S-DIRK (2-Stage Diagonally Implicit Runge-Kutta)), which is the numerical integration method used in the simulation, is the same quadratic as the trapezoidal rule. It is known that the numerical vibration does not persist as in the trapezoidal law (see, for example, Non-Patent Document 1 and Non-Patent Document 2). Therefore, 2S-DIRK is considered to be suitable as a numerical integration method used for simulating transient phenomena in electronic circuits including switching elements, but no method has been established to accurately estimate the truncation error. is the current situation.

JP 2007-328386 A (Claim 6)

Taku Noda, Kiyoshi Takenaka, Toshio Inoue, “Numerical Integration by the 2-Stage Diagonally Implicit Runge-Kutta Method for Electromagnetic Transient Simulations”, IEEE Transactions Power Delivery, vol. 24, No. 1, pp. 390-399, 2009 Toshio Inoue, Yuki Tanaka, Teruhisa Kumano “Power System Long-Time Dynamics Simulation Method: Development of Basic Program Focusing on System Voltage Characteristics”, Central Research Laboratory Research Report T01051, 2002

  In view of the above-described prior art, the present invention accurately estimates an error when performing a numerical analysis using a two-stage diagonal implicit Runge-Kutta method, and shortens the calculation time using the estimated error. An object of the present invention is to provide a circuit analysis method, a circuit analysis apparatus, a circuit analysis program, and a recording medium on which the circuit analysis program is recorded.

In order to achieve the above object, a first aspect of the present invention provides a computer including circuit equation setting means, analysis means, and error estimation means, wherein the circuit equation setting means includes an electronic circuit including a switching element. A circuit equation setting process for setting dy / dt = f (y), which is a circuit equation of the electronic circuit, is executed based on the characteristic information of the circuit element, and the analysis unit performs the following by the two-stage diagonal implicit Runge-Kutta method. of (a) using the formula and (b) equation solving the circuit equation, (n is a natural number) the n-th step executes the analysis process of calculating the solution y _n of said error estimation means, (b) By substituting the equation (d) into the right side of the equation and comparing the equation obtained by Taylor expansion with the equation (d), the coefficients a ₁ and a ₂ of the equation (d) are obtained, and this (a) (C) derived from the equation and the equation (b) Substituting the equations (d), (e) and the coefficients a ₁ and a ₂ into the right side of the equation, and comparing the equation obtained by Taylor expansion with the equation (e), the coefficient of the equation (e) b ₁ , b ₂ , b ₃ are obtained, and the coefficient b ₁ , b is calculated by adding the difference between the analytical solution y ^* _{n at} time t _n obtained using the Taylor expansion of the solution y _n-1 and y _{n in the} equation (e). b _2, b ₃ to estimate the error ε of the solution y _n by substituting (f) equation is calculated, the (f) circuit and executes the error estimation process for estimating the error ε by formula It is in the analysis method.

  In the first aspect, it is possible to realize a highly accurate numerical analysis with a small error by using the two-stage diagonal implicit Runge-Kutta method. In addition, since the error can be reduced, the calculation time can be shortened when performing numerical analysis for determining the time interval h based on the error.

According to a second aspect of the present invention, in the circuit analysis method described in the first aspect, d ² f / dt ^{2 in the} equation (f) is
The circuit analysis method is characterized by the following.

  In the second aspect, the error can be estimated based on the four solutions.

According to a third aspect of the present invention, in the circuit analysis method described in the first or second aspect, in the analysis process, the state change of the switching element and the solution y _n−1 calculated by the error estimation process after performing the time step size setting process for determining the time step size h based on the error epsilon, in circuit analysis method characterized by calculating solutions y _n.

  In the third aspect, the time interval h is determined by paying attention to the state change of the switching element that can cause the electronic circuit to be in a transient state, and the calculation time is longer than when the other elements in the electronic circuit are taken into consideration. It can be shortened.

  A fourth aspect of the present invention is a circuit analysis program for causing a computer to execute the circuit analysis method described in any one of the first to third aspects.

  A fifth aspect of the present invention resides in a computer-readable recording medium on which a circuit analysis program according to claim 4 is recorded.

  According to a sixth aspect of the present invention, there is provided a circuit analysis apparatus including a computer configured to execute the circuit analysis method according to any one of the first to third aspects.

  In any of the fourth to sixth aspects, the above circuit analysis can be performed using these, and a highly accurate error estimation can be realized using the two-stage diagonal implicit Runge-Kutta method. Calculation time can be shortened.

  According to the present invention, the two-stage diagonal implicit Runge-Kutta method is used to realize high-precision numerical analysis with a small error, and the calculation time is shortened by adopting a variable time step size based on the error. A circuit analysis method, a circuit analysis device, a circuit analysis program, and a recording medium on which the circuit analysis program is recorded are provided.

It is a block diagram which shows the structure of the circuit analysis apparatus which concerns on this invention. It is a block diagram which shows the hardware constitutions of the computer of the circuit analysis apparatus which concerns on this invention. It is a figure which shows the flow of the circuit analysis method which concerns on this invention. It is a figure which shows the flow regarding the error estimation process of the circuit analysis method concerning this invention. It is an image of the error estimation method which concerns on a comparative example. It is RC circuit diagram which is an analysis object of the circuit analysis method concerning the present invention. It is a graph which shows the error of the circuit analysis method concerning this invention, and the error of a comparative example (estimation method 2). It is a RLC circuit diagram which is an analysis object of a circuit analysis method concerning the present invention. It is a graph which shows the error of the circuit analysis method concerning this invention, and the error of a comparative example (estimation method 2). It is a chopper circuit diagram which is an analysis object of the circuit analysis method concerning the present invention. It is a graph which shows the voltage of MOSFET by the circuit analysis method concerning this invention. It is a graph which shows transition of the time step width by the circuit analysis method concerning the present invention. It is an inverter circuit diagram which is an analysis object of the circuit analysis method concerning the present invention. It is a graph which shows the inverter output current and IGBT voltage by the circuit analysis method concerning this invention.

  Hereinafter, a circuit analysis method and a circuit analysis apparatus according to embodiments of the present invention will be described. As shown in FIG. 1, the circuit analysis apparatus 1 according to the present embodiment is an apparatus including a computer 20 including units 11 to 13 that execute circuit equation setting processing, analysis processing, and error estimation processing. As shown in FIG. 2, the computer 20 includes storage means such as a CPU 21, a RAM 22, a ROM 23, and a hard disk 24, and an input device 30 such as a keyboard and a storage medium reading device and an output device 40 such as a display and a printer are connected to the computer 20. ing.

  As shown in FIG. 1, means that can be executed by the computer 20 are means for executing each process in a circuit analysis method to be described later. Specifically, the circuit equation setting means 11, the analysis means 12, and error estimation are performed. Means 13. Each of these means 11 to 13 reads and executes what is created as a circuit analysis program 10 for causing the computer 20 to execute a circuit analysis method described later.

  Here, the processing of the circuit analysis method will be described in detail with reference to FIG. As shown in the figure, first, a circuit equation setting process for setting dy / dt = f (y) which is a circuit equation of the electronic circuit based on the characteristic information of the circuit element of the electronic circuit including the switching element is executed (step S1). ). This process is executed by the circuit equation setting means 11. Specifically, circuit data recorded in the hard disk 24 or circuit data of a circuit to be analyzed is read into the RAM 22 via the input device 30, and a circuit equation is created based on the circuit data.

  The circuit data includes information indicating the characteristics of each electronic component constituting the electronic circuit and the connection relationship thereof. The circuit equation is a simultaneous equation in which the contact potential, the element current, and the element voltage of the analysis target circuit are variables. When the number of contacts of the analysis target circuit is Ns and the number of elements is Nb, Ns + 2Nb number of equations are obtained. Have.

Next, an analysis process for solving the circuit equation is performed by the two-stage diagonal implicit Runge-Kutta method. Specifically, when (n is a natural number) the n-th step to the solution the solution y _n of the analysis means 12, the initial value setting to set an initial value necessary for solving the circuit equation such as the initial solution y ₀ process (step S2), the process of determining the time step size h employed in the calculation process of the n-th step of the solution _{y n} (step S3), and executes calculation processing of the solution _{y n} at time _{t n} (the step S4) sequentially .

Then, the error estimating means 13 executes the error estimation process for estimating the error for the solution y _n (step S5). Finally, it is determined whether or not exceeds the calculated end time (step S6), and that is, if the time t _n does not exceed the predetermined time (Step S6: No), as the n + 1 th step Step S3~ S5 is executed. On the other hand, if the time t _n exceeds the predetermined time (step S6: Yes), the calculation is terminated.

Hereinafter, although the order will be changed, the calculation process of the solution y _n at time t _n will be described in detail. That is, the calculation process will be described on the assumption that the time interval h is determined by the determination process of the time interval h (step S3).

In the circuit analysis method according to the present invention, the circuit equation is solved by 2S-DIRK. At this time, the formula for proceeding from time t _n−1 to t _n with time step width h is as follows.

First, a temporary solution using the equation
Is calculated. Note that “s” is s = 1−1 / SQRT (2) (SQRT is a function for obtaining a square root) in 2S-DIRK, which is input in advance in the above-described initial value setting process (step S2) and stored in the RAM 22. Remember.

Next, a solution y _n at time t _n is obtained using the equation (10). In 2S-DIRK, α = −SQRT (2) and β = 1 + SQRT (2), which are previously input in the initial value setting process (step S2) and stored in the RAM 22.

Incidentally, the solution from the formulas described Equation 9 and number 10 y _n can be expressed as in equation 11 in equation (c).

Next, error estimation process for estimating the error ε of the solution y _n obtained by the calculation for (step S5) will be described.

First, the solution
Is expressed as (d), and (d) is substituted into the right side of (b), and the equation obtained by Taylor expansion and (d) are compared with the coefficient a of (d). _1, seek _{a 2.}

Here, the equation (d) can be expressed as the following equation (d1).

Substituting equation (d1) into the solution on the right side of equation (b) yields the following equation (d2).

When the equation (d2) is Taylor-expanded with the solution y _n−1 , the following equation (d3) is obtained.

When the right side of the formula (d1) and the right side of the formula (d3) are compared, the following formula (d4) is obtained, and it can be determined that a ₁ = 1 and a ₂ = 1.

Next, expressed as a solution _{y n} (e) expression.

The expression (e) can be expressed as the expression (e1) in the same manner as the expression 14.

Here, when the expressions (d1) and (e1) are substituted into the expression (c), the expression (e2) is obtained.

When the equation (e2) is Taylor-expanded with the solution y _n−1 , the equation (e3) is obtained.

Here, for a physical phenomenon, if the time interval h is sufficiently fine and can be regarded as linear,
Therefore, when the right side of equation (e1) is compared with the right side of equation (e3), equation (e4) is obtained.

Therefore, it can be determined that the coefficients b ₁ = 1, b ₂ = 1/2, and b ₃ ≈0.2071. Here, the analytical solution ^y _{* n} at time _{t n,} by using the Taylor expansion of _{y n-1} expressed by (h) formula.

(E3) the formula obtained by substituting _{b 1 = 1, b 2 =} 1/2, b 3 ≒ 0.2071 to equation to estimate the error epsilon (f) equation is obtained by the difference (h) and expression.

Incidentally, (f) in the formula ^for d ² f / dt 2 can be obtained as follows. When Taylor expansion is performed on y _n−3 , y _n−2 , and y _n−1 with respect to y _n , Equation 26 is obtained.

From the four equations in Equation 26,
And
It can be expressed as.

As described above, the solution y _n and its error ε at time t _n were calculated. Thereafter, as described above, the calculation is terminated or the time interval h is determined depending on whether the calculation end time is exceeded (see FIG. 3).

The time interval h is determined based on a change in the state of the switching element, for example, a change in the gate voltage and an error ε. The determination process of the time interval h will be described in detail with reference to FIG. First, in the initial value setting process, the minimum step size h _min that is the minimum value of the time step size, the maximum step size h _max that is the maximum value, the number of step extension prohibition steps (S _a , S _b ), and the maximum allowable error. A tolerance r which is a value is input in advance and stored in the RAM 22.

  Next, it is confirmed whether or not there is a state change in the gate voltage source or the switching element in the circuit (step S10).

  Here, attention is paid to the state change of the switching element because the calculation time becomes enormous if the time interval h is simply determined based on only the error ε. More specifically, especially in a complex circuit where there are hundreds to thousands of circuit elements, the number of dynamic elements such as inductors and capacitors is considerable. This is because it is stored (requiring four solutions as shown in the equation (g)), and the time increment h is determined for all errors for each element.

  On the other hand, an electronic circuit including a switching element, particularly a power electronics circuit, is characterized in that power conversion is performed by performing a commutation operation by ON / OFF of the switching element, and that power electronics circuits are generally the most common. A transient phenomenon with a short constant is a sudden change in current due to switching of the switching element.

  Therefore, in an electronic circuit including a switching element such as a power electronics circuit, if the state of the switching element, for example, a change in current is monitored, the circuit is in a transient state or a stable state after the transient state is converged. Can be determined.

  For this reason, the calculation time can be shortened by using the state change of the switching element as one of the conditions for determining the time interval h.

When there is a change in the state of the switching element, for example, the gate voltage (step S10: Yes), the time increment h is set to h _min, and h = h _min from the current step to after the _sa step. (Step S11).

Next, when there is no state change (step S10: No), and when the current step is not at the time step change prohibition time, the error εmax is compared with the allowable error r, and ε _max <0.1 ×. If r and h <h _max (step S12: Yes), the time interval h is doubled (step S13). The error ε _max is the maximum value of the error ε in the last few steps, for example, 10 steps. The error ε _max that is the maximum value of the error ε of the latest 10 steps is used because the time step h is coarse compared to the time constant of the physical phenomenon to be analyzed. This is to prevent the time interval h from being extended when the error is underestimated in the step. If the condition of step S12 is not satisfied (step S12: No), if ε _max > r and h> h _min (step S14: Yes), the time increment h is halved (step S15). If the time interval h is changed in step S13 or step S15, then the time extension is prohibited until _sb steps have elapsed.

In step S12, ε _max <0.1 × r is set because, from 2E-DIRK, the error increases 8 times if the time increment h is doubled in 2S-DIRK. In other words, if the current error estimated value is 1/8 or less of the allowable error r, the error in the next step will not exceed the allowable error r even if the time interval h is doubled. Because. In the above example, the margin is further increased, and if the error ε is 1/10 or less of the allowable error, the time interval h is doubled.

  According to the circuit analysis method described above and the circuit analysis device configured to execute the method, the circuit equation of the electronic circuit including the switching element is solved using 2S-DIRK and the error is estimated. Can do. Hereinafter, the accuracy of the error estimated by the circuit analysis method according to the present invention and the fact that the calculation time is shortened will be described by comparison with a comparative example. In comparison, comparison is also made with the true value of the error obtained approximately.

[Comparative example]
First, an error estimation method to be compared with the circuit analysis method according to the present invention will be described. In 2S-DIRK, in going from the time t _n-1 to t _n, both intermediate time

Solution at
The calculated ((a) type), then solving _{y n} at time _{t n.} The solution from solution yn _-1
The calculation method used when obtaining is the same as the backward Euler method. Therefore, the approximation, as shown in FIG. 5, the solution y _n-1 solution
The solution y _nb at the time t _{n obtained} from the straight line connecting can be considered as an approximate solution of the solution y _n-1 to the solution y _n obtained by the backward Euler method with a time interval h. The difference between the solution y _n and the solution y _nb is _defined as ε _b . If the time interval h is sufficiently small with respect to the phenomenon to be analyzed, the phenomenon can be linearly approximated, and the difference between the solution y _n and the solution y _nb becomes small. Backward Euler is one order accurate, because 2S-DIRK is a secondary precision, close y _n is sufficiently true value as compared to the y _nb. Therefore, epsilon _b can be assumed to seek approximate value of the local truncation error of Backward Euler. Although epsilon _b is not intended determine local truncation error directly 2S-DIRK, it is considered that the local truncation error of 2S-DIRK has a normal εb less, epsilon _b can be a measure of the local truncation error.

[True value of error ε _t ]
The true value ε _t of the error is approximately calculated in the next step.
(1) by performing a single integration time step size h, obtaining a calculated value _{y n} at time _{t n-1.}
(2) Approximate true value y ^* _n is obtained from time t _n−1 by performing integration 100 times with a time interval of 0.01 h. y ^* _n is not strictly a true value, since the time step size h is set to 1/100 of the case of obtaining the above (1), sufficiently compared with the calculated value y _n obtained in (1) true value Close to.
(3) The true value ε _t of the truncation error generated by the one-step integration is obtained from the difference between y _n and y ^* _n obtained in (1) and (2).
(4) the solution at time _{t n} as _{y n,} similarly calculating solutions _{y n + 1} at the time _{t n + 1.}

[Comparison of error estimation accuracy 1]
FIG. 6 is an RC circuit which is an example of an electronic circuit to be analyzed. FIG. 7 shows a comparison between the error ε calculated by the circuit analysis method according to the present invention, the error ε _{b of the} comparative example, and the true value ε _{t of the} error calculated for the RC circuit. In the figure, "estimation method 1", the error due to circuit analysis method according to the present invention, "estimation method 2" indicates the error epsilon _b according to the comparative example (hereinafter, the same applies in other comparison diagram. ). Specifically, FIG. 7A shows a comparison of errors when the time interval h is 1 ms, and FIG. 7B compares the error when the time interval h is 0.1 s.

In FIG. 7A, the error ε of the estimation method 1 completely overlaps the true value ε _{t of the} error, and in FIG. 7B, the error ε of the estimation method 1 is immediately after the voltage application (t Although an error is observed in the vicinity of = 0), after that, it almost coincides with the true value ε _{t of the} error. In any time interval h, the error ε _b of the estimation method 2 overestimates the truncation error compared to the estimation method 1 and the true value ε _t . As can be seen from a comparison between FIG. 7A and FIG. 7B, when the time interval h is increased, the error ε by the estimation method 1 is estimated to be larger than the error true value ε _t. ing. This means that the error is estimated on the safe side.

[Comparison of error estimation accuracy 2]
FIG. 8 shows an RLC circuit which is an example of an electronic circuit to be analyzed. FIG. 9 shows a comparison between the error ε calculated by the circuit analysis method according to the present invention, the error ε _b according to the comparative example, and the true value ε _{t of the} error calculated for the RLC circuit. Specifically, FIG. 9A shows a comparison of errors when the time interval h is 10 μs, and FIG. 9B compares the error when the time interval h is 200 μs.

Similar to “Comparison 1 of error estimation accuracy” described above, in FIG. 9A, the error ε of the estimation method 1 completely overlaps with the true value ε _{t of the} error, and in FIG. The error ε of the estimation method 1 substantially coincides with the true value ε _{t of the} error. In any time interval h, the error ε _b of the estimation method 2 overestimates the truncation error compared to the estimation method 1 and the true value ε _t .

  Table 1 shows the characteristics of the circuit analysis method (estimation method 1) and the estimation method 2 according to the present invention.

[Comparison of calculation time]
As described above, according to the circuit analysis method of the present invention, the error can be estimated with higher accuracy than the estimation method 2.

This contributes to shortening the calculation time by changing the time interval h more appropriately. This is because (1) electronic circuits including switching elements, particularly power electronics circuits, perform switching with a very short period, so that the time interval h can be extended at a time is short. (2) despite the possible extension time step size h, estimation of truncation error by the estimation method 2 for estimating excessive errors, because you can not extend the (error epsilon _b is close tolerances r. Figure 4 step 13 This is because of the reason.

  For this reason, according to the estimation method 2, there is a high possibility that the calculation time cannot be shortened because the time increment h cannot be increased even if the circuit is in a stable state after convergence of the transient state. On the other hand, according to the circuit analysis method of the present invention, since the error can be estimated with high accuracy, the time interval h can be shortened following the stable state after the convergence of the transient state, so the calculation time is shortened. be able to.

  In the following, when obtaining a solution by the circuit analysis method according to the present invention, it is shown that the solution can be calculated with high accuracy even when it is performed in variable time increments when compared with the case where the solution is performed in fixed time increments.

[Comparison with fixed time increment 1]
FIG. 10 shows a chopper circuit to be analyzed in this comparison. The circled portion in the figure shows a portion for monitoring the current of the switching element (MOSFET). FIG. 11 is a voltage-time graph of the switching element. In the figure, voltage values calculated by variable time increments (circuit analysis method of the present invention) and fixed time increments are shown.

The simulation conditions are h _min = 2 ns, h _max = 128 ns, r = 0.01 A, sa = 100, and sb = 12. The minimum time step is set to 2 ns because the MOSFET switching period is usually several tens of ns. Therefore, when trying to accurately reproduce the waveform at the time of MOSFET switching by simulation, the time step width h is about several ns. This is because it is necessary to set.

  As shown in FIG. 11 (a), the calculated values in variable time increments are in agreement with the fixed time increments indistinguishable from each other. Further, in FIG. 11B, which is an enlarged view of FIG. 11A, since the rise of the gate voltage is delayed due to the variable time increments, the waveforms do not completely coincide with each other. It has become.

  Further, FIG. 12 shows the transition of the time step width calculated by the variable time step. As shown in the figure, the time interval h becomes fine when the gate drive voltage changes and the MOSFET in the circuit is switching, and the switching period ends, and the circuit transient phenomenon occurs. It is shown that the time interval h is extended as the value of.

  In this comparison, 184 seconds were required for the fixed time step, and 5 seconds were required for the variable time step (the circuit analysis method of the present invention). In other words, the circuit analysis method according to the present invention is 37 times faster in this circuit. A computer with an Intel (R) Core (TM) 2 Quad CPU and 2.40 GHz CPU was used for the calculation.

[Comparison with fixed time increment 2]
In this comparison, the effect of shortening the calculation time is verified with a circuit having a large number of semiconductor elements that perform switching and a high switching frequency. FIG. 13 shows an inverter circuit to be analyzed in this comparison. This circuit is a combination of a step-up chopper and a single-phase inverter, and switching is performed using a total of five elements: one MOSFET in the step-up chopper and four IGBTs in the single-phase inverter. Further, the carrier frequency of the boost chopper is set to 72 kHz, and the carrier frequency of the single-phase inverter is set to 18 kHz. The circled portion in the figure is a portion for monitoring current truncation error.

  As shown in FIG. 14 (a), the inverter output currents according to the circuit analysis method according to the present invention are indistinguishable from each other as compared with the fixed time step. Further, as shown in FIGS. 14B and 14C, the waveform of the IGBT voltage also matches the circuit analysis method according to the present invention and the fixed time step so that they cannot be distinguished.

From 0 ms to 30 ms, when calculation is performed with h _min = 2 ns, h _max = 128 ns, r = 0.01 A, s _a = 250, s _b = 12, 18313 seconds in fixed time increments, in variable time increments It took 5249 seconds. In other words, the circuit analysis method according to the present invention is 3.48 times faster in this circuit.

  As described above, the circuit analysis method according to the present invention and the circuit analysis apparatus configured to execute the method use the two-stage diagonal implicit Runge-Kutta method to provide high-precision numerical values with small errors. While realizing the analysis, the calculation time can be shortened by adopting a variable time step based on the error.

  The present invention can be used in the industrial field of performing transient analysis of electronic circuits including switching elements.

DESCRIPTION OF SYMBOLS 1 Circuit analyzer 10 Circuit analysis program 11 Circuit equation setting means 12 Analysis means 13 Error estimation means 20 Computer 21 CPU
22 RAM
23 ROM
24 hard disk 30 input device 40 output device

Claims (6)

In a computer comprising circuit equation setting means, analysis means, and error estimation means, the circuit equation setting means is a circuit equation of the electronic circuit based on characteristic information of the circuit elements of the electronic circuit including the switching elements. A circuit equation setting process for setting / dt = f (y) is executed,
Said analyzing means, calculates the solutions y _n of solving the circuit equations using the following equation (a) and (b) expression by two-stage diagonal implicit Runge-Kutta method, first the n steps (n is a natural number) Run the analysis process
The error estimation means substitutes the equation (d) for the right side of the equation (b) and compares the equation obtained by Taylor expansion with the equation (d), thereby obtaining the coefficients a ₁ , to seek a _2, this formula (a) and (b) the right-hand side of the equation (c) that derived from the equation equation (d), by substituting the equation (e), and the coefficients _a 1, _{a 2,} to Taylor expansion By comparing the equation obtained by the equation (e) with the equation (e), the coefficients b ₁ , b ₂ , and b ₃ of the equation (e) are obtained, and the analysis at the time t _n obtained by using the Taylor expansion of the solution y _n−1. calculates the solutions ^y _* the the difference between _n and (e) expression _{y n} coefficients _{b 1,} b 2, to estimate the error ε of the solution _{y n} by substituting _{b 3} (f) formula, the ( f) A circuit analysis method characterized by executing an error estimation process for estimating the error ε according to the equation.
In the circuit analysis method according to claim 1,
D ² f / dt ^{2 in the} formula (f) is
The circuit analysis method characterized by the above-mentioned. In the circuit analysis method according to claim 1 or 2,
Wherein the analysis processing, the change of state of the switching element, after executing the error estimation processing time step size setting process of determining the calculated solution y _n-1 of the error ε time step size h based on the, solution y A circuit analysis method characterized by calculating _n .   A circuit analysis program for causing a computer to execute the circuit analysis method according to any one of claims 1 to 3.   A computer-readable recording medium on which the circuit analysis program according to claim 4 is recorded.   A circuit analysis apparatus comprising a computer configured to execute the circuit analysis method according to claim 1.