JP2010278120A5 - - Google Patents

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JP2010278120A5
JP2010278120A5 JP2009127576A JP2009127576A JP2010278120A5 JP 2010278120 A5 JP2010278120 A5 JP 2010278120A5 JP 2009127576 A JP2009127576 A JP 2009127576A JP 2009127576 A JP2009127576 A JP 2009127576A JP 2010278120 A5 JP2010278120 A5 JP 2010278120A5
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silicon carbide
carbide layer
semiconductor device
manufacturing
ratio
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JP5436046B2 (en
JP2010278120A (en
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上記目的を達成するために、この発明は、所定のオフ角を有する炭化珪素基板の表面上に、活性領域となる所定のC/Si比を有する第1の炭化珪素層を形成する第1工程と、前記第1の炭化珪素層の表面上に、前記所定のC/Si比より小さく、かつ、表面が平坦となるC/Si比を有する第2の炭化珪素層を形成する第2工程と、前記第2の炭化珪素層をエッチング除去する第3工程とを備えている。 To achieve the above object, the present invention provides a first step of forming a first silicon carbide layer having a predetermined C / Si ratio to be an active region on a surface of a silicon carbide substrate having a predetermined off angle. And forming a second silicon carbide layer having a C / Si ratio smaller than the predetermined C / Si ratio and having a flat surface on the surface of the first silicon carbide layer; And a third step of etching away the second silicon carbide layer.

以上の説明から明らかなように、この発明によれば、活性領域となる所定のC/Si比を有する第1の炭化珪素層の表面上に、所定のC/Si比より小さく、かつ、表面が平坦となるC/Siを有する第2の炭化珪素層を形成した後に、この第2の炭化珪素層をエッチング除去するようにした。これにより、第1の炭化珪素層表面に生じるステップバンチング部が除去されるので、凹凸の大きいステップバンチングに対しても平坦化可能であり、また平坦化にあたりCMP研磨などの研磨装置及び研磨工程も必要としないのでコスト増加も抑制することができる。 As is apparent from the above description, according to the present invention, the surface of the first silicon carbide layer having a predetermined C / Si ratio serving as the active region is smaller than the predetermined C / Si ratio and has a surface After the second silicon carbide layer having C / Si that becomes flat is formed, the second silicon carbide layer is removed by etching. Thereby, since the step bunching portion generated on the surface of the first silicon carbide layer is removed, it is possible to flatten even for step bunching with large unevenness, and a polishing apparatus such as CMP polishing and a polishing process are also required for the flattening. Since it is not necessary, an increase in cost can be suppressed.

Claims (9)

所定のオフ角を有する炭化珪素基板の表面上に、活性領域となる所定のC/Si比を有する第1の炭化珪素層を形成する第1工程、
記第1の炭化珪素層の表面上に、前記所定のC/Si比より小さく、かつ、表面が平坦となるC/Si比を有する第2の炭化珪素層を形成する第2工程、
記第2の炭化珪素層をエッチング除去する第3工程、
を含む炭化珪素半導体装置の製造方法。
A first step of forming a first silicon carbide layer having a predetermined C / Si ratio to be an active region on a surface of a silicon carbide substrate having a predetermined off angle ;
Before SL on the surface of the first silicon carbide layer, wherein less than a predetermined C / Si ratio, and a second step of forming a second silicon carbide layer having a C / Si ratio the surface becomes flat,
A third step of etching away the previous SL second silicon carbide layer,
A method for manufacturing a silicon carbide semiconductor device comprising:
前記第2の炭化珪素層を形成するC/Si比は0.8以下であり、
記第2の炭化珪素層を形成する温度は1600℃以下である
請求項1記載の炭化珪素半導体装置の製造方法。
C / Si ratio of forming the second silicon carbide layer is 0.8 or less,
Manufacturing method of the preceding Symbol silicon carbide semiconductor device of temperature according to claim 1, wherein at 1600 ° C. or less to form a second silicon carbide layer.
前記第2の炭化珪素層を形成するC/Si比は0.5であ
求項記載の炭化珪素半導体装置の製造方法。
C / Si ratio of forming the second silicon carbide layer is Ru 0.5 der
Motomeko 2 method for manufacturing the silicon carbide semiconductor device according.
前記第1の炭化珪素層を形成するC/Si比は1.5以上であり、The C / Si ratio forming the first silicon carbide layer is 1.5 or more,
前記第2の炭化珪素層を形成する温度は1550℃以上1650℃以下である  The temperature for forming the second silicon carbide layer is not less than 1550 ° C. and not more than 1650 ° C.
請求項1乃至3のいずれか1項に記載の炭化珪素半導体装置の製造方法。The manufacturing method of the silicon carbide semiconductor device of any one of Claims 1 thru | or 3.
前記所定のオフ角は、(0001)面に対して5度以下であるThe predetermined off angle is 5 degrees or less with respect to the (0001) plane.
請求項1乃至4のいずれか1項に記載の炭化珪素半導体装置の製造方法。The manufacturing method of the silicon carbide semiconductor device of any one of Claims 1 thru | or 4.
前記第2の炭化珪素層をエッチング除去する前記第3工程は、The third step of etching away the second silicon carbide layer includes:
水素ガスを用いたドライエッチングにより行われるPerformed by dry etching using hydrogen gas
請求項1乃至5のいずれか1項に記載の炭化珪素半導体装置の製造方法。The manufacturing method of the silicon carbide semiconductor device of any one of Claims 1 thru | or 5.
前記第2の炭化珪素層をエッチング除去する前記第3工程は、The third step of etching away the second silicon carbide layer includes:
前記第2の炭化珪素層の全部を熱酸化法により犠牲酸化膜に置換する第3a工程、  A step 3a of replacing the entire second silicon carbide layer with a sacrificial oxide film by thermal oxidation;
前記犠牲酸化膜を、フッ化水素酸を用いたウェットエッチングにより除去する第3b工程、  A 3b step of removing the sacrificial oxide film by wet etching using hydrofluoric acid;
を含む請求項1乃至5のいずれか1項に記載の炭化珪素半導体装置の製造方法。The manufacturing method of the silicon carbide semiconductor device of any one of Claims 1 thru | or 5 containing these.
前記第2の炭化珪素層をエッチング除去する前記第3工程は、The third step of etching away the second silicon carbide layer includes:
前記第2の炭化珪素層の一部を熱酸化法により犠牲酸化膜に置換する第3a工程、  A step 3a of replacing a part of the second silicon carbide layer with a sacrificial oxide film by a thermal oxidation method;
前記犠牲酸化膜を、フッ化水素酸を用いたウェットエッチングにより除去する第3b工程、  A 3b step of removing the sacrificial oxide film by wet etching using hydrofluoric acid;
を含み、前記第2の炭化珪素層が除去されるまで、前記第3a工程と前記第3b工程とを繰り返し行う請求項1乃至5のいずれか1項に記載の炭化珪素半導体装置の製造方法。6. The method of manufacturing a silicon carbide semiconductor device according to claim 1, wherein the step 3a and the step 3b are repeated until the second silicon carbide layer is removed.
前記第2の炭化珪素層をエッチング除去する前記第3工程は、The third step of etching away the second silicon carbide layer includes:
前記第2の炭化珪素層に加えて、前記第1の炭化珪素層の表面上に形成されたステップバンチングも除去するIn addition to the second silicon carbide layer, step bunching formed on the surface of the first silicon carbide layer is also removed.
請求項1、6乃至8のいずれか1項に記載の炭化珪素半導体装置の製造方法。A method for manufacturing a silicon carbide semiconductor device according to any one of claims 1, 6 to 8.
JP2009127576A 2009-05-27 2009-05-27 Method for manufacturing silicon carbide semiconductor device Expired - Fee Related JP5436046B2 (en)

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JP2010278120A5 true JP2010278120A5 (en) 2011-12-22
JP5436046B2 JP5436046B2 (en) 2014-03-05

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WO2021025084A1 (en) * 2019-08-06 2021-02-11 学校法人関西学院 SiC SEED CRYSTAL AND METHOD FOR PRODUCING SAME, SiC INGOT PRODUCED BY GROWING SAID SiC SEED CRYSTAL AND METHOD FOR PRODUCING SAME, AND SiC WAFER PRODUCED FROM SAID SiC INGOT AND SiC WAFER WITH EPITAXIAL FILM AND METHODS RESPECTIVELY FOR PRODUCING SAID SiC WAFER AND SAID SiC WAFER WITH EPITAXIAL FILM
US20220282395A1 (en) * 2019-08-06 2022-09-08 Kwansei Gakuin Educational Foundation SiC SUBSTRATE, SiC EPITAXIAL SUBSTRATE, SiC INGOT AND PRODUCTION METHODS THEREOF

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JPH11162850A (en) * 1997-08-27 1999-06-18 Matsushita Electric Ind Co Ltd Silicon carbide substrate and its production, and semiconductor element using the same
JP2007269627A (en) * 2002-03-19 2007-10-18 Central Res Inst Of Electric Power Ind METHOD FOR MANUFACTURING SIC CRYSTAL TO REDUCE MICROPIPE PROPAGATING FROM SUBSTRATE AND SiC CRYSTAL, SiC SINGLE CRYSTAL FILM, SiC SEMICONDUCTOR ELEMENT, SiC SINGLE CRYSTAL SUBSTRATE AND ELECTRONIC DEVICE, AND METHOD FOR MANUFACTURING SiC BULK CRYSTAL
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JP4954654B2 (en) * 2006-09-21 2012-06-20 新日本製鐵株式会社 Epitaxial silicon carbide single crystal substrate and manufacturing method thereof
JP2008112834A (en) * 2006-10-30 2008-05-15 Sumitomo Electric Ind Ltd Manufacturing method of silicon carbide semiconductor device
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