JP2010277632A - Storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a storage device which improves performance in writing in cluster units, while improving reliability at an edge of multiple value memory cell array. <P>SOLUTION: A storage device includes a plurality of memory cell blocks. In a memory cell block, a plurality of multiple value memory cells so constituted as to store m bits data (m is a natural number ≥2) are arranged at an intersection of word lines of p lines (p is a natural number ≥3) and bit lines of q columns (q is a natural number ≥2), wherein each word line has m pages from a first page to m-th page, and a memory cell block has n pages (n is a natural number which satisfies n<m×p). In at least one or more word lines which are not edges, page numbers are assigned to all the m pages, wherein a page number is assigned to a word line on at least one edge of each word line in the first page but no page number is assigned in the m-th page. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an electrically erasable and writable semiconductor memory device, and more particularly to a memory device capable of writing information in binary and multilevel values.

  In recent years, a nonvolatile storage device such as a memory card has been used as a storage medium for a portable information terminal represented by a digital camera or a mobile phone, and its market has been expanded. In addition, a nonvolatile memory such as a flash memory is mounted on the memory card. Such a non-volatile memory has increased in capacity with the miniaturization in the semiconductor process. Further, in the nonvolatile memory, the capacity is further increased by using the multi-value technology of the memory cell, and the bit unit price is lowered and it can be obtained at a low cost. In particular, NAND type flash memories are widely used because their bit unit price is the cheapest compared to other nonvolatile memories. However, this NAND-type flash memory has some characteristics related to data retention, and the characteristics may appear remarkably with miniaturization in a semiconductor process.

  Therefore, in a conventional semiconductor memory device, for example, as described in Patent Document 1, by switching the operation of a sense amplifier in a nonvolatile memory, a binary data recording region and a quaternary data storage are performed. By providing the area, efficient use of the memory area is realized.

  Also, in a conventional nonvolatile memory device, as described in, for example, Patent Document 2, data to be written to the nonvolatile memory from the outside is classified into binary writing and multi-value writing according to necessary data reliability. Is disclosed.

  Further, in the conventional NAND flash memory, for example, as described in Patent Document 3, the characteristics of the end of the memory cell array of the NAND flash memory can be improved by devising the precharge operation of the bit line. It is disclosed.

JP 2001-202788 A JP 2005-267676 A JP-A-2005-235260

  However, although the storage devices disclosed in Patent Documents 1 and 2 are provided with a binary storage region and a multi-value storage region according to the required reliability, a memory that is unavoidable in manufacturing the storage device. There is a problem that the nonuniformity of the shape of the memory cell in the region where the layout of the cell array is different from the repetition of the same pattern is not taken into consideration. In a region where the layout is different from the repetition of the same pattern in the memory cell array, nonuniformity of the memory cell shape is seen due to the problem of the manufacturing process, and accordingly, the performance of the memory cell is not uniform. As a result, the reliability of the memory cell in the region where the layout in the memory cell array becomes non-uniform determines the overall rate.

  In addition, in the NAND flash memory disclosed in Patent Document 3, a method for improving characteristics in a region where the layout of the memory cell array is different from the repetition of the same pattern is shown. For this purpose, special control using dummy cells is performed. It is necessary.

  In view of the above problems, an object of the present invention is to provide a storage device using a multivalued memory cell, in which the layout of the memory cell array improves the reliability in a region different from the repetition of the same pattern. And

  Furthermore, an object of the present invention is to provide a storage device that improves performance in writing in units of clusters in a storage device using multi-valued memory cells.

  In order to achieve this object, a memory device of the present invention has a plurality of memory cell blocks, and the memory cell blocks are a plurality of memory cells configured to store data of m bits (m is a natural number of 2 or more). The value memory cells are numbered from 0 to (p-1) in order from the end, and the word line of p rows (p is a natural number of 3 or more) and the numbers from 0 to (q-1) from the end. Arranged at the intersection of the assigned q columns (q is a natural number of 2 or more) bit lines, each word line has m pages from the first page to the m-th page, and the memory cell block is 0 There are n pages (n is a natural number satisfying n <m × p) to which page numbers of (n−1) are assigned, and there are at least m pages for a word line that is not at least one end. Page numbers are assigned to all of the It has a first page to which a page number is assigned to at least one word line and an mth page to which no page number is assigned.

  According to the present invention, by assigning less than m bits of information to the word line at the end of a memory cell block constituted by multi-level memory cells capable of storing m bits, the layout of the memory cell array has the same pattern. It is possible to provide a storage device that improves reliability in a region different from repetition.

  Also, the performance in writing in cluster units can be improved.

Configuration diagram of a storage device according to an embodiment of the present invention 1 is a block configuration diagram in a memory cell array according to an embodiment of the present invention. The page block diagram in the block in embodiment of this invention The figure which showed the correspondence of the word line and page number in embodiment of this invention Diagram of page address decoder in an embodiment of the present invention Sectional drawing of the bit line in embodiment of this invention The figure which shows the timing chart showing the transfer and write busy of the write data in embodiment of this invention

  Embodiments of a storage device according to the present invention will be described with reference to the drawings.

  FIG. 1 shows a configuration of a storage device of the present invention.

  Reference numeral 101 denotes an entire storage device which is a NAND type flash memory. A control circuit 102 controls the I / F with the outside of the storage device 101 and controls the inside. Reference numeral 103 denotes a data transfer circuit, which controls transfer of read / write data from the outside of the storage device 101 via the control circuit 102.

  Reference numeral 104 denotes a memory cell array composed of a plurality of multilevel memory cells for storing data. Reference numeral 105 denotes a word line driver group for driving a word line when data is written to a multi-value memory cell in the memory cell array 104, and there is one word line driver for one word line.

  A sense amplifier / write circuit group 106 reads out read data from a multi-level memory cell from the amount of current flowing through the memory cell, and supplies a potential corresponding to write data to the bit line, one for each bit line. There is a sense amplifier / write circuit.

  Reference numeral 107 denotes a block selection driver group for selecting a block at the time of writing, reading or erasing, and there is a block selection driver for each block.

  A word line timing control unit 108 controls the word line driving timing for the word line driver group.

  Reference numeral 109 denotes a page address decoder for activating a word line corresponding to a page to be driven in the word line driver group 107.

  A block decoder 110 activates a word line group corresponding to a block to be driven in the word line driver group 107. Although not shown in the figure, the block decoder 110 also informs the block selection driver group 107 of information on the word line group to be block-activated.

  Of the word line driver group 105, the word line specified by the page address decoder 109 in the block specified by the block decoder 110 is controlled according to the timing of the word line timing control 108.

  Reference numeral 111 denotes block timing control for controlling the block drive timing for the block selection driver group 107.

  FIG. 2 is a configuration diagram of the memory cell array 104. There are 1024 blocks from block 0 to block 1023. Each of these blocks is divided in parallel with the word line direction of the memory cell array 104 shown in FIG.

  A block is an erase unit of data in the storage device 101. When erasing data in units of blocks, the block selection driver 107 applies a voltage for erasing the data of the multilevel memory cell to the block in the memory cell array 104 to erase the data.

  FIG. 3 is a configuration diagram of each block included in the memory cell array 104. There are 128 pages from page 0 to page 127. Each of these pages corresponds to one word line, and one word line includes a word line corresponding to two pages and a word line corresponding to one page. Generally, the page size used in a NAND type flash memory is 2 KB, 4 KB, or 8 KB. Accordingly, assuming that the cluster size used in the file system is 16 KB, the cluster size is 2 pages, 4 pages, or 8 pages. The correspondence between word lines and bit lines will be described later.

  FIG. 4A shows the correspondence between word lines and page numbers. This corresponds to the memory cell portion of each block in FIG. Each block actually has a block selection transistor for selecting the block, but is not shown here. The block is composed of a plurality of multilevel memory cells arranged in a matrix as shown in FIG. There are word lines in the row direction and bit lines in the column direction. A multilevel memory cell is arranged at the intersection of the word line and the bit line.

  There are 65 word lines from # 0 to # 64. Since two data can be stored in each of the multivalued memory cells connected to each word line, two pages of the first page group and the second page group can correspond to one word line.

  Multi-level memory cells connected to the word line # 0 and the word line # 64 at the end of the memory cell block are used as binary memory cells in order to improve reliability. Therefore, the page corresponding to the word line # 0 and the word line # 64 is only the first page.

  The page number corresponding to each word line is as illustrated.

  FIG. 4B is a correspondence diagram between conventional word lines and page numbers. The number of word lines is 64 from # 0 to # 63. Since two data can be stored in one memory cell, the number of word lines is set to 64, which is 2 that can be stored in each memory cell. 128 pages that have been multiplied correspond. Conventionally, the same number of pages (here, two pages, the first page and the second page) are assigned to all word lines belonging to the block.

In order to assign a word line and a page as shown in FIG. 4A, the page address decoder 109 employs a decoding method that is not conventionally used. FIG. 5 shows a diagram of the page address decoder 109. Based on 7-bit information of Page Address [6: 0] that can represent 128 patterns, the output signal is provided with more than 64, which is half of 128 patterns. Here we have 65 output signals,
The output corresponding to the word line # 0 becomes “H” when the Page Address is 0.
The output corresponding to the word line # 1 becomes “H” when the Page Address is 1 or 3.
The output corresponding to the word line # 64 becomes “H” when Page Address = 126.
Decode as follows.

  By using the page address decoder as shown in FIG. 5, it is possible to reduce the number of bits that can be stored in the multi-level memory cell of the word line at the end of the memory cell array block as compared with other memory cells. . Reducing the number of bits written to the multi-level memory cell leads to improvement of the reliability of the memory cell (data retention characteristic and rewrite frequency characteristic).

  FIG. 6 is a sectional view of the physical structure of the semiconductor integrated circuit of one bit line of FIG. FIG. 6A shows the end of the bit line in one block. The hatched portion indicates the semiconductor substrate, the shaded portion indicates the diffusion region of the source and drain of the transistor, and the lattice portion indicates the wiring. There is a bit line contact portion on the right end of the figure, and a block select gate on the left side. From there, the memory cells of the word line # 0, the memory cells of the word line # 1,..., The memory cells of the word line # 64 and 65 memory cells are arranged in this order.

  FIG. 6B shows a part extracted from FIG. A memory cell in a portion surrounded by a broken line in the center of FIG. 6B is a memory cell that is not an end portion of the memory cell array. The memory cells on both sides of the memory cell surrounded by the dotted line have the same shape as the memory cell surrounded by the dotted line. In the region where such shapes are arranged, the shape of the memory cells can be finished uniformly.

  FIG. 6 (c) is a part extracted from FIG. 6 (a). A memory cell in a portion surrounded by a broken line in the center of FIG. 6C is a memory cell at the end of the memory cell array. The right side of the memory cell surrounded by the dotted line is not a memory cell but a block selection gate having a shape different from that of the memory cell. As described above, in the region where the peripheral shape is not continuous, the shape of the memory cell may be non-uniform.

  As shown in FIG. 6, the memory cells of word line # 0 and word line # 64 correspond to the end of the memory cell array, but as shown in FIG. 4, the memory cells of word line # 0 and word line # 64 are 2 High reliability can be obtained for use as a value.

  Furthermore, in this embodiment, the writing performance can be improved as compared with the conventional case. The point is also explained.

  FIG. 7 is a timing chart showing transfer of write data to the storage device 101 and write busy when writing in units of two pages, which are fixed page units, assuming writing in cluster units based on the file system. .

FIG. 7A shows a timing chart of the storage device 101 according to the present invention. FIG. 7B is a timing chart when the conventional storage device as shown in FIG. 4B is used.
“Data transfer” is a transfer period of write data to the storage device, and each frame indicates data transfer for one page. “Busy” is a busy signal output from the storage device. In a storage device using multi-valued memory cells, busy is output to the outside of the storage device during the program of the second page. In other words, no busy occurs in the program for the first page (the storage device 101 performs a write process, but the data transfer circuit 103 has a margin in writing the first page, so a write from the outside of the storage device 101 is performed. Since the data can be input), the second page data can be transferred. However, since the second page program is busy, the first page data cannot be transferred.

As a result, in the case of the present invention in which the first page in units of two pages always becomes the first page, the data transfer of the second page can be performed during the program of the first page.
This is because the first page in the unit of two pages always becomes the second page. In the conventional case, the data transfer of the first page cannot be performed during the program of the second page. Will improve.

  This is always true when the number of pages that can divide the 128 pages included in the block without any remainder, such as 4 pages, 8 pages, etc., is not limited to the unit of 2 pages.

  INDUSTRIAL APPLICABILITY The present invention is useful for a memory device with high user convenience that can improve the reliability of a memory cell using a multilevel memory cell.

DESCRIPTION OF SYMBOLS 101 Memory | storage device 102 Control circuit 103 Data transfer circuit 104 Memory cell array 105 Word line driver group 106 Sense amplifier / write circuit group 107 Block selection driver group 108 Word line timing control circuit 109 Page address decoder 110 Block decoder 111 Block timing control circuit

Claims (6)

In a storage device that can write and read data by specifying an address from the outside,
The storage device has a plurality of memory cell blocks;
The memory cell block includes:
A plurality of multi-valued memory cells configured to be able to store m-bit (m is a natural number of 2 or more) data are assigned p rows (p is 3 or more) in order from 0 to (p-1) from the end. A natural number) word line,
It is arranged at the intersection of bit lines of q columns (q is a natural number of 2 or more) assigned numbers 0 to (q-1) in order from the end.
Each of the word lines has m pages from a first page to an m-th page,
The memory cell block has n pages (n is a natural number satisfying n <m × p) assigned 0 to (n−1) page numbers,
At least one or more non-end word lines are assigned page numbers to all m pages,
A storage device comprising: a first page to which a page number is assigned to at least one of the word lines, and an m-th page to which the page number is not assigned. 2. The storage device according to claim 1, wherein the writing on the word line is performed by sequentially writing up to the m-th page while increasing the page number from the first page. The storage device according to claim 2, wherein the n is a power of two. The storage device according to claim 1, wherein the multi-level memory cell is configured by a non-volatile multi-level memory cell. The storage device according to claim 4, wherein the nonvolatile multi-level memory cell is a NAND type flash memory. 5. The storage device according to claim 4, wherein the nonvolatile multi-level memory cell stores 2-bit information in one memory cell (m = 2). 6.

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