JP2010268079A - Imaging apparatus and method for manufacturing the imaging apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an imaging apparatus or the like, which can achieve reduction of a current peak value, at electronic global shutter. <P>SOLUTION: The imaging apparatus includes TX2 drivers 21b, which apply a signal charge storage start signal, for resetting photoelectric conversion parts PD, to transistors Mtx2 while delaying the signal charge storage start signal by a prescribed delay time per row group; TX1 drivers 21a, which apply a transfer pulse, for transferring signal charges stored in the photoelectric conversion parts PD to signal charge holding parts FD, to transistors Mtx1 while delaying the transfer pulse by a prescribed delay time per row group so that temporally preceding and succeeding transfer pulses partially and temporally overlap with each other, after a prescribed exposure time elapses from the application of the signal charge storage start signal; and a signal line SEL, which drives selection transistors Mb for applying a read pulse for reading signal charges stored in the signal charge holding parts FD. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an image pickup apparatus that transports and holds a signal charge of a photoelectric conversion unit to a signal charge holding unit after an exposure time has elapsed, and a method for manufacturing the image pickup apparatus.

  An imaging device such as a digital camera or a digital video camera is equipped with an imaging device that converts an optical image into an electrical signal. In recent years, the market share of this imaging device is shifting from CCD to CMOS.

  The MOS type image pickup device such as CMOS mounted on the image pickup apparatus reads out the charges of a large number of pixels arranged in a two-dimensional manner in the pixel portion, but the exposure starts simply by reading out sequentially. The time and the exposure end time are different for each pixel (or for each line). Therefore, an example of a MOS type image pickup device configured so that the exposure start time of all the pixels can be made the same and the exposure end time of all the pixels can be made the same (that is, control by a global shutter is possible). Is described, for example, in JP-A-2001-238132. The image sensor described in the publication includes a photoelectric conversion unit such as a photodiode that generates a signal corresponding to an exposure amount, and a signal charge holding unit that temporarily holds a signal charge generated in the photoelectric conversion unit, In addition, a transistor or the like that functions as a switch when transferring or resetting charges is provided.

  An example of the configuration of the pixel of such an image sensor includes a configuration in which five transistors are provided in one pixel as shown in FIG. 3 according to the embodiment of the present invention. The configuration of the pixel 23 as shown in FIG. 3 is accumulated by the photoelectric conversion unit PD that generates a signal corresponding to the amount of incident light, the first transistor Mtx2 for resetting the photoelectric conversion unit PD, and the photoelectric conversion unit PD. The signal charge holding unit FD that receives the signal charge and holds it for a certain period of time, the second transistor Mr for resetting the signal charge holding unit FD, the photoelectric conversion unit PD, and the signal charge holding unit FD And a transistor Mtx1 functioning as a gate for transferring the signal charge accumulated by the photoelectric conversion unit PD to the signal charge holding unit FD and the signal charge held in the signal charge holding unit FD are read out And a selection transistor Mb, which is a third transistor for this purpose.

The control by the global shutter using the signal charge holding unit FD as an in-pixel memory is roughly performed as follows.
(1) The signal charge holding unit FD is reset by the transistor Mr, the reset data is sequentially scanned and read for each line by the selection transistor Mb, and is stored in a separate circuit.
(2) The photoelectric conversion units PD of all the pixels are collectively reset (global reset) by the transistor Mtx2 via the TX2 driver 21b to start accumulation of signal charges. After a predetermined exposure time has elapsed, the TX1 driver 21a The signal charges of the photoelectric conversion units PD of all the pixels are collectively transferred to the signal charge holding unit FD by the transistor Mtx1 (global transfer).
(3) The signal charge transferred to the signal charge holding unit FD is read by sequentially scanning line by line with the selection transistor Mb, and reset by subtracting the reset data stored in a separate circuit in (1). Remove noise.

  By such processing, a global shutter is realized in which exposure of all pixels is started at the same time by global reset, and exposure of all pixels is completed at the same time by global transfer.

  By the way, when performing global reset, the transistors Mtx2 of all the pixels are simultaneously turned off (collective reset), and when performing global transfer, the transistors Mtx1 of all the pixels are simultaneously turned on (collective transfer). The instantaneous current value increases as the image sensor becomes large and high in pixel. As a specific example, if a current of 200 (nA) per pixel flows, a current of 3 (A) flows instantaneously in the case of an image sensor with 15 million pixels.

  This point will be described with reference to FIG. FIG. 20 is a timing chart showing the operation of the conventional global shutter. The timing shown in FIG. 20 is based on, for example, the technique described in Japanese Patent Laid-Open No. 2001-238132 described above.

  As shown in FIG. 20A, a global reset that starts exposure of all pixels simultaneously causes the TX2 driver 21b of all lines to simultaneously input a control signal for turning off the transistor Mtx2. Is done. At this time, as shown in FIG. 20B, the voltage of the signal output from the TX2 driver 21b to the signal line TX2 shifts from a level corresponding to ON to a level corresponding to OFF with a delay time tl. This delay occurs due to the wiring resistance and the stray capacitance Ctx2 included in the transistor Mtx2 constituting an RC high cut filter, as will be described in detail in an embodiment of the present invention described later.

  After the exposure time Texp elapses from the time when the control input to the TX2 driver 21b is performed, global transfer is performed to end the exposure of all the pixels at once. As shown in FIG. 20A, in this global transfer, a control signal for turning on the transistor Mtx1 from the OFF state to the ON state is simultaneously input to the TX1 drivers 21a of all the lines, and the charge is transmitted from the photoelectric conversion unit PD. This is performed by simultaneously inputting a control signal for turning off the transistor Mtx1 after at least a transfer time ta required for transfer to the charge holding unit FD. As in the case of the signal output to the signal line TX2, the voltage of the signal output from the TX1 driver 21a to the signal line TX1 shifts from the level corresponding to OFF to the level corresponding to ON with a delay time tl. (Refer to FIG. 20B) (It is almost the same when the level is changed from ON to OFF). Therefore, in order to maintain the level corresponding to ON for the transfer time ta described above, the pulse flowing through the signal line TX1 needs to continue for at least the time (tl + ta).

  Then, as shown in FIG. 20C, the total value (composite current) of the currents flowing through the signal lines TX2 of all lines at the time of the global reset and the total value (composite values) of the currents flowing through the signal lines TX1 of all the lines at the time of global transfer. The current is a considerably large value (for example, 3 (A) as described above) in the fluctuation portion of the voltage waveform due to the above-described simultaneous application of signals.

  For this reason, in the image pickup device as described in the above-mentioned Japanese Patent Application Laid-Open No. 2001-238132, the wiring in the image pickup device is thickened to prevent a voltage drop, or the power supply capability of the image pickup board on which the image pickup device is mounted is increased. It is necessary to do. However, in the former case, it is necessary to increase the size and the number of layers of the image pickup device itself, and in the latter case, a powerful power supply circuit is required, which leads to an increase in the size of the image pickup apparatus.

  Since the voltage is unstable (the rise and fall of the voltage are unstable) while the delay time tl described above has elapsed, the operation may vary depending on the line position (or the pixel position). Alternatively, uneven exposure may occur depending on the pixel position. Therefore, in order to be able to ignore the exposure unevenness due to the delay time tl, it is considered necessary to secure the exposure time Texp about 20 times (for example, 100 times) the delay time tl. Here, assuming that the delay time tl is 2 (μsec) (however, the value of the delay time tl is a circuit resistance such as a wiring resistance of the imaging substrate, a wiring resistance in the imaging device, a transistor in the imaging device, or the like). The shortest exposure time Texp at which exposure unevenness can be ignored is 200 (μsec) = 0.2 (msec), and the shutter speed corresponding to this exposure time is 1/5000 (seconds). ). Therefore, even with an electronic global shutter, it is understood that an unlimited high-speed shutter operation cannot be performed, and there is an upper limit shutter speed.

  On the other hand, Japanese Patent Application Laid-Open No. 2006-203775 applies a driving pulse while resetting the photoelectric conversion unit and reading out pixel data from the photoelectric conversion unit with a time difference for each line in accordance with the operation of the mechanical shutter. (That is, performing a high-speed rolling shutter) and then reading out pixel data from the signal charge holding unit over a time longer than the shutter operation time. This point will be described with reference to FIG. FIG. 21 is a timing chart showing an operation at the time of pixel data transfer by a high-speed rolling shutter according to a conventional mechanical shutter operation.

  As shown in FIG. 21A, the TX1 driver receives a control signal for each line in accordance with the mechanical shutter operation. In the example shown in FIG. 21, there is no overlapping portion in each pulse signal input as a control signal. At this time as well, a delay due to the stray capacitance of the image sensor or the like occurs, so that the voltage waveform of the TX1 signal has a slightly smooth edge as shown in FIG. Further, the peak of the current waveform of the TX1 signal is generated at the fluctuation portion in the voltage waveform as shown in FIG.

  As described above, since the rolling shutter does not apply signals simultaneously even at a relatively high speed, the total value (combined current) of the currents flowing through the signal lines TX1 of all lines during pixel data transfer is as shown in FIG. As shown in (D), a relatively low value (in this example, the peak value of the current of one line shown in FIG. 21C and the peak value of the combined current shown in FIG. 21D are substantially the same). Is in the range.

  When such an operation is performed, a current that flows instantaneously is smaller than that in the case of performing the simultaneous operation as described in JP-A-2001-238132, but the operation of the last line from the operation timing of the first line is performed. Elapsed time to timing becomes longer. As a specific example, assuming that the timing deviation between lines is 5 (μsec) and the total number of lines on the image sensor is 3000 lines, 5 (μsec) × (3000-1) ≈15 (msec), that is, 1 The electronic shutter curtain speed is about 60 seconds (note that the mechanical shutter is of a high-speed type and the curtain speed is 3 (msec), that is, about 1/300 seconds).

  Thus, with the technique described in Japanese Patent Application Laid-Open No. 2006-203775, it is difficult to increase the speed to the extent that it can be called a global shutter. When the exposure timing varies depending on the position, distortion that occurs in the image portion of the moving object is likely to occur. Here, it is ideal that the curtain speed that can be called a global shutter is of course that all lines are simultaneously, but the maximum speed of the current focal plane shutter is about 1/2000 to 1/8000 seconds (for example, 1/3000 seconds). ) Can be used as a guide. Therefore, when such a curtain speed can be realized, it is called a global shutter. The publication also describes an embodiment in which the photoelectric conversion units of a plurality of lines are simultaneously reset or pixel data is transferred from the photoelectric conversion units in order to cope with such an increase in the curtain speed. . Specifically, when the technique described in the publication is intended to support a shutter speed of 1/3000 seconds (about 0.3 (msec) = 300 (μsec)), 300 (μsec) / 5 (μsec) ) = 60, 3000 lines / 60 = 50 lines, and it is necessary to process 50 lines simultaneously. That is, assuming that the peak value of the combined current when all lines are processed simultaneously is 3 (A), the peak value of the combined current when simultaneous processing is performed for every 50 lines is 3/60 = 0.05 (A ) = 50 (mA). Although the current peak value is lower than in the case of all lines at the same time, and voltage fluctuations are somewhat solved, it is still a high value of 50 times the current peak value of one line, so it is not a sufficient solution. .

JP 2001-238132 A JP 2006-203775 A

  In the conventional technology as described above, it is impossible to achieve both the realization of the electronic global shutter and the reduction of the current peak value at the time of the electronic global shutter, resulting in an increase in the size of the imaging apparatus.

  The present invention has been made in view of the above circumstances, and an object thereof is to provide an imaging apparatus and a manufacturing method of the imaging apparatus that can reduce a current peak value at the time of an electronic global shutter.

  In order to achieve the above object, an imaging apparatus according to an aspect of the present invention includes a photoelectric conversion unit that generates and stores a signal according to an incident light amount, a first transistor for resetting the photoelectric conversion unit, A light-shielded signal charge holding unit for receiving a signal charge accumulated by the photoelectric conversion unit and holding it for a certain period of time, a second transistor for resetting the signal charge holding unit, the photoelectric conversion unit and the signal charge A gate unit for transferring the signal charge accumulated between the photoelectric conversion unit and the signal charge holding unit to the signal charge holding unit; and a first unit for reading the signal charge held in the signal charge holding unit. And a pixel portion in which pixels having three transistors are two-dimensionally arranged in a row direction and a column direction, and resetting the photoelectric conversion portion to start accumulation of signal charges in the photoelectric conversion portion The signal charge accumulation start signal is applied to each row group composed of one or more rows, and for each row belonging to the same row group, a different row group is predetermined for each row group. A signal charge accumulation start signal control unit for applying while delaying each delay time, and after the predetermined exposure time has elapsed since the application of the signal charge accumulation start signal, the photoelectric conversion unit is driven by driving the gate unit A transfer pulse for transferring the signal charge accumulated by the signal charge holding unit is applied to each row group, and each row belonging to the same row group is simultaneously and temporally A transfer pulse controller for applying the pulse by delaying the predetermined delay time so that some of the transfer pulses overlap each other in time, and driving the third transistor to hold the signal charge It is obtained by anda read pulse controller for applying a read pulse for reading signal charges accumulated in the.

  An image pickup apparatus manufacturing method according to another aspect of the present invention is the image pickup apparatus further comprising a reset voltage read control unit that reads a reset voltage when the signal charge holding unit is reset, In this manufacturing method, when the reset current when the photoelectric conversion unit is reset by the signal charge accumulation start signal control unit is equal to or less than a predetermined value, reading of the reset voltage by the reset voltage read control unit for all pixels is completed. A first sequence for starting signal charge accumulation by the signal charge accumulation start signal control unit later, and by the signal charge accumulation start signal control unit before the reset voltage read control unit finishes reading the reset voltage. A second sequence for starting signal charge accumulation and a second imaging program including both Set in the imaging apparatus, when the reset current is greater than the predetermined value is a method for setting the first imaging program that does not include the second sequence comprises a first sequence on the imaging device.

  According to the imaging device and the manufacturing method of the imaging device of the present invention, it is possible to reduce the current peak value during the electronic global shutter.

1 is a block diagram illustrating a configuration of an imaging apparatus according to Embodiment 1 of the present invention. FIG. 3 is a diagram illustrating a more detailed configuration of an imaging unit in the first embodiment. FIG. 3 is a circuit diagram illustrating in more detail a configuration example of a pixel in the pixel portion of the first embodiment. FIG. 3 is a diagram illustrating a configuration of a pixel in the semiconductor substrate of Embodiment 1 in a substrate thickness direction. 6 is a timing chart showing a first sequence of global shutter operation in the imaging apparatus according to the first embodiment. 6 is a timing chart showing a second sequence of global shutter operation in the imaging apparatus according to the first embodiment. 7 is a timing chart showing, in an enlarged manner, the portion of reference symbol ENL1 related to the signal charge accumulation start signal in FIG. 5 or FIG. In the said Embodiment 1, the timing chart which expands and shows in detail the part of the code | symbol ENL2 which concerns on the transfer pulse in FIG. 5 or FIG. FIG. 3 is a circuit diagram showing an equivalent circuit regarding resistance and stray capacitance of a circuit portion including the signal line TX1 and the transistor Mtx1 or the signal line TX2 and the transistor Mtx2 in the first embodiment. FIG. 3 is a circuit diagram showing an equivalent circuit regarding inductance and stray capacitance of a circuit portion from a power supply to a TX1 or TX2 driver in the first embodiment. In the said Embodiment 1, the timing chart for demonstrating in detail the mode of the delay with respect to a response. In the first embodiment, the maximum value of the combined inrush current when the predetermined delay time for delaying the signal charge accumulation start signal and the transfer pulse is set to the response time tk due to the circuit configuration shown in FIG. Figure for. The figure which shows the mode of the peak which added the TX1 driver supply current regarding m lines in the said Embodiment 1, when the number of rows contained in one row group is m. 5 is a timing chart showing a state when the electronic shutter operation is performed at the maximum strobe tuning speed that can be achieved when the predetermined delay time is set to the response time tk in the first embodiment. 5 is a flowchart showing a flow of processing in a manufacturing method of an imaging apparatus that designs what imaging program is set according to the type of imaging element mounted on the imaging apparatus in the first embodiment. 4 is a flowchart illustrating a first imaging program set in the imaging apparatus in the first embodiment. 4 is a flowchart illustrating a second imaging program set in the imaging apparatus in the first embodiment. The circuit diagram which shows the structural example of the pixel in the pixel part of Embodiment 2 of this invention in detail. 6 is a timing chart showing a sequence of a global shutter operation in the imaging apparatus according to the second embodiment. 9 is a timing chart showing the operation of a conventional global shutter. 9 is a timing chart showing an operation at the time of pixel data transfer by a high-speed rolling shutter according to a conventional mechanical shutter operation.

Embodiments of the present invention will be described below with reference to the drawings.
[Embodiment 1]

  1 to 17 show the first embodiment of the present invention, and FIG. 1 is a block diagram showing the configuration of the imaging apparatus.

  As shown in FIG. 1, the imaging apparatus includes a photographing optical system 1 including a zoom lens 2, a diaphragm 3, and a focus lens 4, a lens driving unit 5, an imaging unit 6, an AF processing unit 7, and image processing. A display unit 9 including a display unit 8, a rear display unit 10 and an electronic viewfinder (EVF) 11, a camera operation unit 13, and a camera control unit 14. The imaging apparatus also includes a power supply 15 as shown in FIG. Although the memory card 12 is also illustrated in FIG. 1, the memory card 12 is configured to be detachable from the imaging apparatus, and thus may not have a configuration unique to the imaging apparatus.

  The photographing optical system 1 forms an optical image of a subject on a pixel unit 22 (see FIG. 2) of an image sensor included in the image capturing unit 6.

  The zoom lens 2 is for zooming by changing the focal length of the photographing optical system 1.

  The diaphragm 3 is for adjusting the brightness of the subject optical image formed on the imaging unit 6 by defining the passage range of the subject light flux passing through the photographing optical system 1.

  The focus lens 4 is for performing focusing by adjusting the focal position (focus position) of the photographing optical system 1.

  The lens driving unit 5 is for driving the photographing optical system 1. That is, the lens driving unit 5 drives the diaphragm 3 and the focus lens 4 included in the photographing optical system 1 based on the control of the camera control unit 14 that receives the AF evaluation value from the AF processing unit 7, and The object image to be formed has an appropriate amount of light and is focused. Further, the lens driving unit 5 outputs lens driving information such as a lens position and an aperture amount to the camera control unit 14.

  The imaging unit 6 photoelectrically converts the optical image of the subject imaged by the photographing optical system 1 and outputs it as an image signal.

  The AF processing unit 7 calculates an AF evaluation value based on the image signal output from the imaging unit 6 and outputs the AF evaluation value to the camera control unit 14. That is, this imaging apparatus is configured to perform autofocus by contrast AF (mountain climbing AF).

  The image processing unit 8 performs various image processing on the image signal output from the imaging unit 6.

  The display unit 9 displays an image based on a signal image-processed for display by the image processing unit 8. The display unit 9 can perform live view (LV) display and still image reproduction display. The rear display unit 10 of the display unit 9 is arranged on the rear side of the imaging apparatus main body, and is configured so that a photographer can directly view. Further, the EVF 11 is provided as a finder unit on the upper part of the image pickup apparatus, and is configured to allow a photographer to enlarge and observe through an eyepiece lens or the like.

  The memory card 12 is a recording medium for storing a signal image-processed for recording by the image processing unit 8.

  The camera operation unit 13 is for performing various operation inputs to the imaging apparatus. The camera operation unit 13 includes operation members such as a power switch for turning on / off the power of the imaging apparatus and a release button including a two-stage push button for inputting an instruction for still image shooting.

  The camera control unit 14 is based on the lens drive information from the lens drive unit 5, the AF evaluation value from the AF processing unit 7, the operation input from the camera operation unit 13, and the like. The image pickup apparatus including the unit 8 and the memory card 12 is controlled. Further, the camera control unit 14 functions as an exposure time setting unit, performs AE calculation based on a signal from the imaging unit 6 (or based on photometric data from a photometric circuit not shown), and an electronic shutter in the imaging unit 6. The shutter speed (exposure time) and the aperture value of the aperture 3 are set.

  Next, FIG. 2 is a diagram illustrating a more detailed configuration of the imaging unit 6.

  The imaging unit 6 includes a vertical scanning circuit 21, a pixel unit 22, a horizontal scanning circuit 24, and an A / D conversion unit 25.

  The pixel unit 22 has a plurality of pixels 23 arranged two-dimensionally in the row direction and the column direction, and performs photoelectric conversion for each pixel 23 to generate signal charges (pixel data).

  The vertical scanning circuit 21 applies various signals to the pixels arranged in the pixel unit 22 in units of rows (lines). Signals from the pixels in the row selected by the vertical scanning circuit 21 are output to a vertical transfer line VTL (see FIG. 3) provided for each column. More detailed configurations of the vertical scanning circuit 21 and the pixel unit 22 will be described later with reference to FIG.

  The horizontal scanning circuit 24 takes in signals of pixels for one row selected by the vertical scanning circuit 21 and transferred from the vertical transfer line VTL, and time-series the signals of the pixels in that row in the order of the horizontal pixel arrangement. Is output.

  The A / D converter 25 converts an analog image signal output from the horizontal scanning circuit 24 into a digital image signal.

  Next, FIG. 3 is a circuit diagram illustrating a configuration example of the pixel 23 in the pixel unit 22 in more detail. FIG. 3 shows an example of a pixel 23 configured in, for example, a MOS type solid-state imaging device.

  In FIG. 3, PD (photodiode) is a photoelectric conversion unit that generates a signal according to the amount of incident light, and FD (floating diffusion) receives signal charges accumulated by the photoelectric conversion unit PD and holds them for a certain period of time. This is a signal charge holding portion that is shielded from light.

  Mtx2 is a transistor (first transistor) that functions as a first reset unit that resets the photoelectric conversion unit PD, and is connected to the current source VDD and to the signal line TX2 for applying the signal charge accumulation start signal. Has been. The transistor Mtx2 has a stray capacitance, and this stray capacitance is clearly shown as Ctx2 in FIG.

  Mtx1 is a transistor which is disposed between the photoelectric conversion unit PD and the signal charge holding unit FD and functions as a gate unit for transferring the signal charge accumulated by the photoelectric conversion unit PD to the signal charge holding unit FD. Yes, and connected to a signal line TX1 for applying a transfer pulse. This transistor Mtx1 also has a stray capacitance, and this stray capacitance is clearly shown as Ctx1 in FIG.

  Ma is an amplifying transistor that functions as an amplifying unit, and forms a source follower amplifier with the current source VDD. The signal charge held in the signal charge holding unit FD is amplified by the amplifying transistor Ma, and read out to the vertical transfer line VTL via the selection transistor Mb which is the third transistor functioning as the signal charge reading unit. The selection transistor Mb is connected to a signal line SEL for applying a read pulse.

  Mr is a transistor (second transistor) that functions as a second reset unit that resets the signal charge holding unit FD and the input unit of the amplification transistor Ma, and is connected to a signal line RES for applying an FD reset pulse. . Note that if the application of the transfer pulse to the transistor Mtx1 and the application of the FD reset pulse to the transistor Mr are performed at the same time, not only the signal charge holding unit FD can be reset, but also the photoelectric conversion unit The PD can be reset. Therefore, the combination of the transistor Mtx1 and the transistor Mr can function as a first reset unit for the photoelectric conversion unit PD.

  Here, the TX1 driver 21a in the vertical scanning circuit 21 is connected to the signal line TX1 of each line. Similarly, the TX2 driver 21b in the vertical scanning circuit 21 is connected to the signal line TX2 of each line.

  The TX2 driver 21b resets the photoelectric conversion unit PD by applying a signal charge accumulation start signal that changes the transistor Mtx2 of each pixel 23 on the line from on to off according to the timing of each line, thereby photoelectrically This is for starting the accumulation of signal charges in the conversion unit PD.

  That is, the vertical scanning circuit 21 functions as a signal charge accumulation start signal control unit, controls the TX2 driver 21b for each line, and simultaneously outputs the signal charge accumulation start signal for each row group including one or more rows. In addition to the application, the signal charge accumulation start signal applied for each row group is applied while being delayed by a predetermined delay time.

  The TX1 driver 21a transfers the signal charge accumulated by the photoelectric conversion unit PD to the signal charge holding unit FD at a timing after a predetermined exposure time has elapsed after the signal charge accumulation start signal is applied for each line. The transfer pulse is applied to the transistor Mtx1 of each pixel 23 on the line.

  That is, the vertical scanning circuit 21 also functions as a transfer pulse control unit, controls the TX1 driver 21a for each line, and transfers a part of the transfer pulse that is simultaneously and temporally shifted for each row group. Are applied while being delayed by a predetermined delay time so as to overlap each other in time.

  The functions of the vertical scanning circuit 21 as the signal charge accumulation start signal control unit and the transfer pulse control unit will be described in detail later with reference to FIGS.

  The vertical scanning circuit 21 further functions as a read pulse control unit, and drives the selection transistor Mb to apply a read pulse for reading the signal charge held in the signal charge holding unit FD. Yes.

  In addition, the vertical scanning circuit 21 further functions as a reset voltage read control unit, and applies a reset pulse from the signal line RES to the transistor Mr, and further applies a read pulse from the signal line SEL to the selection transistor Mb. Thus, the reset voltage (reset data) when the signal charge holding unit FD is reset is read out.

  Next, FIG. 4 is a diagram showing the configuration of the pixel 23 in the semiconductor substrate in the substrate thickness direction.

  In the example shown in FIG. 4, a P-type substrate is used as the semiconductor substrate.

  The photoelectric conversion part PD is formed as an n− region, and a p region is formed on the wiring layer side. An electrode is formed on the substrate surface adjacent to the p region, and the signal line TX2 is connected to the electrode. Thus, since the photoelectric conversion part PD is formed as a buried type, it is possible to reduce dark current. Further, the substrate surface other than the portion corresponding to the photoelectric conversion portion PD is shielded from light by a light shielding film having a predetermined light shielding performance.

  The signal charge holding unit FD is formed as an n + region at a predetermined interval from the photoelectric conversion unit PD. This n + region is connected to the amplification transistor Ma side. As described above, since the signal charge holding unit FD is directly connected to the wiring layer, it is difficult to reduce the dark current.

  Further, a gate electrode is formed on the substrate surface between the photoelectric conversion unit PD and the signal charge holding unit FD, and the transistor Mtx1 is configured. The gate electrode of the transistor Mtx1 is connected to the signal line TX1.

  Further, another n + region is formed at a position spaced apart from the n + region constituting the signal charge holding portion FD, and the current source VDD is connected to the latter n + region. A gate electrode is formed on the surface of the substrate between these two n + regions, thereby forming a transistor Mr. The gate electrode of the transistor Mr is connected to the signal line RES.

  Next, FIG. 5 is a timing chart showing a first sequence of global shutter operation in the imaging apparatus.

  When the release button of the camera operation unit 13 is pressed and a release signal is input to the camera control unit 14, this global shutter operation is started based on the control of the camera control unit 14.

  Then, before performing signal charge accumulation by the global shutter operation, first, the signal charge holding unit FD is reset and reset noise is read in the reset data reading period.

  That is, first, a reset pulse is applied from the signal line RES to the transistors Mr of the pixels 23 arranged in the first row of the pixel unit 22 to reset the signal charge holding unit FD in the first row. Further, by applying a read pulse from the signal line SEL to the selection transistor Mb of each pixel 23 arranged in the first row of the pixel unit 22, the reset noise (signal from the signal charge holding unit FD in the first row is set. The reset voltage when the charge holding portion FD is reset is read out. By sequentially performing such an operation from the first row of the pixel unit 22 to the Vth row (here, the number of horizontal lines of the pixel unit 22 is V, the last row), Read reset noise of all pixels. The reset noise read here is output to the image processing unit 8 through the horizontal scanning circuit 24 and the A / D conversion unit 25 in this order.

  Next, during this global shutter operation, a signal charge accumulation start signal is actually applied sequentially to the transistors Mtx2 of all the lines via the signal line TX2 while maintaining a synchronism that can be called a global shutter. By switching from on to off, the accumulation of charges in the photoelectric conversion unit PD, that is, the start of exposure is performed almost simultaneously for all the pixels.

  More specifically, at the time of the global shutter operation, each row group is connected to the transistor Mtx2 of the row group including one or more rows (therefore, the row group may be one row) via the signal line TX2. The signal charge accumulation start signal is applied while being delayed by a predetermined delay time. At this time, the total delay time of all the row groups is controlled so as to maintain simultaneity that can be called a global shutter (for example, 1/3000 (seconds) or less). Note that the exposure start portion indicated by the symbol ENL1 in FIG. 5 will be described in detail later with reference to FIG.

  Thereafter, when a predetermined exposure time (this exposure time (exposure period) corresponds to the shutter speed determined by the AE calculation) has elapsed after the start of exposure for each row group, each row is transmitted via the signal line TX1. By applying a transfer pulse to the group of transistors Mtx1, the charges accumulated in the photoelectric conversion unit PD are transferred to the signal charge holding unit FD, that is, the exposure is finished for each row group. Since the start of exposure is sequential while maintaining the simultaneity that can be called a global shutter as described above, the concurrency that can also be called a global shutter is the same as the end of exposure after a predetermined exposure time has passed. It can be said that it is sequential while keeping Note that this exposure end portion indicated by reference numeral ENL2 in FIG. 5 will be described in detail later with reference to FIG.

  Thereafter, the pixel data reading period starts, and the signal charges held in the signal charge holding unit FD are transferred from the first row to the Vth row (the last row) through the amplification transistor Ma and the selection transistor Mb. To the vertical transfer line VTL in line units.

  Next, FIG. 6 is a timing chart showing a second sequence of the global shutter operation in the imaging apparatus.

  The second sequence shown in FIG. 6 is such that the reset data read period overlaps with the exposure period as much as possible with respect to the first sequence shown in FIG. Accordingly, since the time from reading the reset data to reading the pixel data can be shortened as compared with the first sequence shown in FIG. 5, noise generated due to the dark current can be reduced. It becomes possible.

  Here, even while the signal charge is accumulated in the photoelectric conversion unit PD after the exposure period is started, the transistor Mtx1 is off. Therefore, even if the signal charge holding unit FD is reset, the photoelectric conversion unit PD It does not affect the signal charge. Therefore, by operating the transistor Mr and the selection transistor Mb during this exposure period, it is possible to read out the reset data simultaneously with the exposure.

  In the example shown in FIG. 6, since the reset data reading period is longer than the exposure period, the second half of the reset data reading period overlaps with the exposure period, but is the exposure period the same as the reset data reading period? Alternatively, in the case of a longer period, it is possible to include the entire reset data reading period within the exposure period.

  Further, as shown in FIG. 6, in the case where the exposure period start timing overlaps the reset data read period (when the portion indicated by symbol PA occurs), the signal charge accumulation start signal applied to the signal line TX2 Although attention is required for the control, this will be described later (see step S2 in FIG. 15).

  FIG. 7 is a timing chart showing an enlarged portion of the symbol ENL1 related to the signal charge accumulation start signal in FIG. 5 or FIG. 6, and FIG. 8 is a timing chart showing the details of the symbol ENL2 related to the transfer pulse in FIG. It is a timing chart which expands and shows a part in detail and classifying. 7 and 8, only the signals relating to some row groups are described, it is assumed that similar signal waveforms are generated for the undescribed row groups.

  The control signal input to the TX2 driver 21b of the vertical scanning circuit 21 is a stepped voltage waveform signal for causing the transistor Mtx2 to transition from on to off as shown in FIG. As described above, this control signal is applied to each row belonging to the same row group at the same time, and with respect to different row groups, so as to be delayed by a predetermined delay time for each row group. Note that how to determine the delay time will be described later with reference to FIGS.

  On the other hand, in the voltage waveform of the signal output from the TX2 driver 21b, a response delay occurs due to the wiring resistance of the signal line TX2 and the stray capacitance of the transistor Mtx2 (see also FIG. 9 to be described later), and the edge becomes rounded. ) As shown.

  Then, a current waveform of a signal output from the TX2 driver 21b to satisfy the stray capacitance of the transistor Mtx2 is as shown in FIG.

  In addition, the combined current waveform when the signals output from the TX2 driver 21b are added for all the rows is as shown in FIG. That is, it can be seen that when the delay time as shown in FIG. 7 is shifted, the peak value of the combined current related to all the rows is not so much increased than the peak value of the current related to the single row.

  Similarly, the control signal input to the TX1 driver 21a of the vertical scanning circuit 21 causes the transistor Mtx1 to transition from off to on as shown in FIG. 8A, and then from on to off after a predetermined time has elapsed. This is a rectangular pulse voltage waveform signal having a width for state transition. As described above, this control signal is predetermined so that a part of transfer pulses that are temporally adjacent to each other belong to the same row group at the same time. It is applied while delaying each delay time. This delay time is basically the same as the delay time related to the TX2 driver 21b described with reference to FIG. 7 because the exposure time of all the rows needs to be the same.

  On the other hand, in the voltage waveform of the signal output from the TX1 driver 21a, a response delay occurs due to the wiring resistance of the signal line TX1 and the stray capacitance of the transistor Mtx1 (see also FIG. 9 described later), and the edge becomes rounded. ) As shown.

  Then, the current waveform of the signal output from the TX1 driver 21a to satisfy the stray capacitance of the transistor Mtx1 is as shown in FIG. This current waveform is a waveform having one maximum peak and one minimum peak corresponding to each of the transfer pulse having a rising portion and a falling portion.

  In addition, the combined current waveform when the signals output from the TX1 driver 21a are added for all the rows is as shown in FIG. That is, it can be seen that when the delay time is shifted as shown in FIG. 8, the peak value of the combined current relating to all the rows is not so much increased than the peak value of the current relating to the single row.

  Next, FIG. 9 is a circuit diagram showing an equivalent circuit regarding the resistance and stray capacitance of the circuit portion including the signal line TX1 and the transistor Mtx1, or the signal line TX2 and the transistor Mtx2, and FIG. 10 is a circuit from the power supply 15 to the TX1 or TX2 driver. FIG. 11 is a timing chart for explaining in more detail the state of delay with respect to the response.

  The signal line TX1, the signal line branched from the signal line TX1 to the transistor Mtx1, and the like have wiring resistance, and the wiring resistance obtained by combining these for one row is shown as R in FIG. Further, the transistor Mtx1 has a stray capacitance Ctx1, and the combined stray capacitance of all the transistors Mtx1 for one row is shown as C in FIG.

  Similarly, the signal line TX2, the signal line branched from the signal line TX2 to the transistor Mtx2, and the like have wiring resistance, and the wiring resistance obtained by combining these for one row is shown as R in FIG. Further, the transistor Mtx2 has a stray capacitance Ctx2, and the combined stray capacitance of all the transistors Mtx2 for one row is shown as C in FIG.

  The wiring resistance related to the signal line TX1 and the wiring resistance related to the signal line TX2 may be strictly different from each other, and the stray capacitance Ctx1 and the stray capacitance Ctx2 may be strictly different from each other. Are the same.

  The circuit configuration shown in FIG. 9 is a so-called RC low-pass filter (RC high cut filter). In this circuit configuration, for example, it is assumed that the wiring resistance R is 5 (kΩ) and the stray capacitances Ctx1 and Ctx2 are 5 (fF). When the number of pixels arranged on one line is, for example, 4000 pixels, the combined stray capacitance C is 20 (pF). Therefore, it can be seen that the time constant indicating the degree of time delay with respect to the impulse response is RC = 100 (nsec), and that the response delay occurs for this amount of time.

  Furthermore, an equivalent circuit regarding the inductance and stray capacitance of the circuit portion from the power supply 15 to the TX1 or TX2 driver is as shown in FIG. 10, for example. In FIG. 10, the inductance is indicated by L and the stray capacitance is indicated by C. The circuit configuration shown in FIG. 10 is a so-called LC low pass filter (LC high cut filter).

  Then, as outlined with reference to FIG. 8 and the like, when a rectangular voltage waveform control signal (FIG. 11A) is input to the TX1 driver 21a of the vertical scanning circuit 21, the TX1 driver 21a The waveform of the output transfer pulse (FIG. 11B) has a characteristic having the response time tk of about 100 (nsec) described above. Note that, in order to transfer the signal charge of the photoelectric conversion unit PD to the signal charge holding unit FD, for example, a transfer time ta of about 5 (μsec) is required, but because 100 (nsec) << 5 (μsec). Tk << ta is satisfied.

  Further, the current waveform of the signal output from the TX1 driver 21a is as shown in FIG.

  The current waveform supplied from the power source 15 to the TX1 driver 21a to output the current waveform as shown in FIG. 11C is a graph showing the characteristics of the LC low-pass filter as shown in FIG. As shown in FIG. 11 (D), the waveform first has a peak and then decays. In FIG. 11, the peak value of the current supplied to the TX1 driver 21a for one row is IL, and the effective current supply period for one peak is tp.

  Next, FIG. 12 illustrates the maximum value of the combined inrush current when the predetermined delay time for delaying the signal charge accumulation start signal and the transfer pulse is the response time tk due to the circuit configuration shown in FIG. It is a figure for doing.

  The peak value of the current supplied to the TX1 driver 21a is IL as shown in FIG. Further, as shown in FIG. 11B, the delay time tk starts output from the TX1 and TX2 drivers 21a and 21b and reaches a predetermined voltage at which the on / off state transition of the transistors Mtx1 and Mtx2 is stabilized. It is time until. On the other hand, the effective current supply period tp shown in FIG. 11D further includes a time during which the current value attenuates after reaching the predetermined voltage. Therefore, it is considered that tk <tp, and as shown in FIG. 12, when the delay time is set to the response time tk, each current peak is overlapped somewhat. Therefore, the combined inrush current Iin obtained by adding the TX1 driver supply currents for all lines is a value (IL <Iin) larger than the peak value IL.

  Note that FIG. 12 illustrates the case where one row group is configured by one row, but in the case where it is configured by a plurality of rows, one peak is as illustrated in FIG. FIG. 13 is a diagram illustrating a peak state obtained by adding TX1 driver supply currents regarding m lines when the number of rows included in one row group is m.

  As shown in the figure, the effective current supply period tp is the same as that in one row, but the peak value is m times as much as mIL. Therefore, when processing is performed for each row group composed of m rows, the peak value IL of one peak and the combined inrush current value Iin in FIG.

  FIG. 14 is a timing chart showing a state in which the electronic shutter operation is performed at the maximum strobe tuning speed that can be achieved when the predetermined delay time is set to the response time tk. FIG. 14 shows an example in which the predetermined delay time is set to the response time tk and one row group is composed of one row, as in the case shown in FIG.

At this time, the time required to apply the signal charge accumulation start signal to all the lines (first to V lines) in order to function as the front curtain is tk × (V−1). Similarly, the time required to apply the transfer pulse to all lines in order to function as the rear curtain is tk × (V−1). Therefore, the exposure time Texp corresponding to the maximum shutter speed at which the flash can be tuned is tk × (V−1). As described above, for example, 100 (nsec) can be considered as a specific value of tk, and when the total number of lines V is, for example, 3000 lines,
Texp = tk × (V−1) = 100 (nsec) × 2999
≒ 0.3 (msec) ≒ 1/3300 (sec)
Thus, it can be seen that a high-speed shutter that can be substantially called a global shutter can be realized.

  Next, FIG. 15 is a flowchart showing a flow of processing in the manufacturing method of the imaging apparatus that designs what imaging program is set according to the type of the imaging element mounted on the imaging apparatus.

  When this processing is started, first, the combined stray capacitance C is obtained by multiplying the stray capacitances Ctx1 and Ctx2 of the transistors Mtx1 and Mtx2 for one line by the number of pixels for one line, and further the wiring resistance of the signal lines TX1 and TX2 A time constant RC of an RC high cut filter (RC low pass filter) as shown in FIG. 9 is calculated using R, and this time constant RC is set as a delay time tk in one line (step S1).

  Subsequently, in the case where the start timing of the exposure period overlaps with the reset data reading period as shown by the symbol PA in FIG. 6, the reading of the reset data from the signal charge holding unit FD is not affected. A maximum value Iinmax (A) of the combined inrush current obtained by adding the TX2 driver supply current for all lines is set according to the type of the image sensor mounted in the image pickup apparatus (step S2).

  Next, for example, when a control signal as shown in FIG. 11A is input to the TX1 driver 21a, based on the delay time tk calculated in step S1, the output voltage waveform from the TX1 driver 21a is as shown in FIG. B) The output current waveforms are as shown in FIG. On the other hand, since the LC high cut filter (LC low pass filter) as shown in FIG. 10 is configured by the circuit such as the power supply 15 and the vertical scanning circuit 21, it is shown in FIG. 11C based on the time constant LC. It can be seen that the input current waveform to the TX1 driver 21a from which such an output current waveform can be obtained is as shown in FIG. Accordingly, the peak value IL (A) of the input current in one line as shown in FIG. 11D is set (step S3).

Then, the maximum value Iinmax (A) of the combined inrush current obtained in step S2 is divided by the peak value IL (A) of the input current in one line obtained in step S3, and the result is rounded down. That is,
m = [Iinmax / IL]
Thus, the integer m is obtained (step S4). Here, the symbol [] in the mathematical expression in step S4 represents a floor function.

  In a typical example in which the delay time tk and the effective current supply period tp for one peak have a relationship as shown in FIG. 11, the combined inrush current value Iin is as shown in FIG. Although it is larger than the peak value IL of the input current, it is smaller than twice the peak value IL of the input current in one line. Therefore, when the driving time for each line is delayed by the delay time tk, the combined inrush current value Iin can be made smaller than the maximum value Iinmax when the integer m calculated in step S4 is 2 or more. It can be used as such an index. That is, when m is 2 or more, both the imaging by the first sequence shown in FIG. 5 and the imaging by the second sequence shown in FIG. 6 can be executed, but when m is 0 or 1 Only the imaging in the first sequence shown in FIG. 5 can be executed, and the imaging in the second sequence shown in FIG. 6 cannot be executed.

  Therefore, it is next determined whether or not the integer m is 1 or 0 (step S5).

  If it is determined in this step S5 that m is 1 or 0, a first imaging program including only a first sequence as shown in FIG. 16 described later is set in the imaging device (step S6). On the other hand, when it is determined that m is 2 or more, a second imaging program including both a first sequence and a second sequence as shown in FIG. (Step S7), this process is terminated.

  Next, FIG. 16 is a flowchart illustrating a first imaging program set in the imaging apparatus.

  When this process is started, first, the aspect ratio of the photographed image is set (step S11). Here, for example, the aspect ratio of the pixel portion 22 is 4: 3 (the number of horizontal lines is V2), and the pixel data of the upper end portion and the lower end portion of the pixel portion 22 are excluded to further increase the 16: 9. The aspect ratio (the number of horizontal lines is V1, where V1 <V2) can be set.

  Based on the aspect ratio set in step S11, V1 or V2 is stored in the variable V representing the number of horizontal lines (step S12).

  Subsequently, based on the result of the AE calculation, the camera control unit 14 sets a shutter speed SS (exposure time) (step S13).

  Then, the camera control unit 14 multiplies the delay time tk by the number obtained by subtracting 1 from the number of horizontal lines V (that is, all the signal charges in the first row group after starting to accumulate). It is determined whether or not it is greater than the sum of delay times tk until the start of accumulation of signal charges in the row group (step S14).

  Here, if it is determined that SS> tk × (V−1), the camera control unit 14 delays each Vk line (here, one line is assumed as a specific example). Shutter drive control for shifting the drive time by tk is set (step S15).

  If it is determined in step S14 that SS ≦ tk × (V−1), the camera control unit 14 calculates a delay time tk ′ that satisfies SS = tk ′ × (V−1). Thus, the shutter drive control for shifting the drive time by the delay time tk ′ is set for each Vk line (step S16).

  By performing the processing of step S15 or step S16, the camera control unit 14 functions as an exposure time setting unit, and starts the accumulation of signal charges in the first row group by the vertical scanning circuit 21. The predetermined delay time in the vertical scanning circuit 21 is controlled so that the sum of the predetermined delay times until the start of signal charge accumulation in the row group is equal to or less than the exposure time set in step S13. Yes.

  After performing the process of step S15 or step S16, it is determined whether or not the release button included in the camera operation unit 13 has been operated (step S17). If the button has not been operated yet, the process returns to step S11 and described above. Repeat the process.

  On the other hand, if it is determined in step S17 that the release button has been operated, electronic shutter driving is performed according to the first sequence as shown in FIG. 5 (step S18).

  Thereafter, image processing is performed by the image processing unit 8 (step S19), and the processed image is recorded on the memory card 12 and displayed on the display unit 9 as necessary (step S20). Is determined (step S21).

  If it is determined that shooting has not been completed, the process returns to step S11 to repeat the above-described processing. If it is determined that shooting has been completed, this processing ends.

  Next, FIG. 17 is a flowchart illustrating a second imaging program set in the imaging apparatus.

  When this process is started, the process from step S11 to S14 described above is performed, and further, the process of step S15 or step S16 described above is performed according to the determination result of step S14.

  Here, the processing after the processing of step S16 is the same as the processing shown in FIG.

  On the other hand, after performing the process of step S15, it is determined whether or not the release button included in the camera operation unit 13 has been operated (step S25), and if it has not been operated yet, the process returns to step S11 and described above. Repeat the above process.

  If it is determined in step S25 that the release button has been operated, electronic shutter driving is performed according to the second sequence as shown in FIG. 6 (step S26), and the process proceeds to step S19 described above. The subsequent processing is the same as the processing shown in FIG.

  According to the first embodiment, it is possible to achieve both the realization of the electronic global shutter and the reduction of the current peak value during the electronic global shutter without increasing the size of the imaging apparatus.

  In addition, since the total delay time tk until the start of signal charge accumulation in all row groups is controlled to be equal to or shorter than the exposure time, stroboscopic tuning can be performed at all shutter speeds. In a broad sense, it can be called a global shutter. As a result, it is possible to realize an imaging apparatus having a high strobe tuning speed that cannot be realized with a mechanical shutter without increasing the size.

  In addition, when manufacturing the imaging device, when the reset current of the photoelectric conversion unit is equal to or less than a predetermined value, the second imaging program including both the first sequence and the second sequence is set in the imaging device and reset. Since the first imaging program including the first sequence and not including the second sequence is set in the imaging device when the current is larger than the predetermined value, the signal charge accumulation start signal is applied to the photoelectric conversion unit PD. However, the reading of the reset data from the signal charge holding portion FD can be prevented from being affected. As a result, accurate reset data can be acquired, and FD dark current noise can be removed satisfactorily. Since the second sequence is executed when it can be executed, the FD dark current noise itself can be reduced, and image data with less noise can be obtained.

Furthermore, when a reset pulse or a transfer pulse is applied to each row group consisting of a plurality of rows, a higher-speed shutter can be realized while balancing power consumption.
[Embodiment 2]

  18 and 19 show the second embodiment of the present invention, and FIG. 18 is a circuit diagram showing a configuration example of the pixel 23 in the pixel portion 22 in more detail.

  In the second embodiment, parts that are the same as those in the first embodiment are given the same reference numerals and description thereof is omitted, and only differences are mainly described.

  First, the configuration of the pixel 23 of the present embodiment will be described with reference to FIG. In FIG. 18, a pixel 23 surrounded by a dotted line indicates a pixel area for two pixels. That is, the image sensor shown in FIG. 18 has a configuration as shown in the drawing, for example, every two adjacent pixels. When the configuration shown in FIG. 18 is adopted, a CDS section (not shown) that subtracts reset data from pixel data at a position preceding the horizontal scanning circuit 24 on the end side of each vertical transfer line VTL. )).

  The first photoelectric conversion unit PD positioned on the upper side of the drawing is connected to the transistor Mtx2 functioning as the first reset unit, and the second photoelectric conversion unit PD positioned on the lower side of the drawing is set to the transistor Mtx2 ′ functioning as the first reset unit. The signal charge accumulation start signal is applied to each signal line TX2 via (first transistor). In the configuration shown in FIG. 18, the reset of the first photoelectric conversion unit PD is performed by the transistor Mtx2, and the reset of the second photoelectric conversion unit PD is performed by the transistor Mtx2 '.

  The first photoelectric conversion unit PD is connected to the first charge storage unit C1 via the transistor Mtx1 that functions as a gate unit. The second photoelectric conversion unit PD is connected to the second charge storage unit C2 via the transistor Mtx1 'functioning as a gate unit. The transistors Mtx1 and Mtx1 'are connected to a signal line TX1 for applying a transfer pulse.

  The first charge accumulation unit C1 is connected to the signal charge holding unit FD via the transistor Mtx3 functioning as a gate unit. Here, the transistor Mtx3 is connected to a signal line TX3 for applying a transfer pulse. The second charge storage unit C2 is connected to the signal charge holding unit FD via a transistor Mtx4 that functions as a gate unit. Here, the transistor Mtx4 is connected to a signal line TX4 for applying a transfer pulse.

  The configuration after the signal charge holding unit FD is the same as that shown in FIG.

  Next, FIG. 19 is a timing chart showing the sequence of the global shutter operation in the imaging apparatus. The image sensor having the pixel configuration as shown in FIG. 18 is controlled to perform exposure first and then read out reset data and pixel data during the global shutter operation.

  That is, when the release button of the camera operation unit 13 is pressed and a release signal is input to the camera control unit 14, this global shutter operation is started based on the control of the camera control unit 14.

  Then, the signal charge accumulation start signal is sequentially applied to the transistors Mtx2 and Mtx2 ′ of all the lines via the signal line TX2 by a high-speed shutter that can be called a global shutter (see FIG. 7), whereby the transistors Mtx2, Mtx2 ′ is turned off and charge accumulation in the photoelectric conversion units PD of all pixels is started (exposure period starts).

  When a predetermined exposure period has elapsed after the start of exposure for each line, a high-speed shutter that can substantially transfer a transfer pulse to the transistors Mtx1 and Mtx1 ′ of all pixels of all lines via the signal line TX1. (See FIG. 8), the pixel charges accumulated in the photoelectric conversion unit PD are transferred to the first charge accumulation unit C1 and the second charge accumulation unit C2 (end of the exposure period). .

  Subsequently, a readout period of reset data and pixel data is started.

  That is, first, a reset pulse is applied from the signal line RES to the transistors Mr provided in common in the first row and the second row of the pixel portion 22, so that signals common to the first row and the second row are applied. The charge holding unit FD is reset. Further, the reset noise is read from the signal charge holding portion FD by applying a read pulse from the signal line SEL to the select transistors Mb provided in common in the first row and the second row of the pixel portion 22. .

  Immediately thereafter, a transfer pulse is applied to the transistor Mtx3 provided in the first row of the pixel portion 22 via the signal line TX3, whereby the pixel charge accumulated in the first charge accumulation portion C1 is converted into a signal charge. Transfer to holding unit FD. Further, pixel data is read from the signal charge holding portion FD by applying a read pulse from the signal line SEL to the selection transistors Mb provided in common in the first row and the second row of the pixel portion 22. .

  Then, the CDS unit in the imaging unit 6 performs a process of subtracting the reset noise from the pixel data and outputs the result to the horizontal scanning circuit 24.

  Such operations are sequentially performed from the first row to the V-th row (final row) for odd-numbered rows of the pixel unit 22 to output pixel data of odd-numbered lines from which reset noise is removed. .

  Next, the same operation is performed on even lines.

  That is, first, a reset pulse is applied from the signal line RES to the transistors Mr provided in common in the first row and the second row of the pixel portion 22, so that signals common to the first row and the second row are applied. The charge holding unit FD is reset. Further, the reset noise is read from the signal charge holding portion FD by applying a read pulse from the signal line SEL to the select transistors Mb provided in common in the first row and the second row of the pixel portion 22. .

  Immediately thereafter, a transfer pulse is applied to the transistor Mtx4 provided in the second row of the pixel portion 22 via the signal line TX4, whereby the pixel charge accumulated in the second charge accumulation portion C2 is converted into a signal charge. Transfer to holding unit FD. Further, pixel data is read from the signal charge holding portion FD by applying a read pulse from the signal line SEL to the selection transistors Mb provided in common in the first row and the second row of the pixel portion 22. .

  Then, the CDS unit in the imaging unit 6 performs a process of subtracting the reset noise from the pixel data and outputs the result to the horizontal scanning circuit 24.

  By sequentially performing such an operation from the second row to the Vth row (final row) for even rows of the pixel unit 22, pixel data of even lines from which reset noise has been removed is output. .

  According to the second embodiment, a high-speed shutter that can be substantially called a global shutter is performed on the imaging unit having the configuration shown in FIG. 18 as in the first embodiment, and substantially the same effect is obtained. Can be played.

  Further, according to the configuration of the second embodiment, since pixel data can be read immediately after reset data is read, it is possible to suppress the generation of FD dark current noise to almost zero, and there is little noise and image quality is reduced. There is an advantage that good image data can be obtained.

  Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. Moreover, various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the embodiment. For example, you may delete some components from all the components shown by embodiment. Furthermore, the constituent elements over different embodiments may be appropriately combined. Thus, it goes without saying that various modifications and applications are possible without departing from the spirit of the invention.

DESCRIPTION OF SYMBOLS 1 ... Shooting optical system 2 ... Zoom lens 3 ... Diaphragm 4 ... Focus lens 5 ... Lens drive part 6 ... Imaging part 7 ... AF process part 8 ... Image processing part 9 ... Display part 10 ... Back surface display part 11 ... Electronic viewfinder ( EVF)
DESCRIPTION OF SYMBOLS 12 ... Memory card 13 ... Camera operation part 14 ... Camera control part (exposure time setting part)
15 ... Power supply 21 ... Vertical scanning circuit (signal charge accumulation start signal controller, transfer pulse controller, readout pulse controller, reset voltage readout controller)
21a ... TX1 driver 21b ... TX2 driver 22 ... Pixel unit 23 ... Pixel 24 ... Horizontal scanning circuit 25 ... A / D conversion units C1, C2 ... Charge storage units Ctx1, Ctx2 ... Floating capacitance FD ... Signal charge holding unit Ma ... For amplification Transistor Mb ... selection transistor (third transistor)
Mr ... transistor (second transistor)
Mtx1, Mtx1 ′... Transistor (gate portion)
Mtx2, Mtx2 '... Transistor (first transistor)
Mtx3, Mtx4 ... Transistor (Gate part)
PD: photoelectric conversion unit RES, SEL, TX1, TX2, TX3, TX4 ... signal line VDD ... current source VTL ... vertical transfer line

Claims (3)

A photoelectric conversion unit for generating and storing a signal corresponding to the amount of incident light, a first transistor for resetting the photoelectric conversion unit, and a light shield for receiving a signal charge accumulated by the photoelectric conversion unit and holding it for a certain period of time The signal charge holding unit, the second transistor for resetting the signal charge holding unit, the signal charge that is arranged between the photoelectric conversion unit and the signal charge holding unit and accumulated by the photoelectric conversion unit Are arranged in a two-dimensional array in a row direction and a column direction, and a gate section for transferring the signal charge to the signal charge holding section and a third transistor for reading out the signal charge held in the signal charge holding section A pixel portion,
Applying a signal charge accumulation start signal for resetting the photoelectric conversion unit to start accumulation of signal charges in the photoelectric conversion unit for each row group composed of one or more rows, the same row A signal charge accumulation start signal control unit for applying each row belonging to a group at the same time, and for different row groups while being delayed by a predetermined delay time for each row group;
A transfer pulse for driving the gate unit to transfer the signal charge accumulated by the photoelectric conversion unit to the signal charge holding unit after a predetermined exposure time has elapsed since the signal charge accumulation start signal was applied. For each row group, and for each row belonging to the same row group, at the same time, the predetermined pulses are overlapped in time so that some of the transfer pulses that are temporally adjacent to each other overlap in time. A transfer pulse controller for applying while delaying each delay time;
A read pulse control unit for applying a read pulse for driving the third transistor and reading the signal charge accumulated in the signal charge holding unit;
An image pickup apparatus comprising:   The predetermined delay time from the start of signal charge accumulation of the first row group by the signal charge accumulation start signal control unit to the end of the start of signal charge accumulation of all row groups while setting the exposure time The imaging apparatus according to claim 1, further comprising an exposure time setting unit that controls the predetermined delay time in the signal charge accumulation start signal control unit so that a total sum of the signal charges becomes equal to or less than the exposure time. . The imaging apparatus according to claim 1, further comprising: a reset voltage read control unit that reads a reset voltage when the signal charge holding unit is reset.
When a reset current when the photoelectric conversion unit is reset by the signal charge accumulation start signal control unit is less than or equal to a predetermined value, the signal charge accumulation is performed after the reset voltage read control unit finishes reading all the pixels. A first sequence for starting signal charge accumulation by the start signal control unit, and signal charge accumulation by the signal charge accumulation start signal control unit before the reset voltage reading by the reset voltage read control unit is completed. A second imaging program including both of the second sequence to be started and set in the imaging device,
When the reset current is larger than the predetermined value, a first imaging program that includes the first sequence and does not include the second sequence is set in the imaging device.

Images