JP2010267117A - Audio data transfer device, transfer method and audio data processing system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress deterioration of data transfer efficiency between a cache memory and an external memory storing audio data of multi-channels processed by an arithmetic unit when a cache memory system is arranged between the external memory and the arithmetic unit. <P>SOLUTION: An audio data transfer device 40 includes a buffer memory 45 and a lookahead part 44. The lookahead part 44 controls to transfer at least part of the audio data of n pieces of channels (n is an integer of two or more) stored in the external memory 1 to the buffer memory 45. In addition, the lookahead part 44 adjusts the data transfer size when the audio data of m pieces of channels (m is an integer of 1-n) is transferred between the external memory 1 and the buffer memory 45 depending on m pieces of channels processed by the arithmetic unit 30 among the audio data of n pieces of channels. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an audio data transfer device that transfers audio data between an arithmetic device and an external memory.

  In recent years, AV devices such as digital televisions and DVD recorders are rapidly spreading. In addition, since multi-channel audio data such as 5.1 channel and 7.1 channel has been standardized, it is necessary to process multi-channel audio data in AV equipment.

The AV device has an AV decoder that decodes the encoded data. Non-Patent Document 1 discloses an AV decoder LSI.
The AV decoder is a PCR counter indicating a program time reference value (PCR: Program Clock Reference) necessary for synchronous playback of video and audio, and stream data input from the outside is converted into video data, audio data, subtitle information, character super information, etc. Multiplexing / separation core for separation, MPEG4-video core for video signal processing of video data, filter core for filtering processing to improve video quality, audio / audio core for audio audio decoding processing, etc. These operate in parallel.
The AV decoder operates by connecting each module to a common external memory in order to reduce the size of the circuit and reduce power consumption.

  Audio data audio decoding processing is generally performed by software processing using a CPU (Central Processing Unit), a DSP (Digital Signal Processor), or the like as an arithmetic unit. In order for the CPU and DSP to operate at high speed, it is essential to shorten the memory access time for the program and data stored in the external memory. Therefore, the voice / audio core has a cache with a program and data prefetching mechanism. Arithmetic unit with system is used.

Patent Document 1 discloses a network cache device and a program having a data prefetch function based on prefetch pattern data and a prefetch pattern data generation function.
Patent Document 2 discloses a cache control in which a cache area is configured by a plurality of blocks, and the priority is ranked for each block, and the rank is appropriately changed based on a reuse rate or the like, thereby efficiently using the cache area. A computer that performs a program and cache processing is disclosed.
Patent Document 3 discloses an arithmetic device and a data processing system using a cache system.

JP 09-212421 A JP 2003-122634 A JP 2008-003929 A

Masakazu Ishikawa, Atsushi Asano, Masae Sonami "LSI chip set for mobile broadcast receiving terminals (2)-limited receiving LSI and AV decoder LSI", Toshiba Review Vol.59 No.11 2004, P24-26

  When the inventor of the present application places a cache memory system between an external memory storing multi-channel audio data processed by the arithmetic device and the arithmetic device, the data transfer between the cache memory and the external memory is performed. We have found that there is a problem that efficiency decreases. This problem is caused by the data transfer size between the cache memory and the external memory and the data structure of multi-channel audio data. Hereinafter, this problem will be described.

  In general, the data transfer size between the cache memory and the external memory is a fixed size according to the cache line width in the cache memory, the amount of data to be read ahead, and the like. For this reason, for example, when the size of the data processed by the arithmetic device is smaller than the data transfer size, unnecessary data other than the data processed by the arithmetic device is transferred from the external memory to the cache memory. If the data processed by the arithmetic unit is larger than the data transfer size, access to the external memory must be divided into a plurality of times. These wasteful data transfer and increase in the number of memory accesses cause a decrease in data transfer efficiency between the cache memory and the external memory.

  In addition, multi-channel (for example, n channels; n is an integer of 2 or more) audio data includes one sample data composed of a set of data for n channels. For this reason, the decrease in the data transfer efficiency between the cache memory and the external memory described above becomes more remarkable. That is, even when only a part of channels (for example, m channels; m is an integer smaller than n) included in the multi-channel audio data is processed by the arithmetic device, the prefetching by the cache memory is n This is performed in units of sample data including data for channels. Therefore, unnecessary channel data other than the necessary m channels are transferred between the cache memory and the external memory and accumulated in the cache memory, or the data is transferred to the external memory for unnecessary channel data transfer. The number of accesses will increase.

Note that the network cache apparatus and program disclosed in Patent Document 1 create prefetch data in a specific pattern from cached data, and improve the transfer efficiency of data between the cache memory and the external memory. is not.
The cache control program and the computer that performs cache processing disclosed in Patent Document 2 perform ranking when holding data used in the past as cache, so that data that is frequently reused is stored in the cache memory. It is intended to improve the probability of existing data, and not to improve data transfer efficiency between the external memory and the cache memory.
An arithmetic unit and a data processing system using a cache system disclosed in Patent Document 3 are a load for controlling the start address, the end address, the read size, the address offset information, and the data prefetching of an area where data is prefetched. By having a plurality of cache / store cache control units, the cache memory is independent of the arithmetic unit, and the data stored in the address that is consecutive to the address requested to be accessed is prefetched into the cache memory, thereby waiting for the arithmetic unit. It is intended to shorten the time and does not improve the data transfer efficiency between the cache memory and the external memory.

  The audio data transfer apparatus according to the first aspect of the present invention includes a buffer memory and a prefetch unit. The prefetch unit controls a process of transferring at least a part of audio data of n channels (where n is an integer of 2 or more) stored in an external memory to the buffer memory. Further, the prefetching unit may determine the number of the m channels according to m channels (where m is an integer between 1 and n) of the n channels of audio data. A data transfer size is adjusted when audio data is transferred between the external memory and the buffer memory.

The audio data transfer method according to the second aspect of the present invention includes the following (a) and (b).
(A) Identifies audio data of m channels (where m is an integer equal to or greater than 1 and equal to or less than n) to be processed by a computing device among audio data of n channels (where n is an integer equal to or greater than 2) And (b) controlling a process of transferring audio data of the m channels from an external memory to a buffer memory by applying a data transfer size adjusted according to the m channels.

  As described above, according to each aspect of the present invention, the data transfer size between the external memory and the buffer memory is set according to m channels to be processed by the arithmetic unit among the n channels of audio data. Can be adjusted. For this reason, the occurrence of useless data transfer and increase in the number of data transfers caused by transferring the audio data of n channels between the external memory and the buffer memory regardless of whether or not to be processed by the arithmetic unit Can be suppressed.

  According to each aspect of the present invention described above, it is possible to suppress deterioration in data transfer efficiency when acquiring multi-channel audio data stored in an external memory so as to be supplied to an arithmetic device.

It is a block diagram of the audio data transfer apparatus concerning Embodiment 1 of invention. It is the schematic diagram showing the recording information of the data access recording part concerning Embodiment 1 of invention. It is a schematic diagram of the audio data buffer concerning Embodiment 1 of invention. It is a flowchart which shows the flow of the process of the audio data transfer concerning Embodiment 1 of invention. It is a flowchart which shows the analysis of the channel access concerning Embodiment 1 of invention. It is the schematic diagram showing the information currently recorded on the data access recording part concerning Embodiment 1 of invention. It is a schematic diagram at the time of transferring the data for 6 channels concerning Embodiment 1 of invention. It is a block diagram of the audio data transfer apparatus concerning Embodiment 2 of invention.

Embodiment 1 of the Invention
First, the configuration of an audio data processing system 50 according to an embodiment of the present invention will be described with reference to FIG. Each element and operation constituting the audio data processing system 50 will be described in detail later.

  The audio data processing system 50 includes an external memory 1, an instruction cache 10, a CPU 30, and an audio data transfer device 40. The audio data transfer apparatus 40 includes a data cache 20, a data address determination unit 41, a data access analysis unit 42, a data access recording unit 43, and an audio data prefetch unit 44. The audio data prefetch unit 44 has an audio data buffer 45.

  The CPU 30 outputs the address where the program to be executed is stored to the instruction cache 10, reads the program code stored at the address, and inputs data to the audio data transfer device 40 by executing the program. Output. Further, the CPU 30 outputs an internal data clear command to the data cache 20 and the audio data prefetch unit 44.

  The instruction cache 10 outputs an address to the external memory 1 and reads data stored at the address.

  The audio data transfer device 40 inputs and outputs data between the CPU 30 and the external memory 1.

  The data address discriminating unit 41 holds in advance the start address and end address of the audio data secured in the external memory 1. When the CPU 30 performs data access, the data address determination unit 41 compares the address information of the data that the CPU 30 intends to access with the address information held by the data address determination unit 41, and the data that the CPU 30 wants to access is It is determined whether or not the data is audio data. When the CPU 30 determines that the data to be accessed is audio data, the data address determination unit 41 outputs address information to the data access analysis unit 42. In addition, when the data address determining unit 41 determines that the data to be accessed by the CPU 30 is audio data, the data address determining unit 41 mediates data transfer between the audio data prefetching unit 44 and the CPU 30, When it is determined that the data is data, the data transfer is mediated between the data cache 20 and the CPU 30.

  The data cache 20 is a cache memory having no prefetching mechanism, and inputs / outputs data other than audio between the data address determination unit 41 and the external memory 1.

  When the data address discriminating unit 41 discriminates that the data requested by the CPU 30 is the audio data, the data access analyzing unit 42 obtains the address information of the audio data accessed by the CPU 30 from the data address discriminating unit 41. The CPU 30 analyzes the channel configuration of the audio data requested to be accessed from the address information, and outputs the result to the data access recording unit 43.

  The data access recording unit 43 inputs / outputs channel information requested by the CPU 30 to access to the data access analyzing unit 42 and the audio data prefetching unit 44, and records the access history to the channel requested by the CPU 30.

  FIG. 2 is a schematic diagram illustrating an example of recorded information of the data access recording unit 43. This represents access presence / absence information recorded in the data access recording unit 43 when the audio data has an 8-channel configuration (hereinafter referred to as CH1 to CH8), and the circled in FIG. 2 corresponds to the access presence / absence information. . FIG. 2 shows that CH1 to CH6 are channels being accessed by the CPU 30.

  The audio data prefetch unit 44 inputs and outputs audio data to and from the data address determination unit 41 and the external memory 1. Based on the access presence / absence information recorded in the data access recording unit 43, the audio data prefetching unit 44 reads audio data to be accessed next by the CPU 30 from the external memory 1 and writes it in the audio data buffer 45. .

  Here, the prediction of the address of the external memory 1 storing the audio data to be accessed next by the CPU can be performed by storing the audio data in the external memory 1 with regularity. For example, the audio data to be accessed next by the CPU 30 from the address information held by the audio data prefetch unit 44 is obtained by previously storing the audio data sequentially in the order of the channels on consecutive addresses in the external memory 1. Can be predicted.

  The audio data prefetch unit 44 outputs the data stored in the audio data buffer 45 to the data address determination unit 41 and stores the address information of the audio data requested to be accessed from the CPU 30 in the audio data buffer 45. Based on the data amount, the channel configuration information of the audio data requested by the CPU 30 analyzed by the data access analyzing unit 42, and the access presence / absence information stored in the data access recording unit 43, the audio data to be accessed next by the CPU 30 is stored. The address of the external memory 1 is predicted, and the data stored in the audio data buffer 45 and the data of the external memory 1 are exchanged. Here, the accessed audio data can be grasped by using the access presence / absence information stored in the data access recording unit 43, and efficient data transfer between the external memory and the audio buffer can be achieved.

  Here, the audio data prefetching unit 44 does not refer to the recording contents recorded in the data access recording unit 43, but has a channel configuration of the audio data that the audio data prefetching unit 44 previously holds and requests access by the CPU 30. Audio data can be input to the audio buffer 45 based on the address information of the external memory 1 in which information and audio data are stored. Also, audio data can be input from the external memory 1 to the audio data buffer 45 based on the address information input from the data address determination unit 41.

  FIG. 3 is a schematic diagram of the audio data buffer 45. FIG. 3A shows a state in which no data is input to each bank. In FIG. 3, reference numerals 100 to 107, 200 to 207, 300 to 307, 400 to 407, and 500 to 507 represent audio data, respectively. The audio data buffer 45 is composed of two banks. When the data accessed by the CPU 30 moves from the bank 1 to the bank 2 and from the bank 2 to the bank 1, the data is exchanged. The data size per bank is based on the processing speed of the CPU 30, the data transfer speed of the audio data prefetch unit 44 and the external memory 1, and the data size at which the data replacement is completed before the CPU 30 accesses the data in the same bank next time. And good.

  The data exchange operation between the audio data buffer 45 and the external memory 1 will be described below.

  When the data stored at the address referred to by the CPU 30 is not stored in the audio data buffer 45, the audio data prefetch unit 44 writes all the data in the audio data buffer 45 to the external memory 1 and newly adds the audio data. Data stored in the buffer 45 at the address referred to by the CPU 30 corresponding to the buffer size of the audio data buffer 45 is read from the external memory 1 and written to the audio data buffer 45. FIG. 3B shows an example of a state where data is written in the audio buffer 45.

  When data stored at an address referenced by the CPU 30 moves between banks of the audio data buffer 45, the CPU 30 moves between banks unless access channel information is recorded in the data access recording unit 43. All data in the bank that was previously accessed is written to the external memory 1, and data of the size of one bank is read into the bank that has been written to the external memory 1. FIG. 3C shows an example of a state in which data is read from the bank 1 after the bank 1 writes data to the external memory 1. FIG. 3C shows that the audio data 300 to 307 are stored in the location where the audio data 100 to 107 are stored from the state of FIG.

  When the information of the access channel is recorded in the data access recording unit 43, based on the contents of the data access recording unit 43, the data of the bank to which the CPU 30 was accessing before moving between the banks is determined. Only the audio data accessed by the CPU 30 for the specific channel is written to the external memory 1, and only the audio data accessed by the CPU 30 for the specific channel is read from the external memory 1 into the area where the data is written to the external memory 1. FIG. 3D shows an example of a state in which only data of the channel accessed by the CPU 30 is read from the bank 1 after the bank 1 has written the data to the external memory 1. FIG. 3D shows that the audio data 300, 301, 305, and 306 are stored in the location where 100, 101, 105, and 106 are stored from the state of FIG. Yes.

  If the channel information has been recorded in the data access recording unit 43 and there is data that the CPU 30 has never accessed in the data in the bank that has been accessed so far, all the access presence / absence information in the data access recording unit 43 is stored. Clear, write all data stored in the audio data buffer 45 to the external memory 1, and newly store the data stored in the audio data buffer 45 at the address referenced by the CPU 30 for the buffer size of the audio data buffer 45 Are read from the external memory 1 into the audio data buffer 45. FIG. 3E shows an example of a state where audio data is newly read from the external memory 1 into the audio data buffer 45. FIG. 3E shows that data different from the data stored in the audio buffer 45 so far has been stored in the audio buffer 45.

  When the CPU 30 finishes the process, the CPU 30 requests the audio data prefetch unit 44 to clear the internal data of the audio data buffer 45. When receiving the internal data clear request from the CPU 30, the audio data prefetch unit 44 writes all the data stored in the audio data buffer 45 to the external memory and clears all access presence / absence information in the data access recording unit 43.

FIG. 4 is a flowchart showing an example of the operations of the audio data processing system 50 and the audio data transfer device 40.
As shown in FIG. 4, first, the CPU 30 outputs an access request for acquiring data (step S10). Next, it is determined from the address information included in the access request whether or not the information stored at the corresponding address is audio data (step S11).

  If it is determined in step S11 that the data is audio data, the address information is transferred to the audio data prefetch unit 44 (step S12), and the channel data requested to be accessed from the address information is analyzed (step S13). The analysis result is recorded in the data access analysis unit (step S14). The audio data prefetch unit 44 prefetches audio data of a specific channel that the CPU 30 next requests from the external memory 1 based on the currently requested external memory address information and the information recorded in step S14. (Step S15). The CPU 30 inputs the pre-read audio data to the audio buffer and sequentially processes it (step S16).

  If it is determined in step S11 that the data is not audio data, the address information is transferred to the data cache 20 (step S17), and the CPU 30 performs processing as necessary (step S18).

  FIG. 5 is a flowchart showing an example of a procedure when the data access analysis unit 42 analyzes the address information of the audio data accessed by the CPU 30 and writes the channel information in the data access recording unit 43.

  The data access analysis unit 42 is in a standby state before the start of processing, and determines whether the CPU 30 has accessed audio data after the start of processing. The determination is performed by comparing the address information of the audio data held by the data address determination unit 41 with the address referred to by the CPU 30. When it is determined that the CPU 30 has accessed the audio data, the address referred to by the CPU 30 is input from the data address determination unit 41 to the data access analysis unit 42. If it is determined that the access performed by the CPU 30 is not for audio data, the process is repeated (step S20).

When the address of the audio data accessed by the CPU 30 is input from the data address determination unit 41, the data access analysis unit 42 determines which channel the audio data accessed by the CPU 30 is based on the input address ( Step S21). At this time, the audio channel can be obtained by Equation 1, for example. Here,% indicates a remainder operator that returns the remainder of division as a calculation result.
Audio channel = {(A−B) / C% D} +1.
A: CPU access address B: Start address of audio data area C: Data size per channel D: Total number of channels

  The data access analysis unit 42 determines whether the audio data accessed by the CPU 30 for the specific channel has been accessed based on the access presence / absence information of the data access recording unit 43 (step S22). When the channel accessed by the CPU 30 has been accessed, the writing to the data access recording unit 43 is terminated. When the channel accessed by the CPU 30 is not accessed, if the audio data accessed by the CPU 30 for the specific channel has been accessed, the data is recorded in the data access recording unit 43 (step S23), and the data access analyzing unit 42 returns to the standby state. .

  FIG. 6 shows a state in which access channel information is recorded in the data access recording unit 43 when the CPU 30 performs data access in a channel configuration including discontinuous channels. In this case, either the data size priority mode or the access count priority mode is selected to perform data transfer.

  In the data size priority mode, in the case of a channel configuration including discontinuous channels, data transfer is divided by the channels before and after the channel configuration. As shown in FIG. 6, when the CPU 30 accesses the audio data of CH1, CH2, CH6, and CH7, data transfer for 2 channels of CH1 and CH2 and data transfer of 2 channels of CH6 and CH7 are performed. Divide the data transfer into times. As a result, unnecessary data can be prevented from being transferred, and the data size can be reduced.

  In the access count priority mode, priority is given to the number of data transfers performed once, and for audio data that the CPU 30 requests access to, data of channels that the CPU 30 does not plan to use when the channel configuration is discontinuous. Including data transfer. As shown in FIG. 6, when the CPU 30 accesses the audio data of CH1, CH2, CH6, and CH7, data for 7 channels from CH1 to CH7 are transferred by one data transfer.

  FIG. 7 is a schematic diagram of data transfer from the external memory 1 to the audio data buffer 45 when the CPU 30 accesses data for six channels. Data transfer is an arbitration period in which information on the address and size of data to be accessed is transmitted, or when another module is using the bus, waiting until the transfer is completed, and data is transmitted and received following the arbitration period. It consists of a data transfer period.

  FIGS. 7A and 7B are comparative examples for explaining that the data transfer efficiency of the audio data transfer apparatus 40 according to the present embodiment is good. FIG. 7C shows transfer by the audio data transfer device 40.

  FIG. 7A shows an example in which the amount of data transmitted and received in one data transfer is 2 channels, and 6-channel data is divided and transferred in multiple times. In this case, it is necessary to provide an arbitration period for the data transfer of CH3 and CH4 and the data transfer of CH5 and CH6 as well as providing the arbitration period before the data transfer of CH1 and CH2. The data transfer in this case is an arbitration period, CH1 data transfer, CH2 data transfer, arbitration period, CH3 data transfer, CH4 data transfer, arbitration period, CH5 data transfer, and CH6 data transfer. Since a period is required, the entire data transfer time becomes long.

  FIG. 7B is an example in which data transfer is performed with a fixed transfer size regardless of the channel configuration of audio data accessed by the CPU 30. FIG. 7B shows an example in which the amount of data transmitted and received in one data transfer is 8 channels and the channel configuration of audio data accessed by the CPU 30 is only 6 channels from CH1 to CH6. . In this case, a series of processes including an arbitration period, CH1 data transfer, CH2 data transfer, CH3 data transfer, CH4 data transfer, CH5 data transfer, CH6 data transfer, CH7 data transfer, and CH8 data transfer As a result, even the data of CH7 and CH8 that the CPU 30 does not plan to access is transferred, and the entire data transfer time becomes longer.

  In the present embodiment, data transfer is performed in accordance with the data size of the audio data being accessed by the CPU 30 based on the channel configuration recorded in the data access recording unit 43. As shown in FIG. 7C, when the channel configuration of the audio data accessed by the CPU 30 is only 6 channels from CH1 to CH6, the data transfer is an arbitration period, the data transfer of CH1, the data transfer of CH2, the data transfer of CH3 Data transfer, CH4 data transfer, CH5 data transfer, and CH6 data transfer. Since only 6 channels of data required for one access are transferred, the data transfer efficiency is better than the examples shown in FIGS. 7A and 7B, and the transfer time can be shortened.

  Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention. For example, when replacing the banks of the audio data buffer 45, the CPU 30 assigns the audio data of a specific channel stored in the external memory 1 to a specific block of the audio data buffer 45, so that the CPU 30 stores the audio data buffer 45. It is also possible to make it easy to search for audio data of a specific channel that is held.

Embodiment 2 of the Invention
FIG. 8 is a configuration diagram of the audio data transfer apparatus according to the second embodiment, and is a configuration diagram in a method in which the CPU 30 operates by rewriting the data access recording unit 43.

  The configuration differs from that of the first embodiment in that the data access analysis unit 42 is not provided, and information regarding the channel configuration of audio data accessed by the CPU 30 is newly output from the CPU 30 to the data access recording unit 43.

  In the first embodiment, the data access analysis unit 42 analyzes the channel configuration based on the address information referred to by the CPU 30 and records the result in the data access recording unit 43. On the other hand, in the second embodiment, the channel configuration to be accessed before the CPU 30 accesses the audio data is written in the data access recording unit 43, and then the audio data is accessed.

  The audio data prefetch unit 44 refers to the access presence / absence information written in the data access recording unit 43 and transfers data between the audio data buffer 45 and the external memory 1. Thereby, an effect equivalent to that of the first embodiment can be obtained.

  In the second embodiment, the audio data is accessed after recording the channel configuration for accessing the data access recording unit 43 before the CPU 30 accesses the audio data. Therefore, the audio data prefetch unit 44 can perform data transfer between the audio data buffer 45 and the external memory 1 with a size matching the channel configuration of the audio data accessed by the CPU 30 from the first audio data access.

  Each component used in the second embodiment has the same function as each component described in the first embodiment, and detailed description thereof is omitted.

  The operation flow of the audio data processing system 50 and the audio data transfer device 40 in the apparatus according to the second embodiment is the same as that shown in the flowchart of FIG. 4 before step S13 for performing address analysis and before the CPU 30 accesses the audio data. And a step of previously recording a channel configuration for accessing the data access recording unit 43.

  Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention. For example, in the first and second embodiments, the data buffer 45 does not need to perform both reading and writing, and may be only read access.

1 External memory 10 Instruction cache 20 Data cache 30 CPU
40 Audio Data Transfer Device 41 Data Address Determination Unit 42 Data Access Analysis Unit 43 Data Access Recording Unit 44 Audio Data Prefetching Unit 45 Audio Data Buffer 50 Audio Data Processing System

Claims (15)

Buffer memory,
A prefetch unit that controls a process of transferring at least a part of audio data of n channels (where n is an integer of 2 or more) stored in an external memory to the buffer memory;
With
The prefetching unit is configured to perform audio data of the m channels according to m channels (m is an integer of 1 to n) of the n channels of audio data. Adjusting the data transfer size when transferring between the external memory and the buffer memory,
Audio data transfer device.   The prefetch unit adjusts the data transfer size so that the number of times of data transfer between the buffer memory and the external memory required for acquiring audio data of the m channels is reduced. The audio data transfer device described in 1.   The prefetching unit adjusts the data transfer size so that a data transfer size per time between the buffer memory and the external memory necessary for acquiring the audio data of the m channels is reduced. The audio data transfer apparatus according to claim 1 or 2. The prefetching unit identifies the m channels based on address information output by the arithmetic device to acquire the audio data from the external memory;
The audio data transfer device according to any one of claims 1 to 3. The prefetching unit receives a notification identifying the m channels from the arithmetic unit;
The audio data transfer device according to any one of claims 1 to 4. The audio data transfer according to any one of claims 1 to 5, wherein the prefetching unit specifies audio data of the m channels to be acquired next based on a history of the arithmetic device accessing the external memory. apparatus. The data address determination unit for determining whether the data accessed by the arithmetic unit is audio data, and the data cache unit for caching the data when the data is not audio data. An audio data transfer device according to claim 1. First of identifying audio data of m channels (where m is an integer equal to or greater than 1 and equal to or less than n) to be processed by a computing device among audio data of n channels (where n is an integer equal to or greater than 2) Audio data identification step,
A transfer control step of controlling a process of transferring audio data of the m channels from an external memory to a buffer memory by applying a data transfer size adjusted according to the m channels;
Including audio data transfer method. A data transfer size adjustment step of adjusting the data transfer size so that the number of times of data transfer between the buffer memory and the external memory required for acquiring the audio data of the m channels is reduced;
The audio data transfer method according to claim 8, further comprising: A data transfer size adjustment step for adjusting the data transfer size so that a data transfer size per time between the buffer memory and the external memory required for acquiring the audio data of the m channels is reduced. ,
The audio data transfer method according to claim 8, further comprising: The audio data according to any one of claims 8 to 10, wherein the first audio data specifying step is performed based on address information output by the arithmetic device to acquire the audio data from the external memory. Transfer method. 12. The audio data transfer method according to claim 8, further comprising a channel specification notification receiving step of receiving a notification specifying the m channels from the arithmetic device. 13. The audio data specifying step according to claim 8, further comprising a second audio data specifying step of specifying audio data of the m channels to be acquired next based on a history of access to the external memory by the arithmetic device. The audio data transfer method described in 1. An audio data discriminating step for discriminating whether the data accessed by the arithmetic unit is audio data;
A data cache step of caching the data in a data cache unit when the data is not audio data;
The audio data transfer method according to claim 8, comprising: The arithmetic unit, the external memory,
An audio data processing system comprising the audio data transfer device according to any one of claims 1 to 7.

Images