JP2010263602A - Packet processing device, and power control method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce a needless power consumption in a DSP put in a low load state. <P>SOLUTION: A CPU 21 in a packet processing device 1 collects statistical information from an FPGA 31 of a voice data processing card 30 and monitors processing loads of DSPs. The CPU 21, when detecting that the processing load of one of the DSPs is low and determining that the device can be shifted to a power saving mode, determines the DSP as a power turning off target, and controls the device so as to change an allocation table 311a in the FPGA 31. The FPGA 31, when the allocation table 311a is changed, informs the CPU 21 of completion of the table change. A DSP power control element 32 turns off the DSP as the power turning off target. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a packet processing apparatus and a power control method for controlling the power supply of a packet processing unit.

  Conventionally, in a packet processing card equipped with a device for codec conversion of voice packets, error checking of input packets is performed by FPGA (Field Programmable Gate Array) or LSI (Large Scale Integration), and codec conversion is performed by DSP ( (Digital Signal Processor).

  In the packet processing card, a plurality of DSPs are provided as shown in FIG. The FPGA performs an error check on the input packet and determines which DSP is to perform codec conversion processing according to channel information included in the packet.

  Specifically, the FPGA has a sorting table as shown in FIG. In the distribution table, as illustrated in FIG. 12, channel information and a DSP that performs codec conversion on a packet are stored in association with each other. Under such a configuration, the FPGA extracts channel information included in the packet, and acquires a DSP corresponding to the extracted channel information from the distribution table. Then, the FPGA is determined as a DSP that performs codec conversion processing, and distributes packets to the determined DSP.

  For example, in the example of the distribution table in FIG. 12, each DSP performs codec conversion processing of voice packets for 200 channels. Specifically, using the example of FIG. 12, DSP # 0 performs codec conversion processing of 0 to 199 channel voice packets, and DSP # 1 performs codec conversion processing of voice packets of 200 to 399 channels. It becomes.

  Then, the DSP performs codec conversion on the input packet and returns the converted packet to the FPGA. Further, the DSP stands by in an idle state when no packet is input.

JP 2008-98785 A JP 2003-281008 A

  By the way, in the above-described conventional technology, since a plurality of DSPs are mounted on one audio data processing card, the power consumption of the DSP and the memory is high. In addition, even when the packet flow rate is reduced, all DSPs remain powered on, and standby power due to leakage current is consumed, resulting in additional power consumption.

  Accordingly, the present invention has been made to solve the above-described problems of the prior art, and an object thereof is to reduce unnecessary power consumption to the DSP at the time of low load.

  In order to solve the above-described problems and achieve the object, this apparatus monitors the processing load of the signal processing unit, and cuts off the power supply to the signal processing unit when the monitored processing load is low. It is necessary to control as follows.

  The disclosed apparatus has an effect of reducing unnecessary power consumption to the DSP at the time of low load.

FIG. 1 is a block diagram illustrating the configuration of the packet processing apparatus according to the first embodiment. FIG. 2 is a diagram for explaining a detailed configuration of the transmission / reception unit. FIG. 3 is a diagram illustrating an example of a packet format. FIG. 4 is a diagram for explaining the coefficient table. FIG. 5 is a diagram for explaining the DSP processing load calculation processing of the weight determination unit. FIG. 6 is a diagram illustrating an example of changing the distribution table when shifting to the power saving setting. FIG. 7 is a diagram illustrating an example of changing the distribution table at the time of shifting to the steady setting. FIG. 8 is a sequence diagram illustrating a processing flow when the power is turned off by the packet processing apparatus according to the first embodiment. FIG. 9 is a sequence diagram illustrating a processing flow when the power is turned on again by the packet processing apparatus according to the first embodiment. FIG. 10 is a diagram for explaining the prior art. FIG. 11 is a diagram for explaining the prior art. FIG. 12 is a diagram for explaining the prior art. FIG. 13 is a block diagram illustrating the configuration of the packet processing apparatus according to the second embodiment. FIG. 14 is a block diagram illustrating a configuration of a buffer control block according to the second embodiment. FIG. 15 is a diagram illustrating an example of a silence process according to the second embodiment. FIG. 16 is a flowchart illustrating the flow of processing by the buffer control block according to the second embodiment. FIG. 17 is a sequence diagram illustrating the flow of processing performed by the packet processing apparatus according to the second embodiment. FIG. 18 is a diagram illustrating the effects of the packet processing apparatus according to the second embodiment.

  Exemplary embodiments of a packet processing apparatus and a power supply control method according to the present invention will be described below in detail with reference to the accompanying drawings. The present invention is not limited to the examples described below. Each embodiment can be appropriately combined within a range in which processing contents do not contradict each other.

  In the following embodiments, the configuration and processing flow of the packet processing apparatus according to the first embodiment will be described in order, and finally the effects of the first embodiment will be described.

[Configuration of packet processing device]
First, the configuration of the packet processing apparatus 1 will be described with reference to FIG. FIG. 1 is a block diagram illustrating the configuration of the packet processing apparatus 1 according to the first embodiment. As shown in the figure, the packet processing device 1 includes a packet switch card 10, a control card 20, a voice data processing card 30, and software 40, which are connected via a bus. The processing of each of these units will be described below.

  The packet switch card 10 has a switch function LSI 11 having a switch function, and transmits the received packet to the audio data processing card 30. Further, the switch function LSI 11 includes a packet number counting unit 11a.

  The packet number counting unit 11a counts the number of packets processed by the audio data processing card 30. Specifically, the packet number counting unit 11a counts the number of packets that the switch function LSI 11 transmits to the audio data processing card 30, and notifies the control card 20 of the counted number of packets.

  The voice data processing card 30 performs codec conversion of voice packets, and particularly includes an FPGA 31, a DSP power control element 32, a plurality of regulators 33a to 33f, a plurality of DSPs 34a to 34f, and a plurality of memories 35a to 35f.

  The FPGA 31 performs an error check on the input packet, and particularly includes a transmission / reception unit 310, a packet distribution unit 311, a buffer control unit 312, and a power supply control unit 313.

  The transmission / reception unit 310 receives a packet from the packet switch card 10 and performs a packet check for an error in the received packet. Here, a detailed configuration of the transmission / reception unit will be described with reference to FIG. FIG. 2 is a diagram for explaining a detailed configuration of the transmission / reception unit. As shown in FIG. 2, the transmission / reception unit 310 includes a packet monitoring unit 310a and a weighting determination unit 310b.

  The packet monitoring unit 310a extracts packet length and codec conversion type information as the DSP processing load, and monitors the DSP processing amount based on the extracted packet length and codec conversion type. Specifically, the packet monitoring unit 310 a receives a packet from the packet switch card 10. A packet check is performed to check if there is an error in the received packet.

  As a result, when the packet monitoring unit 310a determines that the packet is normal, the packet monitoring unit 310a extracts the payload length and the CODEC type information, and notifies the weighting determination unit 310b of the payload length and the codec type information.

  Here, the extraction process will be specifically described with reference to the example of the packet format of FIG. The packet monitoring unit 310a extracts the payload length excluding the header from the packet and the codec type information included in the header.

  The weighting determination unit 310b calculates the DSP processing amount using the packet length and codec conversion type information, and particularly includes a coefficient extraction unit 310A and a calculation unit 310B. The coefficient extraction unit 310A includes a coefficient table 311A that stores codec conversion types and coefficients in association with each other.

  Specifically, as illustrated in FIG. 4, the coefficient table 311A includes “conversion source CODEC” that is codec information before conversion, “conversion destination CODEC” that is codec information after conversion, and each conversion type. The “coefficients” set according to the processing load are stored in association with each other. 4 will be described with reference to the example of FIG. In the case of codec conversion to be codec converted to 711u, the coefficient is “× 1”.

  The coefficient stored in the coefficient table 311A is set to a higher value as the codec conversion has a higher processing load. The coefficient can be freely set by the software according to the number of steps of the DSP codec conversion program and the processing time measurement during debugging. The coefficient may be changed to an arbitrary value.

  Here, the DSP processing load calculation process of the weight determination unit 310b will be described with reference to FIG. FIG. 5 is a diagram for explaining the DSP processing load calculation processing of the weight determination unit. As shown in FIG. 5, the weight determination unit 310b receives the payload length and codec type information from the packet monitoring unit 310a (see (1) in FIG. 5). Then, the coefficient extraction unit 310A of the weight determination unit 310b searches the coefficient table 311A using the codec type information (see (2) in FIG. 5), extracts the coefficient, and notifies the calculation unit 310B (FIG. 5 (3)).

  In addition, when the payload length is input from the transmission / reception unit 310 (see (4) in FIG. 5) and the coefficient is received from the coefficient extraction unit 310A, the calculation unit 310B multiplies the payload length by the coefficient, and according to the DSP processing load. The packet length is normalized (see (5) in FIG. 5).

  The calculation unit 310B adds and counts the normalized results (see (6) in FIG. 5). Thereafter, the calculation unit 310B notifies the CPU (Central Processing Unit) 21 as statistical information (see (7) in FIG. 5).

  Returning to the description of FIG. 1, the packet distribution unit 311 includes a buffer that holds packets received from the transmission / reception unit 310 and a distribution table 311 a that is referred to in order to determine a distribution destination DSP.

  As illustrated in FIG. 6, the distribution table 311a stores a voice communication channel of a packet and a DSP that performs codec conversion of the packet in association with each other. The packet distribution unit 311 reads the DSP corresponding to the voice call channel of the packet received from the transmission / reception unit 310 from the distribution table 311a, and distributes the packet to the read DSP.

  For example, when the voice call channel of the packet received from the transmission / reception unit 310 is “CH # 0”, the packet distribution unit 311 refers to the distribution table 311a and distributes the packet to “DSP # 0”.

  The buffer control unit 312 includes buffers corresponding to DSP # 0 to DSP # 5, and includes a buffer amount measurement unit 312a that measures the buffer accumulation amount. The buffer control unit 312 receives a packet from the packet distribution unit 311. Then, the buffer control unit 312 holds the packet in the buffer corresponding to the distribution destination DSP of the received packet.

  The buffer amount measuring unit 312a measures the accumulated amounts of the buffers corresponding to DSP # 0 to DSP # 5. Then, the buffer amount measuring unit 312a notifies the CPU 21 of the control card 20 of the measured accumulation amount of each buffer.

  Here, the control card 20 will be described. The control card 20 controls the power sources of the DSPs 34 a to 34 f in the audio data processing card 30, and particularly has a CPU 21. The CPU 21 collects statistical information from the packet switch card 10 and the voice data processing card 30 and monitors the processing load of the DSP. Then, the CPU 21 determines whether or not to shift to the power saving setting for suppressing the power consumption of the DNS according to the processing load of the DSP, and particularly includes the power saving determination unit 21a.

  Here, the statistical information means “number of packets” counted by the packet number counting unit 11a, “DSP processing amount” calculated by the weighting determination unit 310b, and “accumulation of each buffer” measured by the buffer amount measuring unit 312a. It means “amount”.

  The power saving determination unit 21a holds a threshold value for each piece of statistical information, and uses the statistical information constantly transmitted from the packet switch card 10 and the voice data processing card 30 to determine whether the DSP processing load is low. To do. Specifically, the power saving determination unit 21a determines whether the increase amount of the “number of packets” per unit time is equal to or less than a predetermined threshold. The power saving determination unit 21a determines whether the increase amount of the “DSP processing amount” per unit time is equal to or less than a predetermined threshold.

  As a result, the power saving determination unit 21a determines that the increase amount of the “number of packets” per unit time is equal to or less than a predetermined threshold value, and the increase amount of the “DSP processing amount” per unit time is equal to or less than the predetermined threshold value. If it is determined, it is determined that the power saving setting can be entered. Note that the power saving determination unit 21a may determine whether or not the shift is possible in consideration of a load deviation for each DSP.

  When it is determined that the CPU 21 can shift to the power saving setting, the CPU 21 notifies the software 40 of shifting to the power saving setting, and waits for permission to shift to the power saving setting from the software 40. Note that the CPU 21 may make a determination independently without notifying the software 40.

  Thereafter, when receiving the power saving setting transition permission from the software 40, the CPU 21 determines a DSP to be powered off and controls to change the distribution table 311 a in the FPGA 31. For example, as illustrated in FIG. 6, the distribution table 311 a is changed so that DSP # 4 and DSP # 5 do not have CH allocation in order to set DSP # 4 and DSP # 5 as power-off targets. As the number of DSPs to be distributed decreases, the number of corresponding channels per DSP increases.

  Then, the CPU 21 monitors the “buffer accumulation amount” notified from the buffer amount measurement unit 312a, and at the time when the packet buffer amount to the DSP to be powered off becomes “0”, the DSP power control element An instruction to issue a power-off instruction to 32 is notified to the power supply control unit 313.

  Here, a process of returning to the steady setting after shifting to the power saving setting will be described. Specifically, the power saving determination unit 21a determines whether the increase amount of the “number of packets” per unit time is equal to or greater than a predetermined threshold. The power saving determination unit 21a determines whether the increase amount of the “DSP processing amount” per unit time is equal to or greater than a predetermined threshold. The power saving determination unit 21a determines whether the “buffer accumulation amount” is equal to or greater than a predetermined threshold.

  As a result, the CPU 21 determines whether the increase in the “number of packets” per unit time is equal to or greater than a predetermined threshold, the increase in the “DSP processing amount” per unit time is equal to or greater than a predetermined threshold, or “ If any one of the conditions “buffer accumulation amount” is equal to or greater than a predetermined threshold value is satisfied, it is determined that the processing capacity of the audio data processing card is not sufficient, and the DSP is turned on again.

  Then, the CPU 21 notifies the power supply control unit 313 of an instruction to issue a power reactivation instruction to the DSP power supply control element 32. Further, the CPU 21 notifies the software 40 that the power is being turned on again. Note that if the software 40 is not notified when the power is turned off, the notification is not necessary here either.

  The CPU 21 changes the distribution table 311a of the FPGA 31 when the BOOT process of the DSP is completed. As illustrated in FIG. 7, the distribution table 311 a is changed so that CHs are assigned to DSP # 4 and DSP # 5 that are the targets of power-off. As the number of DSPs to be distributed increases, the number of corresponding channels per DSP decreases.

  The power control unit 313 controls the power of each of the DSPs 34a to 34f. Specifically, when receiving an instruction to issue a power-off instruction from the CPU 21, the power-supply control unit 313 instructs the DSP power-control element 32 to turn off the power and notifies the DSP to be turned off. When the power control unit 313 receives an instruction from the CPU 21 to issue a power reactivation instruction, the power control unit 313 instructs the DSP power control element 32 to power on and also notifies the DSP to be powered on.

  The DSP power supply control element 32 individually manages the power supplies of the DSPs 34a to 34f. Specifically, when the DSP power supply control element 32 receives a power-off instruction from the power supply control unit 313, the DSP power supply control element 32 controls the power-off sequence of a plurality of types of power to the DSP and cuts off the power of the DSP to be turned off. .

  When the DSP power control element 32 receives a power-on instruction from the power control unit 313, the DSP power-control element 32 re-powers the DSP to be powered on while controlling the power-on sequence of the plural types of power to the DSP.

  The regulators 33a to 33f are circuits that are provided in the DSPs 34a to 34f, respectively, and control so that the voltage and current input to the DSPs 34a to 34f are always kept constant.

  The DSPs 34a to 34f perform codec conversion on the received packets. Further, the DSPs 34 a to 34 f are activated when the power is turned on again, perform a BOOT process for loading a program, and notify the FPGA 31 of a BOOT process completion notification when the BOOT process is completed.

  Further, in each of the DSPs 34a to 34f and each of the memories 35a to 35f, the power supply layer is also divided for each DSP so that power on / off can be controlled independently.

  When the software 40 receives a notification to the effect of shifting to the power saving setting from the power saving determination unit 21a, the software 40 determines whether it is possible to shift to the power saving setting. Notify the power determination unit 21a. The overall power supply control element 36 manages the power supply of the entire audio data processing card 30.

[Processing by packet processor]
Next, processing performed by the packet processing apparatus 1 according to the first embodiment will be described with reference to FIGS. 8 and 9. FIG. 8 is a sequence diagram illustrating a processing flow when the power is turned off by the packet processing apparatus according to the first embodiment. FIG. 9 is a sequence diagram illustrating a processing flow when the power is turned on again by the packet processing apparatus according to the first embodiment.

  As shown in FIG. 8, the CPU 21 of the packet processing device 1 collects statistical information from the FPGA 31 of the voice data processing card 30 and monitors the processing load of the DSP (step S101). When the CPU 21 determines that the increase amount of the “number of packets” per unit time is equal to or less than a predetermined threshold value and the increase amount of the “DSP processing amount” per unit time is equal to or less than the predetermined threshold value, The DSP processing load is detected to be low (step S102).

  When it is determined that the CPU 21 can shift to the power saving setting, the CPU 21 notifies the software 40 of the transition to the power saving setting (step S103), and permits the power saving setting shift permission from the software 40. Receive (step S104).

  Subsequently, when receiving the power saving setting transition permission from the software 40, the CPU 21 determines a DSP to be powered off and controls to change the distribution table 311a in the FPGA 31 (step S105). Then, when the distribution table 311a is changed (step S106), the FPGA 31 notifies the CPU 21 that the change is completed (step S107).

  Thereafter, when the CPU 21 detects that the packet buffer amount to the DSP to be turned off becomes “0” while monitoring the “buffer accumulation amount” (step S108), the CPU 31 is turned off to the FPGA 31. The DSP is notified (step S109).

  Then, the FPGA 31 instructs the DSP power control element 32 to turn off the power and notifies the DSP to be turned off (step S110). When the DSP power supply control element 32 receives an instruction to turn off the power from the FPGA 31, the DSP power supply control element 32 turns off the power of the DSP to be turned off while controlling the power-off sequence of the plurality of types of power to the DSP (step S111). Then, the DSP whose power is cut off enters a dormant state (step S112). Thereafter, the CPU 21 continues to monitor statistical information (step S113).

  Next, the flow of processing when the power is turned on will be described with reference to FIG. As shown in FIG. 9, the CPU 21 of the packet processing device 1 collects statistical information from the FPGA 31 of the voice data processing card 30 and monitors the processing load of the DSP (step S201).

  The CPU 21 determines whether the increase in the “number of packets” per unit time is equal to or greater than a predetermined threshold, whether the increase in the “DSP processing amount” per unit time is equal to or greater than a predetermined threshold, When any condition of “amount” is equal to or greater than a predetermined threshold is satisfied, it is detected that the processing capacity of the audio data processing card is insufficient (step S202).

  The CPU 21 notifies the FPGA 31 of the DSP to be turned on again (step S203). Further, the CPU 21 notifies the software 40 that the power is being turned on again (step S204). Then, the FPGA 31 notifies the DSP power control element 32 of an instruction to turn on the power of the DSP to be turned on again (step S205). Then, the DSP power control element 32 re-powers on the DSP to be powered on while controlling the power-on sequence of the plural types of power to the DSP (step S206).

  When the DSP is turned on again, the DSP starts up (step S207), performs a BOOT process for loading a program (step S208), and notifies the FPGA 31 of a BOOT process completion notification when the BOOT process is completed (step S208). Step S209). Then, the FPGA 31 transfers a BOOT process completion notification to the CPU 21 (step S210).

  Subsequently, when receiving the BOOT process completion notification, the CPU 21 determines a DSP to be powered off and controls to change the distribution table 311a in the FPGA 31 (step S211). Then, when the distribution table 311a is changed (step S212), the FPGA 31 notifies the CPU 21 that the change is completed (step S213). Thereafter, the CPU 21 continues to monitor statistical information (step S214).

[Effect of Example 1]
As described above, the packet processing apparatus 1 monitors the processing load of the DSP that performs signal processing on the received packet, and when the monitored processing load is low, the power supply to the DSP is cut off. Control. For this reason, when the load is low, the power supply to the unnecessary DSP is controlled so that the leakage current of the DSP at the low load is suppressed, and extra consumption to the DSP at the low load is achieved. It is possible to reduce power.

  Further, according to the first embodiment, the packet processing device 1 monitors the packet length and the codec conversion type of the packet as the processing load, and the signal processing unit performs the monitoring based on the monitored packet length and the codec conversion type of the packet. A processing load for converting the packet is calculated, and when the calculated processing load is equal to or less than a predetermined threshold, control is performed to cut off the power supply to the DSP. For this reason, the burden on DSP conversion is calculated from the packet length and the codec conversion type of the packet, and it is appropriately determined whether or not the DSP is under low load, and extra power consumption to the DSP at low load Can be reduced.

  Further, according to the first embodiment, the packet processing apparatus 1 monitors the number of packets received by the DSP as a processing load. When the number of monitored packets is equal to or less than a predetermined threshold, power is supplied to the DSP. Control to cut off. For this reason, it is possible to easily determine whether or not the DSP is at a low load, and to reduce unnecessary power consumption to the DSP at the time of a low load.

  Further, according to the first embodiment, the packet processing device 1 monitors the accumulation amount of the buffer that holds the packet that is signal-processed by the DSP, and when the power supply is cut off, Control to cut off the power supply. For this reason, it is possible to prevent the power from being cut off while the buffer holds the packet.

  Further, according to the first embodiment, the DSP includes the DSP power control element 32 that is configured independently of the other DSPs and that performs sequence control for the power control processing of the DSP. In other words, there are many devices in the card, and power cannot be turned on / off like a simple switch in units of devices, and power supply with multiple power supply types and sequence control is required. For this reason, it is possible to appropriately control the power supply of the DSP by dividing the power supply layer in each DSP and the DSP power supply control element 32 performing sequence control.

  In the first embodiment, the DSP 34 performs codec conversion on all packets sent from the packet switch card 10 to the voice data processing card 30. However, when trying to execute codec conversion of all packets, a case where the packet processing apparatus cannot maintain the power saving setting for a long time is assumed.

  For example, in the first embodiment, when the number of packets sent from the packet switch card 10 to the audio data processing card 30 increases, the increase in packets directly leads to an increase in processing load. In the first place, only a part of the plurality of DSPs 34 is operating in the power saving setting. For this reason, in the first embodiment, when the number of packets starts to increase, it is assumed that the processing load immediately exceeds the threshold value and immediately shifts from the power saving setting to the steady setting. That is, it is assumed that the power saving setting cannot be maintained for a long time.

  For this reason, in the second embodiment, a method for maintaining the power saving setting for a long time by avoiding a situation where the power saving setting immediately shifts to the steady setting will be described. Specifically, in the following, a method will be described in which codec conversion is not performed for all packets, but codec conversion is not performed for some packets. That is, in the second embodiment, a method for giving priority to maintaining the power saving setting for a long time even when the voice quality deteriorates because some packets are not subjected to codec conversion will be described.

  More specifically, as described below, when shifting to the power saving setting, the voice data processing card 30 performs a silence process on some of the received packets. Then, the DSP 34 does not perform codec conversion for the packet for which the silence processing has been executed, and performs codec conversion for the packet for which the silence processing has not been executed. Thereafter, the voice data processing card 30 transmits the packet for which the silence processing has been executed and the packet for which the codec conversion has been executed to the packet switch card 10. In the following, description of the same points as the packet processing device 1 according to the first embodiment will be omitted.

[Packet Processing Device According to Second Embodiment]
The configuration of the packet processing apparatus 2 according to the second embodiment will be described with reference to FIG. FIG. 13 is a block diagram illustrating the configuration of the packet processing apparatus according to the second embodiment. In the example illustrated in FIG. 13, the same reference numerals as those in FIG. 1 are assigned to the same portions as those in the packet processing device 1 according to the first embodiment. As illustrated in FIG. 13, in the packet processing device 2 according to the second embodiment, the buffer control unit 400 includes a buffer control block 500. For example, the buffer control unit 400 includes buffer control blocks 500a to 500f in the example illustrated in FIG. The buffer control blocks 500a to 500f are connected to the DSPs 34a to 34f, respectively. Further, each of the buffer control blocks 500a to 500f is connected to the packet distribution unit 311.

  In the example shown in FIG. 13, the audio data processing card 30 has six DSPs 34 and the buffer control unit 400 has six buffer control blocks 500. However, the present invention is not limited to this. It is not something. For example, the audio data processing card 30 and the buffer control unit 400 may have seven or more DSPs 34 and buffer control blocks 500, and may have five or less DSPs 34 and buffer control blocks 500. In the example shown in FIG. 13, the case where the number of the audio data processing cards 30 and the number of the DSPs 34 are the same has been described as an example. However, the present invention is not limited to this. The number of cards 30 may be smaller than the number of DSPs 34. In this case, the audio data processing card 30 executes processing for a plurality of DSPs 34.

  The buffer control block 500 receives a packet from the packet distribution unit 311. Then, as will be described in detail below, the buffer control block 500 performs a silence process on a part of the received packets and does not send it to the DSP 34. Further, the buffer control block 500 sends the packet that has not been silenced to the DSP 34. As a result, the DSP 34 performs codec conversion on the packet that has not been silenced. Thereafter, the buffer control block 500 transmits to the packet distribution unit 311 the packet for which the silence processing has been executed and the packet after the codec conversion by the DSP 34a.

  The configuration of the buffer control block 500 according to the second embodiment will be described with reference to FIG. FIG. 14 is a block diagram illustrating a configuration of a buffer control block according to the second embodiment. FIG. 14 shows the buffer control block 500a as an example. In FIG. 14, for convenience of explanation, the packet distribution unit 311, the CPU 21, and the DSP 34 a are shown together with the buffer control block 500 a.

  As illustrated in FIG. 14, the buffer control block 500 a includes a transmission buffer 501, a reception buffer 502, a route selection selector 510, a silence processing circuit 520, and a selector control unit 530. Here, the transmission buffer 501 is connected to the route selection selector 510, the selector control unit 530, and the DSP 34a. The transmission buffer 501 stores a packet transmitted from the buffer control block 500a to the DSP 34a. Specifically, the transmission buffer 501 stores the packet transmitted to the transmission buffer 401 by the route selection selector 510, as will be described later. The packets stored in the transmission buffer 501 are subjected to codec conversion by the DSP 34a.

  The reception buffer 502 is connected to the silence processing circuit 520, the DSP 34a, the packet distribution unit 311 and the selector control unit 530. The reception buffer 502 stores a packet transmitted from the buffer control block 500a to the packet distribution unit 311. Specifically, as will be described later, the reception buffer 502 stores a packet that has been silenced by the silencer processing circuit 520 and a packet after codec conversion by the DSP 34a. The packet stored in the reception buffer 502 is then transmitted to the packet distribution unit 311 by the buffer control block 500a. For example, the buffer control block 500a reads and transmits the packet stored in the reception buffer 502 according to the sequence number assigned to the packet. The sequence number is stored in, for example, “User Define” of the packet (see FIG. 15).

  Here, the relationship between the packet distribution unit 311 and the DSP 34a and the buffer control block 500a will be briefly described. First, the relationship between the packet distribution unit 311 and the buffer control block 500a will be briefly described. The packet distribution unit 311 transmits the packet to the buffer control block 500a. Here, the packet transmitted by the packet distribution unit 311 is sent to both the route selection selector 510 and the per-CH counter 534 of the buffer control block 500a. That is, the route selection selector 510 and the CH counter 534 receive the same packet every time the packet is sent by the packet distribution unit 311. In addition, the buffer control block 500 a transmits the packet stored in the reception buffer 502 to the packet distribution unit 311. Thereafter, the packet distribution unit 311 transmits the packet to the packet switch card 10.

  Next, the relationship between the DSP 34a and the buffer control block 500a will be briefly described. The buffer control block 500a transmits the packet stored in the transmission buffer 501 to the DSP 34a, and the DSP 34a performs codec conversion. Then, the DSP 34a transmits the codec converted packet to the buffer control block 500a. Thereafter, in the buffer control block 500a, the reception buffer 502 stores the codec-converted packet.

  Returning to the description of the buffer control block 500a. The route selection selector 510 is connected to the packet distribution unit 311, the transmission buffer 501, the silence processing circuit 520, and the selector control unit 530. The route selection selector 510 has a route toward the transmission buffer 501 and a route toward the silence processing circuit 520. Hereinafter, the route toward the transmission buffer 501 is referred to as a “normal processing route”, and the route toward the silence processing circuit 520 is referred to as a “silence processing route”. When the route selection instruction is received from the selector control unit 530, the route selection selector 510 switches to the route selected by the received route selection instruction.

  Here, the flow of packets in the case of the normal processing route will be described. In this case, the packet is sent to the transmission buffer 501, and the buffer control block 500 a stores the packet in the transmission buffer 501. Thereafter, the buffer control block 500 transmits the packet stored in the transmission buffer 501 to the DSP 34a. Then, the DSP 34a receives the packet stored in the transmission buffer 501, and executes codec conversion. Then, the DSP 34a transmits the codec converted packet to the buffer control block 500a. Thereafter, in the buffer control block 500a, the reception buffer 502 stores the codec-converted packet.

  A packet flow in the case of the silence processing route will be described. In this case, the packet is sent to the silence processing circuit 520, and the silence processing circuit 520 executes the silence processing on the packet received by the buffer control block 500a, as will be described later. Then, the silence processing circuit 520 stores the packet that has been subjected to the silence processing in the reception buffer 502. That is, in the case of the normal processing route, the DSP 34a performs codec conversion, and in the case of the silence processing route, the silence processing circuit 520 executes the silence processing.

  The silence processing circuit 520 is connected to the reception buffer 502 and the route selection selector 510. Silencer processing circuit 520 performs a signalless process on a packet selected as a signalless process target. Specifically, the silence processing circuit 520 performs no signal processing on the packet sent by the route selection selector 510 via the silence processing route. Then, the silence processing circuit 520 stores the packet that has been subjected to the silence processing in the reception buffer 502.

  Here, an example of the silence process according to the second embodiment will be described with reference to FIG. FIG. 15 is a diagram illustrating an example of a silence process according to the second embodiment. Here, 600 in FIG. 15 indicates the packet after the silencing process. The “Card ID” 601 in FIG. 15 includes information indicating the packet switch card 10 that is a packet transmission source. “CH No” of 602 in FIG. 15 includes information indicating a voice channel. “LENGTH” 603 in FIG. 15 includes information indicating the packet length. “CODEC” 604 in FIG. 15 includes information indicating the codec type of the packet. “User Define” 605 in FIG. 15 includes information about a user who is a transmission source of a packet and a sequence number. The sequence number is given by the device that is the packet transmission source. Reference numeral 606 in FIG. 15 denotes an area in which audio information is stored. In the example illustrated in FIG. 15, 606 in FIG. 15 illustrates the case where the data of all the areas is “0”.

  Here, the device that is the transmission source of the packet is, for example, a device that belongs to an ATM (Automated Teller Machine) network or an STM (Synchronous Transfer Mode) network. In the following description, a case where the packet transmission source device is a device belonging to, for example, an ATM network or an STM network will be described as an example. However, the present invention is not limited to this, and other devices may be used. There may be. For example, a device belonging to a network different from the ATM network or the STM network may be used.

  The silence processing circuit 520 converts the information indicating the codec type included in the packet into information indicating the codec type after the codec conversion. For example, a case where the buffer control block 500a receives a packet of the codec type “1” and the DSP 34a converts the packet of the codec type “1” into the codec type “2” will be described as an example. In this case, the silence processing circuit 520 changes the codec type of the packet from “1” to “2”. Further, the silence processing circuit 520 sets the sound information included in the packet to silence. Specifically, the silence processing circuit 520 converts all data in the area where the audio information is stored into a predetermined fixed value. For example, in the example illustrated in FIG. 15, the silence processing circuit 520 converts all the data in the area where the audio information is stored into “0”.

  When the packet has a flag area for storing flag information indicating whether or not the codec conversion is completed, the silence processing circuit 520 changes the flag information stored in the flag area. That is, the silence processing circuit 520 stores flag information indicating that the codec conversion by the DSP 34a is completed in the flag area.

  In this way, the silence processing circuit 520 changes the packet data formally without actually executing codec conversion. Here, the silence processing circuit 520 does not change the “User Define” data, and does not change the sequence number included in the “User Define”. As a result, the buffer control block 500a transmits the packet from the reception buffer 502 according to a series of sequence numbers regardless of whether the packet has been silenced by the silencer processing circuit 520 or the packet after codec conversion by the DSP 34a. .

  Returning to the description of FIG. The selector control unit 530 is connected to the CPU 21, DSP 34 a, packet distribution unit 311, reception buffer 502, and route selection selector 510. As will be described in detail below, the selector control unit 530 selects a packet to be silenced based on the settings made by the CPU 21 and sends the selected packet to the silence processing circuit 520. The path selection selector 510 is controlled.

  Here, the relationship between the CPU 21 and the buffer control block 500a will be briefly described. As shown in “Statistical information 3” in FIG. 14, the buffer count 533 of the buffer control block 500 a sends the accumulation amount of the transmission buffer 501 and the reception buffer 502 to the CPU 21. Further, as shown in “statistical information 4” in FIG. 14, the counter for each channel 534 sends the count number for each voice channel to the CPU 21. Here, the information sent to the CPU 21 by the buffer count 533 and the CH counter 534 is a process for determining whether the power saving determination unit 21a of the CPU 21 can shift from the steady setting to the power saving setting. This is used for determining whether to return to the steady setting from.

  Returning to the description of the selector control unit 530. In the example illustrated in FIG. 14, the selector control unit 530 includes a silence setting register 531, a silence rate setting register 532, a buffer count 533, a CH counter 534, and a silence determination circuit 535. Here, the silence setting register 531 stores setting information indicating whether or not to execute the silence process. For example, the silence setting register 531 stores “1” when the silence process is executed, and stores “0” when the silence process is not executed.

  The setting information stored by the silence setting register 531 is used by the silence determination circuit 535. The setting information stored by the silence setting register 531 is stored by the CPU 21. That is, the CPU 21 controls whether or not to perform the silence process by changing the setting information stored in the silence setting register 531.

  The silencing rate setting register 532 stores ratio information indicating the ratio of packets for which silencing processing is executed among the received packets. For example, when silence processing is performed on one packet per 30 packets, the silence rate setting register 532 stores “30”.

  In the following description, the case where the mute rate setting register 532 stores “30” will be described as an example. However, the present invention is not limited to this, and a value of “29” or less may be stored. , “31” or more may be stored, or any value may be stored. In the following description, the case where the mute rate setting register 532 stores the number of times as ratio information will be described as an example. However, the present invention is not limited to this, and information other than the number of times may be stored. For example, the mute rate setting register 532 may store a discard rate (percentage) indicating the proportion of packets discarded.

  Further, the silence rate setting register 532 stores ratio information for each channel. Here, the silence rate setting register 532 may store different ratio information for each channel, or may store the same ratio information for all channels.

  The ratio information stored in the silence rate setting register 532 is used by the silence determination circuit 535 and the CH counter 534. Further, the ratio information stored by the silence rate setting register 532 is stored by the CPU 21. That is, the CPU 21 changes the ratio information stored in the silencing rate setting register 532, thereby controlling the ratio of packets for which silencing processing is executed among the received packets.

  The buffer count 533 counts the accumulated amount of packets accumulated in the transmission buffer 501 and the accumulated amount of packets accumulated in the reception buffer 502. Here, the accumulated amount of the transmission buffer 501 counted by the buffer count 533 is used by the silence determination circuit 535 and the CPU 21. The accumulated amount of the transmission buffer 501 counted by the buffer count 533 is used by the silence determination circuit 535. Further, the accumulation amount of the reception buffer 502 counted by the buffer count 533 is used by the CPU 21.

  The per-CH counter 534 counts the number of packets for each channel using the ratio information stored in the silence rate setting register 532. The count number counted by the CH counter 534 is used by the silence determination circuit 535 and the CPU 21.

  For example, the case where “30” is stored in the mute rate setting register 532 and a packet of the channel “1” is received will be described. In this case, the CH counter 534 repeats counting the number of packets between “1” and “30”. More specifically, when receiving a packet, the per-CH counter 534 first counts that the number of packets is “1”, and then counts “2”. Similarly, the CH counter 534 counts the number of packets until it reaches “30”. Here, the counter for each CH 534 counts to “30”, and counts that the count number is “1” when counting next time. The CH counter 534 again counts the number of packets until it reaches “30”.

  In addition, the CH counter 534 notifies the silence determination circuit 535 of the count every time it counts. For example, when the packet number of the channel “1” is counted as “1”, the fact that the number of packets of the channel “1” is “1” is notified. Similarly, when the number of packets for channel “1” is counted as “30”, it is notified that the number of packets for channel “1” is “30”.

  In the following, a case will be described as an example where the CH counter 534 notifies the silence determination circuit 535 of the count every time it is counted, but the present invention is not limited to this. For example, the per-CH counter 534 may notify every time the count is indicated, instead of notifying every time it counts. For example, the CH counter 534 may notify that the count number is “30” every time the count number becomes “30”.

  When the DSP power supply control element 32 cuts off the power supply to a part of the plurality of DSPs 34, the silence determination circuit 535 selects a predetermined percentage of the received packets as a signalless processing target. Specifically, the silence determination circuit 535 selects the signal to be silenced based on the count number counted by the CH counter 534 and the ratio information stored in the silence rate setting register 532.

  For example, a case where “30” is stored in the mute rate setting register 532 will be described. In this case, the silence determination circuit 535 selects a pocket at a rate of 1 out of 30 packets for each channel. For example, the silence determination circuit 535 selects a packet corresponding to the count number “30” for the channel “1” each time the count number “30” for the channel “1” is notified by the per-CH counter 534. . Similarly, the silence determination circuit 535 selects a packet for every other channel when the count number “30” is notified.

  Further, the silence determination circuit 535 sends a route selection instruction to the route selection selector 510 so that the selected packet is sent to the silence processing circuit 520. Specifically, the silence determination circuit 535 sends a route selection instruction so that the route for the selected packet becomes the silence processing route, and the route for the packets other than the selected packet becomes the normal processing route. Send directions selection instructions.

  For example, a case where the route selection instruction indicating the normal processing route is the route selection instruction “0” and the route selection instruction indicating the silence processing route is the route selection instruction “1” will be described. Further, a case where packets for channel “1” are continuously received will be described. In this case, when the silence number determination circuit 535 is notified of the count number “30”, the route selection instruction “” is set so that the route for the packet corresponding to the count number “30” becomes the silence processing circuit 520. 1 ”is sent to the route selection selector 510. After that, when the count “1” is notified, the silence determination circuit 535 sends a route selection instruction “0” to the route selection selector 510 so that the route becomes the transmission buffer 501.

  In this way, the silence determination circuit 535 controls based on the ratio information and the count number for each channel so that a predetermined ratio of the received packets is sent to the silence processing circuit 520 instead of the DSP 34a. . As a result, the packet sent to the silence processing circuit 520 instead of the DSP 34a is not sent to the DSP 34a, and codec conversion by the DSP 34a is not executed. In other words, the DSP 34a reduces the number of packets to be processed by the number of packets for which the silence processing is executed.

  The silence determination circuit 535 may store a predetermined threshold value in advance, and may control to send all packets to the DSP 34a when the accumulated amount of the transmission buffer 501 is smaller than the predetermined threshold value. . That is, when the accumulated amount of the transmission buffer 501 is smaller than a predetermined threshold, it is considered that the processing load on the DSP 34a is low and the power saving setting state can be maintained even if the DSP 34a processes all packets. Based on this, the silence determination circuit 535 controls so that all packets are sent to the transmission buffer 501 when the accumulated amount of the transmission buffer 501 is smaller than a predetermined threshold. The predetermined threshold is set in advance by the administrator of the packet processing device 2.

  Further, the silence determination circuit 535 holds a predetermined threshold in advance, and when the accumulated amount of the transmission buffer 501 is larger than the predetermined threshold, a predetermined ratio of packets is sent to the silence processing circuit 520. To control. In other words, when the accumulated amount of the transmission buffer 501 is larger than a predetermined threshold, the processing load on the DSP 34a is high, and when the DSP 34a processes all packets, the power saving setting state cannot be maintained and the state returns to the steady setting state. It is possible to end up. Based on this, the silence determination circuit 535 performs control so that a predetermined proportion of packets are sent to the silence processing circuit 520 when the accumulated amount of the transmission buffer 501 is larger than a predetermined threshold. The predetermined threshold is set in advance by the administrator of the packet processing device 2.

[Processing by buffer control block]
Next, the flow of processing by the buffer control block in the second embodiment will be described with reference to FIG. FIG. 16 is a flowchart illustrating the flow of processing by the buffer control block according to the second embodiment.

  As shown in FIG. 16, in the buffer control block 500, when a packet is received from the packet sorting unit 311 (Yes in step S301), the process is started. Here, when the route of the route selection selector 510 is a normal processing route (Yes at Step S302), the buffer control block 500 stores the packet in the transmission buffer 501 (Step S303).

  In the buffer control block 500, codec conversion by the DSP 34 is executed (step S304). That is, the buffer control block 500 transmits the packet stored in the transmission buffer 501 to the DSP 34a, and the DSP 34a performs codec conversion. That is, the DSP 34a performs codec conversion on the packet stored in the transmission buffer 501. Then, the DSP 34a stores the codec converted packet in the reception buffer 502 (step S305).

  On the other hand, returning to step S302, the case where the route of the route selection selector 510 is not the route toward the transmission buffer 501 will be described (No in step S302). That is, a case where the route of the route selection selector 510 is a silence processing route will be described. In this case, the buffer control block 500 performs a silence process by the silence process circuit 520 (step S306). That is, for example, the silence processing circuit 520 changes the codec type of the header information to a value indicating the codec type after the codec conversion by the DSP 34a, and converts all the data in the area where the audio information is stored to “0”. Then, the silence processing circuit 520 stores the packet that has been subjected to the silence processing in the reception buffer 502 (step S307).

  That is, for example, when the ratio setting is “30”, the DSP 34 performs codec conversion for the packets corresponding to the count numbers “1” to “29”, and the packets corresponding to the count number “30”. The silence processing circuit 520 executes the silence processing.

  Thereafter, the buffer control block 500 transmits the packet stored in the reception buffer 502 to the packet distribution unit 311 (step S308). That is, the buffer control block 500 transmits a packet that has been silenced or a codec converted packet.

[Processing by Packet Processing Device According to Second Embodiment]
Next, the flow of processing by the packet processing apparatus 2 according to the second embodiment will be described with reference to FIG. FIG. 17 is a sequence diagram illustrating the flow of processing performed by the packet processing apparatus according to the second embodiment. In FIG. 17, for convenience of description, the silence setting register 531 and the silence rate setting register 532 are collectively referred to as “setting registers”.

  In FIG. 17, for the sake of convenience of explanation, a case where the silence determination circuit 535 does not transmit a route selection instruction when the route of the route selection selector 510 is set as a normal processing route will be described as an example. That is, the route of the route selection selector 510 will be described as an example in which the route becomes a silence processing route when a route selection instruction is received, and becomes a normal processing route when a route selection instruction is not received. . In the following, a case where the ratio information is “30” will be described as an example.

  As shown in FIG. 17, the CPU 21 sets the setting information indicating that the silence process is executed in the silence setting register 531 (step S <b> 401), so that the silence process is performed by the silence determination circuit 535. (Step S402). Further, the CPU 21 sets the rate information in the silence rate setting register 532 (step S403), notifies the channel counter 534 of the rate information (step S404), and also notifies the silence determination circuit 535 of the rate information. (Step S405).

  Thereafter, when the buffer control block 500 receives a packet, the per-CH counter 534 counts the number of packets for each channel, and notifies the silence determination circuit 535 of the count for each channel (steps S406 to S411). In the example illustrated in FIG. 17, the CH counter 534 repeats counting between “1” and “30”. In the example illustrated in FIG. 17, the count number notified by the CH counter 534 is described as “CH count number“ n ”(n is the count number)”. The count numbers shown in FIG. 17 are all assumed to be count numbers for the same voice channel.

  When the buffer control block 500 receives a packet, processing described below is performed on the basis of the count number by the CH counter 534 separately from the count processing by the CH counter 534. Hereinafter, the case where the count number by the CH counter 534 is not the count number indicated by the ratio setting and the case where the count number by the CH counter 534 is the count number indicated by the ratio setting will be described separately.

  First, a case where the count number by the CH counter 534 is not the count number indicated by the ratio setting will be described. That is, in the example shown in FIG. 17, this corresponds to the case where the count number is “1” to “29” (step S406, step S408, step S410). In this case, the route of the route selection selector 510 is a normal processing route.

  Here, the route selection selector 510 transmits the packet to the transmission buffer 501 (step S412), and then the buffer control block 500 transmits the packet from the transmission buffer 501 to the DSP 34 (step S413).

  Then, the DSP 34 performs codec conversion (step S414), and transmits the codec converted packet to the buffer control block 500 (step S415). In the buffer control block 500a, the reception buffer 502 stores the codec-converted packet. Thereafter, the FPGA 31 transmits the packet stored in the reception buffer 502 to the packet switch card 10.

  Next, the case where the count number by the CH counter 534 is the count number indicated by the ratio setting will be described. That is, in the example shown in FIG. 17, this corresponds to the case where the count number is “30” (step S407, step S409, step S411). In this case, the silence processing circuit 520 transmits a route selection instruction for setting the silence processing route to the route selection selector 510 (step S416).

  Here, the route selection selector 510 transmits the packet to the silence processing circuit 520 (step S417). Then, the silence processing circuit 520 executes the silence process (step S418), and stores the packet for which the silence process has been completed in the reception buffer 502 (step S419). Thereafter, the FPGA 31 transmits the packet stored in the reception buffer 502 to the packet switch card 10.

[Effect of Example 2]
As described above, according to the second embodiment, the packet processing device 2 monitors the number of received packets. Then, when the power supply to a part of the plurality of DSPs 34 is cut off, the packet processing device 2 sets a predetermined ratio of the received packets as a non-signal processing target based on the number of monitored packets. select. Then, the packet processing device 2 performs a non-signaling process on the packet selected as the non-signaling process target. As a result, it is possible to continue the power saving setting for a long time as compared with the method that does not execute the silencing process.

  The effect of Example 2 is demonstrated using FIG. FIG. 18 is a diagram illustrating the effects of the packet processing apparatus according to the second embodiment. The horizontal axis in FIG. 18 indicates the passage of time, and the vertical axis in FIG. 18 indicates the processing load. Here, a case where the threshold A is set will be described as an example. That is, a case will be described as an example in which the processing shifts to the power saving setting when the processing load of the DSP 34 becomes equal to or less than the threshold A, and the normal setting is performed when the processing load of the DSP 34 becomes larger than the threshold A.

  Further, reference numeral 701 in FIG. 18 indicates a processing load of the DSP 34 when codec conversion is performed on all packets. In other words, the processing load of the DSP 34 when the silencing process is not executed is shown. For example, reference numeral 701 in FIG. 18 indicates a processing load when the DSP 34 executes codec conversion of all 30 packets when 30 packets are received. Further, reference numeral 702 in FIG. 18 corresponds to the processing load of the DSP 34 when codec conversion of some packets is not executed. In other words, the processing load of the DSP 34 when the silence process is executed is shown. For example, in the case of 702 in FIG. 18, when 30 packets are received, the DSP 34 performs codec conversion of 29 packets out of 30 packets, and the remaining one packet is silenced. Processing load.

  A value C in FIG. 18 indicates a point in time when the processing load indicated by 701 in FIG. A value D indicates a point in time when the processing load indicated by 702 in FIG. Here, the threshold B is a value corresponding to the value D in the processing load indicated by 701 in FIG. That is, it shows a point in time when the processing load of the DSP 34 exceeds the threshold A in the case where the silence process is performed.

  In addition, the processing load on the DSP 34 when performing silence processing is lighter than the processing load on the DSP 34 when performing codec conversion on all packets. Accordingly, as shown in FIG. 18, the value D indicating the point in time when 702 in FIG. 18 exceeds the threshold A is the point before the value C indicating the point in time when 701 in FIG.

  As shown in FIG. 18, when the silence processing is not executed, the processing load of the DSP 34 becomes larger than the threshold A at the value C stage. As a result, the packet processing device 2 shifts from the steady setting to the power saving setting at the stage of the value C. On the other hand, when the silence process is executed, the DSP 34 has a processing load on the DSP 34 that is greater than the threshold A at the stage of the value D that is later in time than the value C. As a result, the packet processing device 2 shifts from the steady setting to the power saving setting at the value D stage. That is, by executing the silence processing, the packet processing device 2 can increase the time from when the power saving setting is started until it returns to the steady setting. That is, the power saving setting can be continued for a longer time.

  Moreover, as a result of continuing the power saving setting for a longer time, it is possible to reduce power consumption. For example, an example of the amount of power consumption reduction will be described using a case where the power consumption per unit time of the audio data processing card is reduced by 20% when shifting to the power saving setting. Further, the case where the power consumption per audio data processing card is “45 W” will be described. Moreover, when shifting to a power saving setting, it demonstrates using the case where it shifts for 6 hours per day. Further, the case where the duration of the power saving setting is increased by 3 hours by executing the invalidation process will be described.

  In this case, the audio data processing card consumes an amount of power of “45 (W) × 24 (hours) = 1.080 (kWh)” in one day when it does not shift to the power saving setting. When the voice data processing card shifts to the power saving setting and does not execute the invalidation processing, “45 (W) × (1−0.2) × 6 (time) +45 (W) × 18 ( Time) = 1.026 (kWh) is consumed per day, and the voice data processing card shifts to the power saving setting and executes the invalidation process, "45 (W) x A power amount of (1-0.2) × 9 (hours) +45 (W) × 15 (hours) = 0.999 (kWh) is consumed per day.

  That is, even when the silence process is not executed, when shifting to the power saving setting, the power consumption can be reduced by about 5% per day. When the silencing process is executed, it is possible to further reduce power consumption by about 3%.

  In addition, according to the second embodiment, the silence processing circuit 520 does not change the information indicating the area where the audio information is stored or the codec type except for the change, so that the process is performed without any packet loss. Is possible. In other words, in the silence process by the silence process circuit 520, no change is made to the sequence number or User Define, and an apparatus using a packet for which the silence process has been executed generates an error or an alarm. There is no.

  As described above, according to the second embodiment, although the voice quality is lowered due to the silence, it is possible to extend the duration of the power saving setting. In addition, it is known that although voice quality is reduced due to silence, even if 5% or less of voice data is lost, there is no effect on the call. Considering this, for example, by setting a value of “20” or more as the ratio setting, it is possible to extend the duration of the power saving setting without substantially affecting the voice quality. Note that the value “20” is merely an example, and an arbitrary value may be used.

  Although the embodiments of the present invention have been described so far, the present invention may be implemented in various different forms other than the embodiments described above. Therefore, another embodiment included in the present invention will be described below as a second embodiment. In the following description, the power saving setting described in the first embodiment is referred to as “power saving setting”, and the setting for executing the silence processing at the time of the power saving setting described in the second embodiment is referred to as “silence setting”. .

[Switch between steady setting and power saving setting]
For example, in the first embodiment, the CPU 21 has described the steady setting and the power saving setting. However, the present invention is not limited to this. For example, the CPU 21 may switch between a steady setting, a power saving setting, and a silence setting. Note that the power consumption setting is smaller than the steady setting, and the silence setting is smaller than the power saving setting.

[Receive buffer]
Further, for example, the reception buffer 502 may include a buffer used when the process of storing the packet from the DSP 34a and the process of storing the packet from the silence processing circuit 520 compete. In this case, for example, the buffer control block 500a gives priority to the process of storing the packet from the DSP 34a in the reception buffer 502, and stores the packet from the silence processing circuit 520 in the buffer. The reception buffer 502 executes processing for storing the packet from the silence processing circuit 520 after the processing for storing the packet from the DSP 34a in the reception buffer 502 is completed. Note that the present invention is not limited to this, and priority may be given to processing for storing packets from the silence processing circuit 520.

[Change settings]
Further, for example, when the bucket processing apparatus shifts from the power saving setting to the steady setting, the number of DSPs that supply power may be gradually reduced. Further, the bucket processing apparatus may gradually increase the number of DSPs that supply power when shifting from the steady setting to the power saving setting. That is, for example, the packet processing apparatus has a plurality of stages of power saving settings in which the number of DSPs supplying power is different, and a threshold is associated with each power saving setting. The packet processing apparatus may use a plurality of stages of power saving settings depending on the processing load.

[System configuration]
Further, each component of each illustrated apparatus is functionally conceptual, and does not necessarily need to be physically configured as illustrated. In other words, the specific form of distribution / integration of each device is not limited to that shown in the figure, and all or a part thereof may be functionally or physically distributed or arbitrarily distributed in arbitrary units according to various loads or usage conditions. Can be integrated and configured. For example, the packet monitoring unit 310a and the weight determination unit 310b may be integrated. Furthermore, all or a part of each processing function performed in each device may be realized by a CPU and a program that is analyzed and executed by the CPU, or may be realized as hardware by wired logic.

  In addition, among the processes described in the present embodiment, all or part of the processes described as being automatically performed can be performed manually, or the processes described as being performed manually can be performed. All or a part can be automatically performed by a known method. In addition, the processing procedure, control procedure, specific name, and information including various data and parameters shown in the above-described document and drawings can be arbitrarily changed unless otherwise specified.

[program]
The power control method described in the present embodiment can be realized by executing a program prepared in advance on a computer such as a personal computer or a workstation. This program can be distributed via a network such as the Internet. The program can also be executed by being recorded on a computer-readable recording medium such as a hard disk, a flexible disk (FD), a CD-ROM, an MO, and a DVD and being read from the recording medium by the computer.

1 Packet Processing Device 10 Packet Switch Card 11 Switch Function LSI
11a Packet number measurement unit 20 Control card 21 CPU
21a Power saving determination unit 30 Audio data processing card 31 FPGA
310 Transmission / Reception Unit 310a Packet Monitoring Unit 310b Weighting Determination Unit 311 Packet Distribution Unit 311a Distribution Table 312 Buffer Control Unit 312a Buffer Amount Measurement Unit 32 DSP Power Supply Control Element 33 Regulator 34 DSP
35 Memory 36 Overall Power Control Element 2 Packet Processing Device 400 Buffer Control Unit 500 Buffer Control Block 501 Transmission Buffer 502 Reception Buffer 510 Route Selection Selector 520 Silencer Processing Circuit 530 Selector Control Unit 531 Silencer Setting Register 532 Silencer Rate Setting Register 533 Buffer count 534 Counter for each channel 535 Silence determination circuit

Claims (8)

A signal processing unit for signal processing the received packet;
A processing load monitoring unit for monitoring the processing load of the signal processing unit;
When the processing load monitored by the processing load monitoring unit is a low load, a power control unit that controls to cut off the power supply to the signal processing unit,
A packet processing apparatus comprising: The processing load monitoring unit monitors a packet length and a packet conversion type as the processing load,
Based on the packet length monitored by the processing load monitoring unit and the conversion type of the packet, the signal processing unit further includes a processing load calculating unit that calculates a processing load for converting the packet,
The power supply control unit controls the power supply to the signal processing unit to be cut off when the processing load calculated by the processing load calculation unit is a predetermined threshold value or less. The packet processing device according to 1. The processing load monitoring unit monitors the number of packets received by the signal processing unit as the processing load,
The power supply control unit controls the power supply to the signal processing unit to be cut off when the number of packets monitored by the processing load monitoring unit is a predetermined threshold value or less. 3. The packet processing device according to 1 or 2. The processing load monitoring unit monitors an accumulation amount of a packet holding unit that holds a packet that is signal-processed by the signal processing unit,
When the power supply to the signal processing unit is cut off, the power control unit cuts off the power supply to the signal processing unit after the accumulated amount of the packet holding unit monitored by the processing load monitoring unit is lost. The packet processing device according to claim 1, wherein the packet processing device is controlled as follows. The signal processing unit is configured such that the power supply layer is independent of other signal processing units,
The packet processing device according to claim 1, further comprising a power control element that performs sequence control on the power control processing of the signal processing unit. A processing load monitoring step for monitoring a processing load of a signal processing unit that performs signal processing on the received packet;
When the processing load monitored by the processing load monitoring step is a low load, a power control step for controlling to cut off the power supply to the signal processing unit,
A power supply control method comprising: A packet number monitoring unit for monitoring the number of received packets;
When power supply to a part of the plurality of signal processing units is cut off by the power control unit, a predetermined ratio of packets received from the number of packets monitored by the packet number monitoring unit A packet selection unit to select as a non-signaling processing target;
The packet processing apparatus according to claim 1, further comprising: a non-signaling processing unit configured to perform a non-signaling process on a packet selected as a non-signaling process target by the packet selection unit. A packet number monitoring step for monitoring the number of received packets;
When power supply to some of the plurality of signal processing units is interrupted by the power control step, a predetermined ratio of packets received based on the number of packets monitored by the packet number monitoring step A packet selection step to select as a non-signaling processing target;
The power supply control method according to claim 6, further comprising: a non-signaling process step of performing a non-signaling process on the packet selected as a non-signaling process target in the packet selection step.

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