JP2010252198A - Delay measuring instrument - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To accurately measure the amount of delay of an object to be measured even if the amount of delay in an instrument is varied. <P>SOLUTION: A trigger generating section 22 generates a delay measurement start trigger signal Tg in synchronization with an SDH frame head timing. A transmission data processing section 23 generates and transmits to a measuring object 1 an SDH frame with an error inserted at a predetermined position of a payload area on receipt of the trigger signal. A transmission delay amount measuring section 24 measures the time from generation of trigger signal till transmission of head data of the SDH frame as a transmission delay amount. A reception delay amount measuring section 34 measures the time from when the specific SDH frame output from the measuring object 1 is input to a reception data processing section 32 till an arrival at an error detection section 33 as a reception delay amount. A delay calculation section 40 determines the amount of delay of the measuring object 1 by subtracting the sum of the transmission delay amount and the reception delay amount from the time from generation of the trigger signal till the error detection in the error detection section 33. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a technique for measuring a transmission delay time of an SDH frame based on a measurement target of a network or the like that transmits SDH frame data.

  When measuring the transmission delay time as described above, a specific SDH frame generally used for the test is transmitted from the transmission unit to the measurement target, and the specific SDH frame output from the measurement target is received by the reception unit. The time from transmission timing to reception timing is measured.

  However, in an actual measurement apparatus, a transmission delay until a specific SDH frame is transmitted after the start of measurement is instructed, or until it is detected that a specific SDH frame is received after the SDH frame is received. If there is a reception delay and the delay amount inside these devices is not known, it is impossible to accurately grasp the delay amount of the actual measurement object.

  The amount of delay inside the apparatus described above is the time required to generate SDH frame data for transmission and the time required to analyze the received SDH frame and detect whether it is a specific SDH frame. This time can be obtained by calculating the number of clocks of the system required for data generation and frame analysis in advance, and conventionally, the amount of delay obtained based on the calculated value is subtracted from the total delay amount. Was seeking the amount of delay.

JP 2003-43174 A

  However, the number of clocks required for the above processing changes due to the addition or reduction of modules for generating and analyzing SDH frame data, and it is inefficient to calculate it one by one. Measurement errors due to mistakes will occur.

  An object of the present invention is to solve this problem and to provide a delay measurement device that can accurately measure the delay amount of an SDH frame depending on a measurement object even if the delay amount inside the device varies.

In order to achieve the above object, a delay measuring apparatus according to claim 1 of the present invention comprises:
A trigger generation unit (22) for generating a trigger signal for delay measurement activation in synchronization with the SDH frame head timing;
A transmission data processing unit (23) that receives the trigger signal, generates a specific SDH frame in which an error is inserted at a predetermined position in the payload area, and transmits the generated SDH frame to a measurement target;
A transmission delay amount measuring unit (24) for measuring a time from when the trigger signal is generated until the head data of the specific SDH frame is output from the transmission data processing unit as a transmission delay amount;
A reception data processing unit (32) for receiving the specific SDH frame output from the measurement object and analyzing the data;
An error detection unit (33) for detecting an error at the predetermined position in the payload area of the specific SDH frame analyzed by the reception data processing unit;
A reception delay amount measurement unit (34) that measures a time from when the specific SDH frame is input to the reception data processing unit until it reaches the error detection unit as a reception delay amount;
A delay amount calculation unit that calculates the delay amount of the measurement target by subtracting the sum of the transmission delay amount and the reception delay amount from the time from when the trigger signal is generated until an error is detected by the error detection unit ( 40).

A delay measuring device according to claim 2 of the present invention is the delay measuring device according to claim 1,
The transmission data processing unit is configured to insert an error bit using a common trigger timing for all channels of the SDH frame.

A delay measuring device according to claim 3 of the present invention is the delay measuring device according to claim 1 or 2,
The transmission data processing unit inserts and transmits error bits continuous for the number of bits corresponding to the time from when the trigger signal is received until an error bit is inserted into the SDH frame,
The error detection unit detects a length of the error bit, and the delay amount calculation unit calculates the delay time by performing correction for a time corresponding to the detected error bit length. To do.

  With this configuration, in the delay measurement device of the present invention, the delay due to the generation processing of a specific SDH frame for delay measurement in which an error is inserted at a predetermined position in the payload area and the delay amount due to reception data processing change. Even so, the delay amount of the measurement target can be accurately measured.

  Further, when error bits are inserted at the same timing for all channels of the SDH frame, the delay amount for all channels can be measured based on one reference timing.

  In addition, when the error bit for the time from the trigger timing until the error bit is actually inserted is inserted and transmitted, the above time can be determined by counting the number of errors on the receiving side. The delay time of minutes can be easily corrected.

  In particular, in the case of multi-channel, the time from the trigger timing until the actual error bit is inserted varies, as compared to, for example, sending such information for several thousand channels from the transmission unit to the delay amount calculation unit. The number of wires in the data processing and measurement system can be greatly simplified.

The figure which shows the structure of embodiment of this invention Basic configuration diagram of SDH frame generation Configuration diagram for inserting errors into the channel at a common timing Diagram showing structure of SDH frame

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 shows a configuration of a delay measuring apparatus 20 to which the present invention is applied.

The delay measurement device 20 includes a transmission unit 21 and a reception unit 31.
The transmission unit 21 receives a trigger generation unit 22 that generates a trigger signal Tg for starting delay measurement in synchronization with the SDH frame head timing, and the trigger signal Tg. And a transmission data processing unit 23 for generating and transmitting the SDH frame to the measurement target.

  The specific SDH frame is a frame in which the trigger signal Tg is synchronized with the SDH frame head pulse, and an error bit is inserted at a predetermined position in the payload area, for example, with the head pulse as a reference.

  The specific SDH frame generated by the transmission data processing unit 23 is transmitted to the measurement target 1 such as an SDH network.

  The transmission delay amount measurement unit 24 includes a time t0 when the trigger signal Tg is output, and a time t1 when the top data (edge timing of the frame top pulse) of the specific SDH frame generated by the transmission data processing unit 23 is transmitted. Difference ΔTt is measured as a transmission delay amount.

  The transmission delay amount storage unit 25 stores the transmission delay amount ΔTt measured by the transmission delay amount measurement unit 24.

  On the other hand, the reception unit 31 receives a specific SDH frame input via the measurement object 1 by the reception data processing unit 32 and performs a process (data decomposition process) reverse to that of the transmission data processing unit 23, Is output to the error detection unit 33.

  The error detection unit 33 detects an error inserted at a predetermined position in a payload area of a specific SDH frame for delay measurement with respect to input data.

  The reception delay amount measurement unit 34 calculates the difference ΔTr from the time t2 (edge timing of the SDH frame head pulse) when the head data of the received SDH frame is input to the time t3 when the error detection unit 33 is reached. Measure as

  The reception delay amount storage unit 35 stores the reception delay amount ΔTr measured by the reception delay amount measurement unit 34.

  The delay amount calculation unit 40 calculates the transmission delay amount from the time (t3−t0) from the time t0 when the trigger signal Tg is generated to the time t3 when the error is detected by the error detection unit 33, as in the following equation. The delay amount Td to be measured is obtained by subtracting the total reception delay amount (ΔTt + ΔTr).

  Td = (t3−t0) − (ΔTt + ΔTr)

  As described above, the delay measuring apparatus 20 according to the embodiment automatically measures the delay amount ΔTt in the transmission unit 21 and the delay amount ΔTr in the reception unit 31, and performs measurement by subtracting the measured internal delay amount. A delay amount Td of 1 is obtained.

  For this reason, even if the time required for data generation due to an increase in the configuration of the transmission unit 21 or the like changes, the delay amount Td of the measurement object 1 can be accurately obtained regardless of the change in the delay amount.

  In the above description, the error bit is inserted at a predetermined position in the payload area of the single channel SDH frame. However, in the case of multi-channel SDH frame data, the error insertion timing differs for each channel. The insertion timing for all channels must be sent separately to the receiving side, which complicates the processing.

  Therefore, in order to accurately measure the delay of a plurality of channels mapped in various ways with reference to a common trigger signal, it is necessary to insert error bits for all channels simultaneously. This will be described below.

  As shown in FIG. 2, the basics of SDH frame generation are based on the SDH frame head pulse repeated at a period uniquely determined by the bit rate. There is an area called AUG immediately below the SDH frame, and there is an area called AU4 or AU3 in the AUG. In AU4, there is the largest container called VC4, and in AU3, there is a container called VC3.

  Further, the VC4 container has TUG3, and TUG3 has TU3 or TUG2. There is LOVC3 in TU3, and TU2 or TU12 or TU11 in TUG2.

  On the other hand, VC3 includes TUG2, and TUG2 includes TU2, TU12, or TU11. Further, in TU2, TU11, and TU12, there are containers VC2, VC12, and VC11, respectively. VC11 is the smallest container.

  The reference for all timings is the SDH frame head pulse, and the above-described container areas are also generated based on this frame head pulse.

  However, the area of the container VC11 that is the smallest is created from the information of TU11, which is one area larger than that, the information of TU11 is created from the information of TUG2, the information of TUG2 is created from TUG3 or VC3, and the information of TUG3 Information is made from VC4, VC4 or VC3 information is made from AU4 or AU3, AU4 or AU3 information is made from AUG, and AUG is made from an SDH frame.

  That is, the processing steps required to generate the VC4 region and the processing steps required to generate the VC11 region are different.

  A container has an overhead area and a payload area, and errors need to be inserted into the payload area as described above. Since VC4 and VC11 differ in the number of steps until the payload area is specified, the error insertion timing differs.

  Therefore, as shown in FIG. 3, by providing a delay adjustment circuit (not shown) in the preceding stage of the payload insertion circuit, payload insertion is made common to all mappings and all channels, and error insertion instruction timing control is applied to the circuit. The error insertion instruction timing is made common to all mappings and all CHs simultaneously.

  In addition to making the error insertion timing common as described above, the error insertion timing is synchronized with the SDH frame head pulse (that is, an error is inserted at the insertion possible timing immediately after the SDH frame head. Therefore, the SDH frame head pulse that has already been passed as a reference for all timings is used as a trigger, and a new trigger signal indicating error insertion timing is not required.

  The SDH frame has a frame structure as shown in FIG. 4 and is transmitted in order from row 1 to row 9 and in order of clm1 to clm270 for each row.

  As described above, the error insertion instruction timing is synchronized with the SDH frame head pulse common to all mappings and all channels. However, in each container, it is necessary to wait until the timing of the payload area first after the error insertion instruction. The waiting time varies depending on the type of container and the position of the payload area of each container when an error is inserted. This waiting time is included in the measurement result as a delay measurement error.

  Therefore, the time Tk from the common error insertion instruction timing until each container actually executes error insertion is measured for each container, and information on the measurement time Tk is embedded in the container at the time of error insertion. This process is performed by the transmission data processing unit 23. As a specific process, the number of error bits corresponding to the measurement time Tk is continuously inserted.

That is, the measurement time Tk is the cycle Tc of the system clock of the transmission data processing unit 23, and the integer is U.
Tk = U · Tc
It is represented by

  Since this integer U is a value representing the measurement time Tk for each channel, error bits corresponding to this integer U are inserted.

  In this way, the duration Tk is obtained from the number of errors U detected by the error detection unit 33, and in the delay amount calculation unit 40, the delay amount ΔTt of the transmission unit 21 and the delay amount ΔTr of the reception unit 31 are calculated. Highly accurate delay measurement using the following equation, where the sum is the correction value H1, the error duration is Tk, the time when the trigger signal Tg is output from the trigger generator 22 is t0, and the error detection start time at the error detector 33 is t4. Can be realized.

  Delay amount Td = (t4−t0) − (H1 + Tk)

  In addition, it is possible to embed errors in the container from the error insertion instruction timing until the actual execution of error insertion in the container, obtain the number of errors in the receiving unit 21, and use the value as a correction value. A single channel delay measurement is also possible.

  DESCRIPTION OF SYMBOLS 1 ... Measurement object, 20 ... Delay measuring apparatus, 21 ... Transmission part, 22 ... Trigger generation part, 23 ... Transmission data processing part, 24 ... Transmission delay amount measurement part, 25 ... Transmission delay amount storage , 31... Reception unit, 32... Reception data processing unit, 33... Error detection unit, 34... Reception delay amount measurement unit, 35.

Claims (3)

A trigger generation unit (22) for generating a trigger signal for delay measurement activation in synchronization with the SDH frame head timing;
A transmission data processing unit (23) that receives the trigger signal, generates a specific SDH frame in which an error is inserted at a predetermined position in the payload area, and transmits the generated SDH frame to a measurement target;
A transmission delay amount measuring unit (24) that measures a time from when the trigger signal is generated until the head data of the specific SDH frame is output from the transmission data processing unit as a transmission delay amount;
A reception data processing unit (32) for receiving the specific SDH frame output from the measurement object and analyzing the data;
An error detection unit (33) for detecting an error at the predetermined position in the payload area of the specific SDH frame analyzed by the reception data processing unit;
A reception delay amount measurement unit (34) that measures a time from when the specific SDH frame is input to the reception data processing unit until it reaches the error detection unit as a reception delay amount;
A delay amount calculation unit for obtaining a delay amount of the measurement target by subtracting the sum of the transmission delay amount and the reception delay amount from the time from when the trigger signal is generated until an error is detected by the error detection unit ( 40).   The delay measurement apparatus according to claim 1, wherein the transmission data processing unit is configured to insert an error bit using a common trigger timing for all channels of the SDH frame. The transmission data processing unit inserts and transmits error bits continuous for the number of bits corresponding to the time from when the trigger signal is received until an error bit is inserted into the SDH frame,
The error detection unit detects a length of the error bit, and the delay amount calculation unit calculates the delay time by performing correction for a time corresponding to the detected error bit length. The delay measuring device according to claim 1 or 2.

Images