JP2010251669A - Electrostatic discharge protection circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an ESD protection circuit which prevents destruction of a circuit within a semiconductor caused by the ESD, and which avoids deterioration of a radio frequency characteristic in the circuit within the semiconductor even in a radio frequency range such as a millimeter-wave band or a quasi-millimeter wave band. <P>SOLUTION: The electrostatic discharge protection circuit, which is connected to a semiconductor integrated circuit, protects the semiconductor integrated circuit from electrostatic discharge. The electrostatic discharge protection circuit includes conductive semiconductor substrate 10, a dielectric layer 13b formed above the conductive semiconductor substrate 10, and a second wiring layer 15 formed on the surface of the dielectric layer 13b. The second wiring layer 15 includes a first signal line 17 which is connected at its one end with a pad and at the other end with the semiconductor integrated circuit, and a second signal line 18 which is connected at its one end with the first signal line 17 and is grounded at the other end. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an electrostatic discharge protection circuit mounted on an MMIC (Monolithic Microwave Integrated Circuit) chip in a high-frequency semiconductor device such as various communication devices and radars.

  In recent years, miniaturization of Si-based semiconductor devices has progressed, and mass production of 65 nm CMOS (Complementary Metal Oxide Semiconductor) has also been realized. With the miniaturization of CMOS technology, the usable frequency of transistors will gradually increase, and research and development will be advanced for applications in the quasi-millimeter and millimeter-wave bands such as in-vehicle radar and HDMI (High-Definition Multimedia Interface) wireless systems. ing.

  By the way, an electrostatically charged object comes into contact with another object, and a discharge phenomenon that occurs between these objects is called ESD (Electro Static Discharge), and a surge (ESD surge) generated by ESD is input to a semiconductor integrated circuit. Then, there is a possibility that elements such as transistors constituting the semiconductor integrated circuit are destroyed. Typical ESD models include HBM (Human Body Model) modeling discharge from a charged human body to a semiconductor element, MM (Machine Model) modeling discharge from a charged device to a semiconductor element, and the semiconductor itself. There are three types of CDM (Charge Device Model) that model how a charged electric charge is discharged to a grounded object. Specifically, the ESD surge generated by the HBM has a frequency of about 6 to 7 MHz, the ESD surge generated by the MM has a frequency of about 30 MHz, and the ESD surge generated by the CDM has a frequency of about 1 GHz. It can be said that the signal is generated in a relatively low frequency region compared to the high frequency region.

  ESD causes thermal breakdown because a high current is applied to a semiconductor element in a short time. In addition, in the case of a MOS transistor or the like, dielectric breakdown is caused by applying a high electric field due to ESD to a gate oxide film. Has become a major issue in terms of device reliability.

  In order to prevent the destruction of the semiconductor element due to the ESD, a configuration using an ESD protection circuit and a capacitor immediately before the semiconductor integrated circuit is known (for example, Patent Document 1).

  FIG. 8 is a circuit diagram showing a configuration of a conventional ESD protection circuit using a protection diode and a capacitor. The ESD protection circuit 103 includes an ESD protection diode 104 connected between the high-frequency signal line and the power supply voltage pad, and an ESD protection diode 105 connected between the high-frequency signal line and GND. The ESD surge input from the pad 101 is removed.

  Of the ESD surges input from the high-frequency signal input / output pad, the positively charged ESD surge passes through the ESD protection diode 104, and the negatively charged ESD surge passes through the ESD protection diode 105. Therefore, since any ESD surge that is charged is discharged to the outside, it is not input to the semiconductor internal circuit 102. On the other hand, since the voltage amplitude of the high-frequency signal input from the high-frequency signal input / output pad is small, the diode does not turn on. Therefore, the high frequency signal input from the high frequency signal input / output pad is not emitted to the outside but input to the semiconductor internal circuit. However, there is a problem that high-frequency signal loss is large due to the capacitance of the ESD protection diodes 104 and 105.

  Here, in addition to the ESD protection circuit 103, a capacitor 106 such as a MIM (Metal-Insulator-Metal) capacitive element is inserted between the ESD protection circuit 103 and the semiconductor internal circuit 102, thereby reducing the loss of high-frequency signals. To reduce. The capacitor 106 has a role of cutting a DC signal first. Furthermore, the capacitor 106 is arranged in front of the semiconductor internal circuit 102, so that the breakdown voltage of the semiconductor internal circuit 102 is remarkably increased, and the effect of increasing the load capacity of the first stage of the semiconductor internal circuit 102 is added. Increases significantly. Therefore, ESD tolerance is further improved, and the current drive capability of the ESD protection circuit 103 can be greatly reduced. Therefore, since it is not necessary to completely branch the ESD surge current input from the high-frequency signal input / output pad 101 by the ESD protection circuit 103, the size of the ESD protection diodes 104 and 105 can be reduced. Capacity is reduced.

  Thus, by providing the capacitor 106, the capacitance of the ESD protection circuit 103 can be reduced, the high frequency characteristics can be prevented from being deteriorated, and the semiconductor internal circuit 102 can be prevented from being destroyed by ESD.

JP 2003-197754 A

  In the conventional ESD protection circuit, the capacitance of the ESD protection diodes 104 and 105 can be reduced by inserting the capacitor 106 in front of the semiconductor internal circuit 102, thereby suppressing the deterioration of the high frequency characteristics due to the ESD protection circuit. Measures were taken. As described above, in the case of a high frequency signal of about several GHz, it is possible to suppress deterioration of the high frequency characteristics by reducing the capacitance of the ESD protection diodes 104 and 105.

  However, when dealing with a quasi-millimeter wave or a millimeter-wave band high-frequency signal exceeding 50 GHz, the ESD protection diodes 104 and 105 are inserted as shown in FIG. There is a problem of deterioration.

  FIG. 9 is a diagram illustrating the occurrence of loss due to the capacitance component of the ESD protection circuit 103.

  FIG. 9A is a diagram schematically showing the capacitance generated in the ESD protection circuit 103. FIG. In the figure, the capacitance value of the capacitor 111 is the capacitance value of the ESD protection diode 104, and the capacitance value of the capacitor 112 is the capacitance value of the ESD protection diode 105. In FIG. 9, the same components as those in FIG.

  FIG. 9B is a graph showing the gain when the capacitance values of the capacitors 111 and 112 are changed. In the figure, for simplicity, the capacitors 111 and 112 are simulated as ideal capacitor elements, and the high frequency characteristics are confirmed. The semiconductor internal circuit 102 uses an input / output 50Ω matching single-stage amplifier. When the capacitors 111 and 112 are not connected, for example, the gain in the 60 GHz band is 4.4 dB.

  The capacitance values of the capacitors 111 and 112 are exactly the same, and changes in the gain of the one-stage amplifier that is the semiconductor internal circuit 102 when the capacitance values are changed are shown. The vertical axis represents the gain of the one-stage amplifier in the semiconductor internal circuit 102 for the signal input to the high-frequency signal input / output pad 101, and the horizontal axis represents the capacitance of each of the capacitors 111 and 112. The frequency at this time is the 60 GHz band.

  As a result, it is confirmed that the characteristics are remarkably deteriorated when the capacitances of the capacitors 111 and 112 are about 30 fF.

  In view of the above-described problems, the present invention prevents the destruction of a semiconductor internal circuit due to ESD, and does not cause deterioration of the high frequency characteristics of the semiconductor internal circuit in a high frequency region such as a millimeter wave or quasi-millimeter wave band. Provide a protection circuit.

  In order to solve the above problems, an electrostatic discharge protection circuit of the present invention is an electrostatic discharge protection circuit that is connected to a semiconductor integrated circuit and protects the semiconductor integrated circuit from electrostatic discharge. A first dielectric layer formed above; and a wiring layer formed on a surface of the first dielectric layer, wherein the wiring layer has one end connected to a pad and the other end connected to the pad A first signal line connected to the semiconductor circuit; and a second signal line having one end connected to the first signal line and the other end grounded.

  Thereby, components other than the frequency component corresponding to the line length of the second signal line are removed from the signal generated on the first signal line. Since the signal due to electrostatic discharge is a low-frequency signal of 1 GHz or less, this configuration allows the signal to flow to the ground potential via the second signal line. In other words, a signal due to electrostatic discharge is not input to the semiconductor integrated circuit. As a result, destruction of the semiconductor integrated circuit due to electrostatic discharge can be prevented.

  Further, by setting the line length of the second signal line to a length corresponding to the frequency of the input / output signal of the semiconductor integrated circuit, it is possible to prevent deterioration of the high frequency characteristics of the semiconductor integrated circuit in the electrostatic discharge protection circuit.

  Furthermore, a first ground electrode layer formed on the back surface of the dielectric layer may be provided.

  The first ground electrode layer may be formed on the semiconductor substrate side of the first dielectric layer.

  As a result, leakage of the high-frequency signal transmitted through the first signal line to the semiconductor substrate is prevented, so that loss of the high-frequency signal can be reduced. In addition, when a circuit is formed on the conductive substrate, the influence from the circuit can be blocked by the first ground electrode layer, so that the electrostatic discharge protection circuit is hardly affected by the circuit.

  The electrostatic discharge protection circuit further includes a contact for electrically connecting the first ground electrode layer and the wiring layer via the first dielectric layer, and the other end of the second signal line. May be electrically connected to the first ground electrode layer via the contact.

  Furthermore, a second dielectric layer formed on the wiring layer and a second ground electrode layer formed on the second dielectric layer may be provided.

  Thereby, when the semiconductor integrated circuit is flip-chip mounted, the influence on the input / output signals of the semiconductor integrated circuit from the flip chip mounting substrate and the underfill resin can be reduced.

  Further, in the first dielectric layer and the second dielectric layer, the portion made of the first material is the second in contact with the first signal line or the second signal line. A nanocomposite film dispersed in the material may be included.

  By using a nanocomposite film having a high dielectric constant, the line lengths of the first signal line and the second signal line can be shortened. Therefore, the ESD protection circuit can be reduced in size.

  The particle size of the first material may be 1 nm or more and 200 nm or less. The first material may be ceramics. In this case, the ceramic may be strontium titanate or barium strontium titanate.

  The second material may be benzocyclobutene, polyimide, polytetrafluoroethylene, or polyphenylene oxide.

  Further, the second signal line removes a frequency component other than the frequency component corresponding to the line length from the signal generated in the first signal line, and the frequency component corresponding to the line length is any frequency of 20 GHz or more. It may be.

  Thereby, it is possible to completely block the input of a signal having a frequency of 1 GHz or less generated by electrostatic discharge to the semiconductor integrated circuit.

  According to the electrostatic discharge protection circuit of the present invention, the electrostatic discharge protection circuit prevents the destruction of the semiconductor internal circuit due to ESD and does not deteriorate the high frequency characteristics of the semiconductor internal circuit in a high frequency region such as a millimeter wave or quasi-millimeter wave band. I will provide a.

It is sectional drawing which shows the structure of an ESD protection circuit. It is a figure which shows an example of a structure of an ESD protection circuit. It is a figure which shows typically the circuit structure of an ESD protection circuit. It is a figure which shows the characteristic evaluation result of an ESD protection circuit and input-output 50 ohm matching 1 step | paragraph amplifier. It is a figure which shows typically another example of the circuit structure of an ESD protection circuit. It is sectional drawing which shows the structure of the ESD protection circuit of a modification. It is sectional drawing which shows the structure of another example of the ESD protection circuit of a modification. It is a circuit diagram which shows the structure of the conventional ESD protection circuit and a capacitor. It is a figure which shows generation | occurrence | production of the loss by the capacitive component of the conventional ESD protection circuit.

  An electrostatic discharge protection circuit of the present invention is an electrostatic discharge protection circuit that is connected to a semiconductor integrated circuit and protects the semiconductor integrated circuit from electrostatic discharge. The electrostatic discharge protection circuit includes a semiconductor substrate and a first substrate formed above the semiconductor substrate. A dielectric layer; and a wiring layer formed on a surface of the first dielectric layer. The second wiring layer has one end connected to the pad and the other end connected to the semiconductor circuit. A first signal line, and a second signal line having one end connected to the first signal line and the other end grounded. The electrostatic discharge protection circuit further includes a first ground electrode layer formed on the back surface of the first dielectric layer, and the first ground electrode layer is a semiconductor substrate of the first dielectric layer. Formed on the side.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a cross-sectional view showing a configuration of an ESD protection circuit according to the embodiment. In FIG. 1, the ESD protection circuit 100 includes a conductive semiconductor substrate 10 such as silicon (Si), dielectric layers 13 a to 13 c (hereinafter, unless otherwise specified, a dielectric layer 13), and a first wiring layer 14. And a second wiring layer 15 and a third wiring layer 16. The conductive semiconductor substrate 10 includes a conductive semiconductor substrate portion 11 and a conductive semiconductor wiring portion 12.

  The conductive semiconductor substrate 10 includes, for example, a Si substrate, a circuit element formed on the Si substrate, and a wiring layer.

  The dielectric layer 13 is made of a resin, and specifically, is a material having a low relative dielectric constant and dielectric loss (for example, BCB (benzocyclobutene)). However, the dielectric layer 13 may be any material having a low relative dielectric constant and dielectric loss, and polyimide, tetrafluoroethylene, polyphenylene oxide, or the like may be used instead of BCB. Of the dielectric layer 13, the dielectric layer 13 b and the dielectric layer 13 c correspond to dielectrics that form a stripline structure together with the first wiring layer 14, the second wiring layer 15, and the third wiring layer 16. .

  The first wiring layer 14 is a first ground electrode layer formed on the dielectric layer 13a and corresponds to a ground layer constituting a stripline structure. For example, Al, Cu, Au, or the like A film formed of an alloy or the like. Since the first wiring layer 14 is grounded, an electric field generated in the second wiring layer 15 enters the conductive semiconductor substrate 10 and a loss occurs in a signal transmitted through the second wiring layer 15. Can be prevented.

  The second wiring layer 15 is a signal line that is formed on the dielectric layer 13b and transmits a signal, and is, for example, Al or Cu. The second wiring layer 15 corresponds to a signal line constituting a strip line structure. Further, since the second wiring layer 15 is formed by a post process after forming the conductive semiconductor substrate 10 by the main process, the signal line formed by the second wiring layer 15 is a low-loss wiring. Become. Specifically, the thickness of the second wiring layer 15 in the stacking direction can be increased by, for example, 3 to 10 μm or 4 to 6 μm by being formed by a post process. As a result, the signal line has a low resistance. It becomes. The second wiring layer 15 is formed apart from the first wiring layer 14 by 10 μm or more. In addition, it is preferable to form 15 micrometer or more apart.

  The third wiring layer 16 is a second ground electrode layer formed on the dielectric layer 13c, and corresponds to a ground layer that forms a stripline structure like the first wiring layer 14, for example, It is a film formed of Al, Cu, Au, or an alloy containing them. Since the third wiring layer 16 is a ground layer, when the ESD protection circuit 100 is flip-chip mounted, it can be prevented from being affected by a mounting substrate, an underfill resin, or the like. The third wiring layer 16 is formed apart from the second wiring layer 15 by 10 μm or more. In addition, it is preferable to form 15 micrometer or more apart.

  Note that the third wiring layer 16 may not be a ground layer. In this case, the second wiring layer 15 has a microstrip line structure together with the first wiring layer 14 and the dielectric layer 13b. In this case, the third wiring layer 16 may be removed.

  FIG. 2 is a diagram illustrating an example of the configuration of the ESD protection circuit 100. As shown in the figure, the second wiring layer 15 includes a first signal line 17 and three second signal lines 18.

  The first signal line 17 has one end connected to the pad and the other end connected to the semiconductor internal circuit, and transmits a high-frequency signal between the semiconductor internal circuit and the pad.

  Each of the second signal lines 18 has one end connected to the first signal line 17 and the other end connected to the first wiring layer 14 and the third wiring layer 16 via a contact 19. The second signal line 18 removes the frequency other than the frequency corresponding to the line length (the length in the x direction in the figure) from the first signal line 17.

  FIG. 3 is a diagram schematically showing a circuit configuration of the ESD protection circuit 100. In FIG. 3, the same components as those in FIG.

  The ESD protection circuit 100 includes a first strip line 21 and a second strip line 22. Note that the characteristics (for example, capacitance value, inductance, transmission loss, etc.) of the combination of all the first strip lines 21 shown in the figure are the signal lines of the first signal line 17 shown in FIG. This corresponds to the characteristics of the stripline structure. The characteristics of each of the second strip lines 22 correspond to the characteristics of the strip line structure in which the second signal line 18 shown in FIG. 2 is a signal line.

  In the figure, it is assumed that there is no parasitic capacitance and parasitic inductance generated in the contact 19 and that the contact 19 is not long.

  The second strip line 22 is used as a short stub. Specifically, since the first stripline 21 is connected to the ground via the second stripline 22, all the low-frequency signals among the signals transmitted through the first stripline 21 are emitted to the outside. Is done.

  For the high frequency signal of the second strip line 22, for example, 60 GHz, the second strip line 22 side is opened at the connection point between the first strip line 21 and the second strip line 22. Adjust it so that it is visible. In other words, the length of the second signal line 18 is adjusted. As a result, a high-frequency signal of 60 GHz among signals transmitted through the first strip line 21 is input to the semiconductor internal circuit 102 without loss at the connection point between the first strip line 21 and the second strip line 22. The

  As described above, the second stripline 22 is configured to cause signals other than the frequency band corresponding to the line length and the frequencies in the vicinity of the frequency band among the signals generated on the first stripline 21 in the traveling direction of the signal. On the other hand, it is removed from the first strip line 21 after the connection point of the second strip line 22. In other words, the second strip line 22 passes only the frequency band corresponding to the line length of the second signal line 18 and the frequency other than the vicinity of the frequency band to the first strip line 21 after the connection point.

  Next, characteristics when the ESD protection circuit 100 having the above-described configuration is inserted into a 60 GHz band input / output 50Ω matching single-stage amplifier will be described.

  FIG. 4 is a diagram showing the characteristic evaluation results of the ESD protection circuit 100 and the input / output 50Ω matching single-stage amplifier.

  FIG. 4A is a table showing characteristics when the ESD protection circuit 103 having the conventional ESD protection diodes 104 and 105 is used. The ESD protection diodes 104 and 105 are formed in the main process for forming the conductive semiconductor substrate 10. FIG. 4B is a table showing characteristics when the ESD protection circuit 100 of the present invention is used.

  Specifically, in FIGS. 4A and 4B, the ESD protection circuit 103 or 100 is inserted into, for example, a 60 GHz band input / output 50Ω matching single-stage amplifier, and the 50Ω including the ESD protection circuit 103 or 100 is used. It is a table | surface which shows the gain in 60 GHz of a matching 1 step | paragraph amplifier. Here, the gain in the 60 GHz band of the 50Ω matched single-stage amplifier in which the input / output matching circuit shown in FIG. 4B is configured by post-process wiring is 5.6 dB. The gain of the 50Ω matched single-stage amplifier is improved from the gain (4.4 dB) in the 60 GHz band of the 50Ω matched single-stage amplifier formed by the main process of the input / output matching circuit of FIG. 9 shown in the conventional example. This is because the wiring (including the input / output matching circuit) in the 50Ω matching single-stage amplifier is also formed by the post process, and the loss generated in the 50Ω matching single-stage amplifier is reduced.

  From FIG. 4A, at 60 GHz, the loss when the conventional ESD protection circuit 103 is used is 0.7 dB. On the other hand, from FIG. 4B, the gain at 60 GHz when the ESD protection circuit 100 is inserted is 5.5 dB, and the loss in the ESD protection circuit 100 is about 0.1 dB. Thus, the ESD protection circuit 100 can remarkably suppress the deterioration of the high frequency characteristics.

  FIG. 4C is a graph showing the frequency characteristics of the ESD protection circuit 100 of the present invention, and shows the gain of the one-stage amplifier including the ESD protection circuit 100 with respect to the frequency. From the figure, it can be confirmed that the gain in the low frequency region of 1 GHz or less is suppressed. That is, a signal generated by ESD is sufficiently removed in the ESD protection circuit 100.

  Thus, in the ESD protection circuit 100 of the present invention, the length of the second signal line 18 is set to a length corresponding to the frequency band of the input / output signal of the semiconductor internal circuit 102 and the frequency in the vicinity of the frequency band. Thus, frequencies other than the frequency band of the input / output signal of the semiconductor internal circuit 102 and the frequencies near the frequency band can be removed. This prevents a low frequency signal generated by ESD from being input to the semiconductor internal circuit 102 and destroying the ESD.

  In addition, since there is the first wiring layer 14 that is a ground layer between the conductive semiconductor substrate 10 and the second wiring layer 15, a high-frequency signal transmitted through the first signal line 17 is transmitted to the conductive semiconductor substrate 10. Leakage can be prevented and loss of high frequency signals can be reduced.

  In addition, although the short stub with which the ESD protection circuit 100 of this embodiment is provided, that is, the second strip line 22 has a three-stage configuration, the second strip line 22 may be connected in any number of stages. Even in the ESD protection circuit 100 ′ in which the second strip line 22 has a single stage configuration as shown in FIG. 5, almost no loss occurs in the ESD protection circuit 100 ′. However, when the number of stages is continued, ESD can be more reliably removed outside.

(Modification)
In the ESD protection circuit according to this modification, in the dielectric layer 13b and the dielectric layer 13c, the portion that is in contact with the first signal line 17 or the second signal line 18 has the first material particles as the first layer. A nanocomposite membrane dispersed in two materials.

  FIG. 6 is a cross-sectional view showing the configuration of the ESD protection circuit of the present modification. In FIG. 6, the same components as those of FIG.

  As shown in the figure, in the ESD protection circuit 200 </ b> A of this modification, a nanocomposite film 31 is formed around the second wiring layer 15. Specifically, the nanocomposite film 31 is formed between the second wiring layer 15 and the first wiring layer 14 and between the second wiring layer 15 and the third wiring layer 16. It is preferable to surround the second wiring layer 15. The nanocomposite film 31 here is a film made of a material in which fine particles made of a first material having a large relative dielectric constant are dispersed in a second material having a small relative dielectric constant and dielectric loss.

  In this modification, an example in which strontium titanate (STO) is used as the first material and BCB is used as the second material will be described. The relative dielectric constant of the nanocomposite film 31 can be controlled by the relative dielectric constant and the amount of fine particles dispersed in the BCB film. For this reason, a dielectric constant can be freely set in the range of several tens to several thousand.

  Furthermore, since the base of the nanocomposite film 31 is a BCB film, it can be easily formed by a spin coating method as with the BCB film. For this reason, it can be used without changing the conventional manufacturing process. Further, since the nanocomposite film 31 is formed by dispersing STO in the BCB film, it can also be formed by selecting a specific region. The thickness of the nanocomposite film 31 is, for example, 5 μm or more or 10 μm or more, and the width is, for example, 5 μm to 60 μm or 20 μm to 40 μm. Note that the width of the nanocomposite film 31 may be longer as long as other wirings are not affected.

  In FIG. 1, since the dielectric layers 13b and 13c around the second wiring layer 15 used as the high-frequency signal line use BCB having a low relative dielectric constant, the first signal line 17 and the second signal are used. The line length of the line 18 is increased, and the size of the ESD protection circuit 100 is increased. As shown in FIG. 6, the nanocomposite film 31 having a high relative dielectric constant selectively around the first signal line 17 and the second signal line 18 formed of the second wiring layer 15 constituting the ESD protection circuit 200A. Thus, the size of the ESD protection circuit 200A can be reduced.

  In this modification, STO is used as the first material used for the nanocomposite film 31, but any material may be used as long as it has a large relative dielectric constant and can be processed into fine particles. For example, barium strontium titanate (BST) or barium titanate (BTO) can be used, and ceramics having a relative dielectric constant of about several tens to several hundreds can be used. A plurality of materials having different relative dielectric constants may be used.

  Moreover, the particle size of the first material only needs to be kneaded and dispersed in the second material, and the smaller the particle size, the better. Specifically, it is preferably 1 μm or less, and particularly good characteristics can be obtained if it is in the range of about 1 nm to 200 nm.

  The concentration of the first material may be selected depending on the required dielectric constant, but can be increased to about 90% in the case of a combination of STO and BCB, for example.

  In the present modification, the nanocomposite film 31 surrounds the first signal line 17 and the second signal line 18, but the first signal line 17 and the second signal line 18 It may be formed between the first wiring layer 14 and between the first signal line 17 and the second signal line 18 and the third wiring layer 16. That is, the nanocomposite film 31 is the surface of the second wiring layer 15 that faces the first wiring layer 14 or the third wiring layer 16 in the portion where the dielectric layer 13 and the second wiring layer 15 are in contact with each other. It may be formed only around the periphery.

  Further, as shown in FIG. 7, the nanocomposite film 31 may be in contact with the first wiring layer 14 and the third wiring layer 16.

  The present invention is effective when the semiconductor internal circuit 102 is operated at a high frequency of, for example, 20 GHz or more, but the effect is particularly remarkable at a high frequency of 50 GHz or more.

  According to the ESD protection circuit of the present invention, the semiconductor internal circuit is protected from ESD without deteriorating the high frequency characteristics by using a low-loss transmission line without using an element that adds parasitic capacitance. It can be used for semiconductor devices such as various communication devices and radar devices.

DESCRIPTION OF SYMBOLS 10 Conductive semiconductor substrate 11 Conductive semiconductor substrate part 12 Conductive semiconductor wiring part 13, 13a, 13b, 13c Dielectric layer 14 1st wiring layer 15 2nd wiring layer 16 3rd wiring layer 17 1st signal Line 18 Second signal line 19 Contact 21 First strip line 22 Second strip line 31 Nanocomposite film 100, 100 ′, 103, 200A, 200B ESD protection circuit 101 High frequency signal input / output pad 102 Semiconductor internal circuit 104, 105 ESD protection diode 106, 111, 112 Capacitor

Claims (11)

An electrostatic discharge protection circuit connected to a semiconductor integrated circuit and protecting the semiconductor integrated circuit from electrostatic discharge,
A semiconductor substrate;
A first dielectric layer formed above the semiconductor substrate;
A wiring layer formed on the surface of the first dielectric layer,
The wiring layer is
A first signal line having one end connected to the pad and the other end connected to the semiconductor integrated circuit;
An electrostatic discharge protection circuit including a second signal line having one end connected to the first signal line and the other end grounded. The electrostatic discharge protection circuit according to claim 1, further comprising a first ground electrode layer formed on a back surface of the dielectric layer. The electrostatic discharge protection circuit according to claim 1, wherein the first ground electrode layer is formed on the semiconductor substrate side of the first dielectric layer. The electrostatic discharge protection circuit further includes a contact for electrically connecting the first ground electrode layer and the wiring layer via the first dielectric layer,
The electrostatic discharge protection circuit according to claim 2, wherein the other end of the second signal line is electrically connected to the first ground electrode layer through the contact. A second dielectric layer formed on the wiring layer;
The electrostatic discharge protection circuit according to claim 2, further comprising a second ground electrode layer formed on the second dielectric layer. Of the first dielectric layer and the second dielectric layer, the portion in contact with the first signal line or the second signal line has particles made of the first material as the second material. The electrostatic discharge protection circuit according to claim 5, comprising a nanocomposite film dispersed therein. The electrostatic discharge protection circuit according to claim 6, wherein a particle diameter of the first material is 1 nm or more and 200 nm or less. The electrostatic discharge protection circuit according to claim 7, wherein the first material is ceramics. The electrostatic discharge protection circuit according to claim 8, wherein the ceramic is strontium titanate or barium strontium titanate. The electrostatic discharge protection circuit according to claim 6, wherein the second material is benzocyclobutene, polyimide, polytetrafluoroethylene, or polyphenylene oxide. The second signal line is removed from a signal generated in the first signal line except for a frequency band according to a line length and a frequency near the frequency band,
The electrostatic discharge protection circuit according to claim 1, wherein a frequency band corresponding to the line length and a frequency near the frequency band are any frequencies of 20 GHz or more.

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