JP2010251639A - Semiconductor device, and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device that suppresses the occurrence of a leak due to local electric field concentration such as GIDL and short-channel effect, and to provide a method of manufacturing the semiconductor device. <P>SOLUTION: The semiconductor device 100 has a gate electrode 12 formed on a semiconductor substrate 2 via a gate insulating film 11, a source/drain region 15 formed on both sides of the gate electrode 12 in the semiconductor substrate 2, having an extension region 151 on the side of the gate electrode 12 and a deep region 152 on the opposite side to the gate electrode 12, and containing a conductivity impurity, wherein the extension region 151 of the source/drain region 15 includes a high-diffusion region 151a on the side of the gate electrode 12 and a low-diffusion region 151b where the depth of the lowermost semiconductor substrate 2 from the surface is smaller than the depth of the lowermost semiconductor substrate 2 from the surface in the high-diffusion region 151a, and which is provided between the high-diffusion region 151a and the deep region 152. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

  Conventionally, it is known that B (boron) and Si at interstitial positions diffuse in pairs in a Si crystal (for example, see Non-Patent Document 1).

  Therefore, when a source / drain region of a P-type transistor is formed using B, B is diffused greatly by paired with Si at the interstitial position, and the concentration profile of B in the source / drain region tends to be gentle. There is. In particular, when the B concentration profile in the extension region of the source / drain region becomes gentle, there is a problem that the short channel effect is likely to occur.

  On the other hand, it is known that C (carbon) has a property that Si at an interstitial position easily forms a pair (for example, see Non-Patent Document 2).

S. C. Jain et al., “Transient enhanced diffusion of boron in Si”, J. Appl. Phys. 91, 8919 (2002); DOI: 10.1063 / 1.1471941 Issue Date: 1 June 2002. Christoph Zechner, Dmitri Matveev, Nikolas Zographos, Victor Moroz, Bartek Pawlak, “Modeling Ultra Shallow Junctions Formed by hosphorus-Carbon and Boron-Carbon Co-implantation”, Mater. Res. Soc. Symp. Proc. Vol. 994-2007 Materials Research Society. 0994-F12-17.

  An object of the present invention is to provide a semiconductor device that suppresses the occurrence of leakage and short channel effects caused by local electric field concentration, and a method for manufacturing the same.

  According to one embodiment of the present invention, a gate electrode formed over a semiconductor substrate with a gate insulating film interposed therebetween, formed on both sides of the gate electrode in the semiconductor substrate, and an extension region on the gate electrode side and the gate electrode Each having a deep region on the opposite side, and a source region and a drain region each containing a conductive impurity, and the extension region of the drain region includes a first region on the gate electrode side and a lowermost region The depth from the surface of the semiconductor substrate is shallower than the depth from the surface of the semiconductor substrate at the bottom of the first region, and is provided between the first region and the deep region of the drain region. A semiconductor device including a second region is provided.

  In another aspect of the present invention, a step of forming a gate electrode on a semiconductor substrate via a gate insulating film, a step of forming a shallow region of the source region and the drain region, and the step of forming the source region and the drain region Before or after forming the shallow region, a step of forming a diffusion suppression region so as to overlap a region other than the end on the gate electrode side in the shallow region of the drain region, and the shallowness of the drain region by heat treatment A step of diffusing conductive impurities in a region not overlapping with the diffusion suppressing region while suppressing diffusion of conductive impurities in the region overlapping with the diffusion suppressing region in the region. Provide a method.

  ADVANTAGE OF THE INVENTION According to this invention, the semiconductor device which suppressed generation | occurrence | production of the leak which generate | occur | produces by local electric field concentration, and the short channel effect, and its manufacturing method can be provided.

1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention. FIG. 3 is an enlarged view of a source / drain region according to the first embodiment of the present invention. The enlarged view of the source-drain area | region which concerns on a comparative example. The graph which showed the concentration profile of the conductivity type impurity in the extension area | region under various conditions. 6 is a graph showing current-voltage characteristics of the semiconductor device according to the first embodiment and the comparative example of the present invention. (A)-(d) is sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. (E)-(g) is sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. Sectional drawing of the semiconductor device which concerns on the 2nd Embodiment of this invention. (A), (b) is sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the 2nd Embodiment of this invention.

[First Embodiment]
(Configuration of semiconductor device)
FIG. 1 is a cross-sectional view of a semiconductor device 100 according to the first embodiment of the present invention. The semiconductor device 100 includes a semiconductor substrate 2, an element isolation region 3 formed in the semiconductor substrate 2 and partitioning an element region, a gate electrode 12 formed on the semiconductor substrate 2 via a gate insulating film 11, a gate Offset spacers 13 formed on both side surfaces of the electrode 12, gate sidewalls 14 formed on the side surfaces of the offset spacer 13, source / drain regions 15 formed on both sides of the gate electrode 12 in the semiconductor substrate 2, and source And a diffusion suppression region 16 formed so as to overlap the upper portion of the drain region 15.

  FIG. 2 is an enlarged view of the source / drain region 15. 2 shows only one of the source / drain regions 15 formed on both sides of the gate electrode 12, the other source / drain region 15 has a similar structure.

  The source / drain region 15 includes a conductive impurity such as B and has an extension region 151 located on the gate electrode 12 side and a deep region 152 located on the opposite side of the gate electrode 12.

  The extension region 151 includes a high diffusion region 151a on the gate electrode 12 side and a low diffusion region 151b on the deep region 152 side. The high diffusion region 151a is a region that hardly overlaps with the diffusion suppression region 16, and the internal conductive impurities are relatively diffused by the heat treatment. On the other hand, the low diffusion region 151 b is a region that greatly overlaps the diffusion suppression region 16, and the diffusion of the conductive type impurities inside is suppressed by the diffusion suppression region 16.

Therefore, the boundary between the semiconductor substrate 2 of the high diffusion region 151a (e.g., 5 × ¹⁰ 18 lines atoms · ^{cm -3} in concentration contours conductivity type impurity) concentration profile near a conductivity type impurity, the low diffusion region 151b It is gentle compared to the ones. Further, the depth Da from the surface of the semiconductor substrate 2 at the bottom of the boundary with the semiconductor substrate 2 in the high diffusion region 151a is from the surface of the semiconductor substrate 2 at the bottom of the boundary with the semiconductor substrate 2 in the low diffusion region 151b. It is deeper than the depth Db.

  FIG. 3 shows an enlarged view of the source / drain region 25 in which all of the extension regions are low diffusion regions as a comparative example.

  The source / drain region 25 includes a conductive impurity such as B, and has an extension region 251 located on the gate electrode side and a deep region 252 located on the opposite side of the gate electrode.

  The extension region 251 has a steep conductivity type impurity concentration profile in which diffusion of the conductivity type impurity is suppressed in all the regions. Here, it is assumed that the depth from the surface of the semiconductor substrate 2 at the bottom of the boundary between the extension region 251 and the semiconductor substrate is the same Db as that of the low diffusion region 151b.

  In general, when the concentration profile of the conductive impurity at the end of the extension region on the channel region side is too steep as in the extension region 251, leakage due to local concentration of the electric field at the end tends to occur. As an example, when a substrate bias voltage is applied, the electric field is locally concentrated at the end of the extension region on the channel region side, and leakage from the drain region called GIDL (gate induced drain leakage) to the substrate occurs.

  On the other hand, if the concentration profile of the conductive impurity in the extension region is too gentle, there is a problem that the short channel effect is likely to occur.

  In the present embodiment, the end of the extension region 151 on the channel region side is used as a high diffusion region 151a having a relatively gentle conductivity type impurity concentration profile, and the depletion layer width at the PN junction in the vicinity thereof is increased. , GIDL or the like can suppress the occurrence of leakage due to local concentration of the electric field. In addition, the short channel effect can be suppressed by making the region other than the end of the extension region 151 on the channel region side a low diffusion region 151b having a steep conductivity type impurity concentration profile.

  In order to suppress the occurrence of GIDL, the end of the drain region extension region 151 on the channel region side only needs to be the high diffusion region 151a. For this reason, the diffusion suppression region 16 may be formed only on the drain side of the source / drain region 15, and only the extension region 151 on the drain side may be configured by the high diffusion region 151a and the low diffusion region 151b. In this case, in the extension region on the source side of the source / drain region 15, similarly to the extension region 251 of the source / drain region 25, the diffusion of the conductive impurity is suppressed in all the regions, and the concentration of the steep conductive impurity is reduced. It is preferable to have a profile.

  The diffusion suppressing region 16 is formed by injecting an impurity having a property of suppressing the diffusion of the conductive impurity in the source / drain region 15 into a part of the source / drain region 15. For example, when the conductivity type impurity in the source / drain region 15 is B or P, the diffusion suppression region 16 is formed by implanting C. When the conductive impurity in the source / drain region 15 is As, the diffusion suppression region 16 is formed by implanting Xe.

  The mechanism in which the impurity in the diffusion suppression region 16 suppresses the diffusion of the conductive impurity in the source / drain region 15 is, for example, as follows. As an example, a case where the conductivity type impurity in the source / drain region 15 is B and the impurity in the diffusion suppression region 16 is C will be described.

  When B is implanted into the semiconductor substrate 2 to form the source / drain regions 15, a part of Si moves from the lattice position to the interstitial position. Si in the interstitial position has a property of being paired with B and diffusing. On the other hand, C in the diffusion suppression region 16 also has a property of forming a pair with Si in the interstitial position. For this reason, when C is paired with Si at the interstitial position, it can be suppressed that B and Si at the interstitial position are paired and diffused.

  FIG. 4 is a graph showing the concentration profile of conductive impurities in the extension regions of the source / drain regions under various conditions. Here, B was used as the conductive impurity, and C was used as the impurity that suppresses diffusion of the conductive impurity.

  P1 in the figure is a concentration profile of B after annealing in a region where C is implanted with an implantation energy of 3 keV. P2 is a concentration profile of B after annealing in a region where C is not implanted. P3 is a concentration profile of B before annealing. That is, P1 corresponds to the profile of the low diffusion region 151b, and P2 corresponds to the profile of the high diffusion region 151a.

Further, T1 and T2 in the figure are tangents in the impurity concentration at the boundary between P1 and P2 with the semiconductor substrate 2, respectively. In general, the impurity concentration at the boundary between the source / drain region and the semiconductor substrate 2 is defined as 5 × 10 ¹⁸ atoms · cm ⁻³ as shown in FIG. The impurity concentration set as the boundary is not limited to this. For example, it can be set in a range of ^{1 × 10 18 atoms · cm -3} ~5 × 10 18 atoms · cm -3.

  By comparing P3 and P1 or P2, it can be seen that B diffuses by annealing and B moves to a deep position. Further, by comparing P1 and P2, it can be seen that B in a region where C is not implanted is more diffused.

Further, since the inclination of the tangent T2 is smaller than the inclination of the tangent T1, the B concentration profile in the vicinity of the boundary with the semiconductor substrate in the region where C is not implanted is gentler than that in the region where C is implanted. I understand that. Note that the impurity concentration at the boundary between the source / drain region and the semiconductor substrate 2 is set to any concentration within the range of 1 × 10 ¹⁸ atoms · cm ^{−3 to} 5 × 10 ¹⁸ atoms · cm ^−3. 4 that the slope of the tangent line T2 is smaller than the slope of the tangent line T1.

  From these results, the concentration profile of the conductive impurities in the vicinity of the boundary between the high diffusion region 151a and the semiconductor substrate 2 is gentler than that of the low diffusion region 151b, and the depth Da is deeper than the depth Db. I understand that

FIG. 5 is a graph showing current-voltage characteristics in the semiconductor device 100 according to the present embodiment and the semiconductor device having the source / drain regions 25 according to the comparative example. Id and Is in the figure are profiles representing the characteristics of the source current and the drain current with respect to the gate voltage in the present embodiment, respectively. Also, Id ₀ and Is ₀ in the figure are profiles representing the characteristics of the source current and the drain current with respect to the gate voltage in the comparative example, respectively.

As shown in FIG. 5, the gate voltage is in the negative region, the magnitude of Id is suppressed to about half the size of Id _0. This indicates that in the semiconductor device 100 according to the present embodiment, the generation of GIDL that is an off-leakage current generated from the drain region is suppressed.

  5 that the occurrence of the short channel effect is suppressed in both the semiconductor device 100 according to the present embodiment and the semiconductor device having the source / drain regions 25 according to the comparative example.

  The semiconductor substrate 2 is made of a Si-based crystal such as a Si crystal.

The element isolation region 3 is made of an insulating material such as SiO ₂ and has an STI (Shallow Trench Isolation) structure.

The gate insulating film 11 is made of, for example, an insulating material such as SiO ₂ , SiN, or SiON, or a high dielectric constant material such as HfSiON.

  The gate electrode 12 is made of, for example, Si-based polycrystal such as polycrystal Si containing conductive impurities, metal, or a stacked body thereof.

The offset spacer 13 and the gate sidewall 14 are made of an insulating material such as SiO ₂ or SiN.

  Below, an example of the manufacturing method of the semiconductor device 100 which concerns on this Embodiment is shown.

(Manufacture of semiconductor devices)
6A (a) to 6 (d) and FIGS. 6B (e) to (g) are cross-sectional views illustrating the manufacturing steps of the semiconductor device 100 according to the first embodiment of the present invention.

  First, as shown in FIG. 6A, the element isolation region 3 is formed in the semiconductor substrate 2 by the STI method or the like, and then the gate electrode 12 is formed on the semiconductor substrate 2 via the gate insulating film 11.

  Although not shown, after the element isolation region 3 is formed, a conductivity type impurity is implanted into the semiconductor substrate 2 by ion implantation or the like to form a well and a channel region.

The gate insulating film 11 and the gate electrode 12 are formed by the following method, for example. First, after forming a well and a channel region, an SiO ₂ film is formed on the semiconductor substrate 2 by a thermal oxidation method, and a polycrystalline Si film is formed thereon by a CVD (Chemical Vapor Deposition) method. Next, using a resist having a gate pattern formed by lithography as a mask, etching by RIE (Reactive Ion Etching) is performed on the polycrystalline Si film and the SiO ₂ film, and the gate electrode 12 and the gate insulating film 11 are formed. Process each one.

  Next, as shown in FIG. 6A (b), offset spacers 13 are formed on both side surfaces of the gate electrode 12.

The gate insulating film 11 and the gate electrode 12 are formed by the following method, for example. First, a SiO ₂ film having a thickness of ₂ nm is formed on the entire surface of the semiconductor substrate 2 so as to cover the surface of the gate electrode 12 by CVD. Next, anisotropic etching by the RIE method is performed on the SiO ₂ film to process the offset spacers 13.

  Next, as shown in FIG. 6A (c), a shallow region 153 of the source / drain region 15 is formed.

  Specifically, for example, using the offset spacer 13 and the gate electrode 12 as a mask, a conductive impurity is implanted into the entire surface of the semiconductor substrate 2 by ion implantation to form a shallow region 153 of the source / drain region 15. .

When the shallow region 153 of the P-type source / drain region 15 is formed using B, for example, ion implantation is performed under conditions of an implantation energy of 0.5 keV and an implantation amount of 1.0 × 10 ¹⁵ cm ⁻² .

  Next, as shown in FIG. 6A (d), a gate sidewall 17 is formed on the side surface of the offset spacer 13.

The gate side wall 17 is formed by the following method, for example. First, by CVD so as to cover the upper surface side and the gate electrode 12 of the offset spacers 13, laminating the SiN film of the SiO ₂ film and the 10nm thick 3nm over the entire surface of the semiconductor substrate 2. Next, anisotropic etching by the RIE method is performed on the SiN film and the SiO ₂ film, and the gate side wall 17 is processed.

  Next, as shown in FIG. 6B (e), a deep region 152 of the source / drain region 15 is formed. Here, a region that does not overlap with the deep region 152 of the shallow region 153 of the source / drain region 15 is an extension region 151.

  Specifically, for example, using the gate sidewall 17 and the gate electrode 12 as a mask, a conductive impurity is implanted into the entire surface of the semiconductor substrate 2 by ion implantation to form a deep region 152.

Here, when the P-type deep region 152 is formed using BF ₂ , for example, ion implantation is performed under conditions of an implantation energy of ¹⁵ keV and an implantation amount of 3.0 × 10 ¹⁵ cm ⁻² .

  Next, as shown in FIG. 6B (f), after the gate side wall 17 is removed, the gate side wall 14 having a width smaller than that of the gate side wall 17 is formed.

The gate side wall 14 is formed by the following method, for example. First, a SiO ₂ film having a thickness of 5 nm is formed on the entire surface of the semiconductor substrate 2 so as to cover the side surfaces of the offset spacer 13 and the upper surface of the gate electrode 12 by CVD. Next, anisotropic etching by the RIE method is performed on the SiO ₂ film to process the gate side wall 14.

  Next, as shown in FIG. 6B (g), the diffusion suppression region 16 is formed.

Specifically, for example, impurities such as C are implanted into the entire surface of the semiconductor substrate 2 by ion implantation using the gate sidewall 14 and the gate electrode 12 as a mask, thereby forming the diffusion suppression region 16. Here, for example, C is implanted under conditions of an implantation energy of 10 keV and an implantation amount of 1.0 × 10 ¹⁵ cm ⁻² .

  Since the width of the gate side wall 14 used as a mask is smaller than the width of the gate side wall 17, the diffusion suppression region 16 is formed so as to overlap with a partial region on the deep region 152 side in the extension region 151.

  Next, heat treatment is performed on the semiconductor substrate 2 in order to activate the conductive impurities in the source / drain regions 15. Thereby, the conductive impurities in the extension region 151 are diffused to form the high diffusion region 151a and the low diffusion region 151b, and the semiconductor device 100 shown in FIGS. As the heat treatment, for example, spike annealing at a temperature of 1050 ° C. is performed.

  In the region of the extension region 151 that does not overlap the diffusion suppression region 16, the conductive impurity is diffused by the heat treatment. High diffusion region 151a is formed mainly by conductive impurities that are largely diffused.

  On the other hand, in the region overlapping the diffusion suppression region 16 of the extension region 151, the diffusion of the conductive impurity due to the heat treatment is suppressed by the diffusion suppression region 16. The low diffusion region 151b is mainly composed of conductive impurities whose diffusion is suppressed.

  The order in which the shallow region 153, the deep region 152, and the diffusion suppression layer 16 of the source / drain region 15 are formed is not limited to that shown above.

(Effects of the first embodiment)
According to the first embodiment of the present invention, the high diffusion region 151 a and the low diffusion region 151 b are formed in the extension region 151 of the source / drain region 15, thereby generating local electric field concentration such as GIDL. The occurrence of leaks and short channel effects can be suppressed.

[Second Embodiment]
(Configuration of semiconductor device)
FIG. 7 is a cross-sectional view of a semiconductor device 200 according to the second embodiment of the present invention. The semiconductor device 200 includes a semiconductor substrate 2, an element isolation region 3 that is formed in the semiconductor substrate 2 and partitions an element region, a gate electrode 12 that is formed on the semiconductor substrate 2 via a gate insulating film 11, a gate Offset spacers 13 formed on both sides of the electrode 12, gate sidewalls 14 formed on the sides of the offset spacer 13, source / drain regions 15 formed on both sides of the gate electrode in the semiconductor substrate 2, And a diffusion suppression region 20 formed so as to overlap the upper portion of the drain region 15.

  The source / drain region 15 includes a conductive impurity such as B and has an extension region 151 located on the gate electrode 12 side and a deep region 152 located on the opposite side of the gate electrode 12.

  The diffusion suppression region 20 is formed so as not to overlap the deep region 152 of the source / drain region 15. For this reason, it is possible to avoid an adverse effect caused by implanting the impurities constituting the diffusion suppression region 20 into the deep region 152. For example, generation of a crystal defect in the deep region 152 can be suppressed and generation of leakage can be suppressed. Other features are the same as those of the diffusion suppression region 16 of the first embodiment.

  Below, an example of the manufacturing method of the semiconductor device 200 concerning this Embodiment is shown.

(Manufacture of semiconductor devices)
8A and 8B are cross-sectional views illustrating the manufacturing process of the semiconductor device 200 according to the second embodiment of the present invention.

  First, the steps until the formation of the deep region 152 of the source / drain region 15 shown in FIGS. 6A (a) to 6B (e) are performed in the same manner as in the first embodiment.

  Next, as shown in FIG. 8A, a resist 21 is formed on the semiconductor substrate 2 so as to cover the upper surface of the deep region 152.

  Next, as shown in FIG. 8B, a diffusion suppression region 20 is formed.

  Specifically, for example, using the gate sidewall 14, the gate electrode 12, and the resist 21 as a mask, impurities such as C are implanted into the entire surface of the semiconductor substrate 2 by ion implantation to form the diffusion suppression region 20. .

  Here, since the upper surface of the deep region 152 is covered with the resist 21, impurities such as C are hardly implanted into the deep region 152, and the diffusion suppression region 20 is formed so as not to overlap the deep region 152.

  Thereafter, heat treatment is performed on the semiconductor substrate 2 in order to activate the conductive impurities in the source / drain regions 15. As a result, the conductive impurities in the extension region 151 are diffused to form the high diffusion region 151a and the low diffusion region 151b, and the semiconductor device 200 shown in FIG. 7 is obtained.

(Effect of the second embodiment)
According to the second embodiment of the present invention, by forming the diffusion suppression region 20 so as not to overlap the deep region 152, while suppressing the occurrence of problems such as crystal defects in the deep region 152, By forming the high diffusion region 151a and the low diffusion region 151b in the extension region 151, the same effect as that of the first embodiment can be obtained.

[Other Embodiments]
The present invention is not limited to the above embodiments, and various modifications can be made without departing from the spirit of the invention.

  In addition, the constituent elements of the above embodiments can be arbitrarily combined without departing from the spirit of the invention.

  100, 200 semiconductor device, 2 semiconductor substrate, 11 gate insulating film, 12 gate electrode, 15 source / drain region, 151 extension region, 151a high diffusion region, 151b low diffusion region, 152 deep region, 153 shallow region, 16, 20 Diffusion suppression area

Claims (5)

A gate electrode formed on a semiconductor substrate via a gate insulating film;
A source region and a drain region respectively formed on both sides of the gate electrode in the semiconductor substrate, each having an extension region on the gate electrode side and a deep region on the opposite side of the gate electrode;
Have
The extension region of the drain region includes a first region on the gate electrode side and a depth from the surface of the lowermost semiconductor substrate that is lower than a depth from the surface of the lowermost semiconductor substrate of the first region. A second region that is shallow and is provided between the first region and the deep region of the drain region;
Semiconductor device. The concentration profile of the conductive impurity at the boundary of the first region is gentler than the concentration profile of the conductive impurity at the boundary of the second region.
The semiconductor device according to claim 1. The second region overlaps with a diffusion suppression region including an impurity that suppresses diffusion of the conductive impurity.
The semiconductor device according to claim 1. The combination of the conductivity type impurity and the impurity is B and C, P and C, or As and Xe.
The semiconductor device according to claim 3. Forming a gate electrode on a semiconductor substrate via a gate insulating film;
Forming a shallow region of the source region and the drain region;
Before or after forming the shallow regions of the source region and the drain region, forming a diffusion suppression region so as to overlap a region other than the end on the gate electrode side in the shallow region of the drain region;
The heat treatment diffuses the conductive impurities in the region not overlapping the diffusion suppression region while suppressing the diffusion of the conductive impurities in the region overlapping the diffusion suppression region in the shallow region of the drain region. Process,
A method of manufacturing a semiconductor device including:

Images