JP2010231701A - Apparatus for quickly starting system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a quick starting apparatus that reduces the time from power-on to completion of system starting, in a system including a cache memory between a CPU and a main storage. <P>SOLUTION: The quick starting apparatus includes a monitoring apparatus that monitors access from the cache memory to the main storage and acquires access time from power-on to an access operation and an address of the main storage to be accessed at the first system boot, and a table storage that stores the access time and address acquired by the monitoring apparatus as table data. The monitoring apparatus reads data from an address of the main storage corresponding to a relevant address of the table data according to the access time included in the table data stored in the table storage, and writes the read data into the cache memory at the second and subsequent system boot. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a startup speed-up device that shortens the processing time during system startup by devising control of the cache memory in a system including a cache memory between a CPU and a main storage device.

  A system including a CPU (computer), a cache memory (including a cache controller), and a main storage device (main memory) is used as an embedded system such as an electric product.

  The cache memory is a volatile memory disposed between the CPU and the main storage device in order to reduce a delay in access from the CPU to the main storage device. The instruction code and data once loaded (read) by the CPU (hereinafter collectively referred to as read data) are stored in the cache memory, and when the CPU reuses the same read data, Instead of reloading from the cache memory, the load time can be shortened and the processing speed of the CPU can be increased.

  Immediately after the system is started, no read data is stored in the volatile cache memory. As a result, immediately after the system is started, many accesses to the main storage device occur when the CPU executes an initialization program (also called an initialization routine or a startup program). Further, it has been found that the initialization program has few repeated instructions, which causes frequent access to the main storage device, and a waiting time is generated in the CPU each time.

In order to cope with such a problem, several methods have been conventionally proposed.
One method is a data prefetch control method, in which an instruction code or data subsequent to an instruction code executed by the CPU is prefetched to prepare for the next reading (Patent Document 1).

  However, in this method, the prefetched subsequent instruction code and data are not always used by a program branch instruction or the like. As a result, unnecessary cache data is loaded into the cache memory and other necessary cache data is deleted. As a result, there is a risk of reloading those instruction codes and data.

  As another method, data that is known to be loaded in advance when the power is turned on is loaded into the cache memory. When the CPU executes the initialization program, the data loaded into the cache memory is used for initialization. There is one that shortens the cache time of a program (Patent Document 2).

  However, since this method is also speeded up only within the range of the capacity of the cache memory, if the initialization program exceeds the size, it cannot be speeded up beyond that. In addition, when the time from when the power is turned on to when the CPU starts up is short, there is a problem that the initialization program cannot be sufficiently cached or the CPU must be started until the cache is completed.

JP-A-1-314327 JP-A-7-36784

  An object of the present invention is to provide a startup acceleration device capable of shortening the time from power-on to system startup completion in a system including a cache memory between a CPU and a main storage device.

In order to achieve the above object, the present invention provides a CPU, a main storage device storing read data used by the CPU, read data read from the main storage device to the CPU, and temporarily A system startup speed-up device comprising a cache memory stored in
A monitoring device that monitors the access from the cache memory to the main storage device at the first system startup, and obtains the access time from power-on to the access and the address of the access destination main storage device When,
A table storage device for storing the access time and address acquired by the monitoring device as table data;
The monitoring device corresponds to the address corresponding to the address included in the table data before reaching the access time according to the order of the access time included in the table data stored in the table storage device at the second or subsequent system startup. It is an object of the present invention to provide a startup acceleration device characterized in that read data is read from an address of a main storage device, and the read data is written to the cache memory.

  Here, the monitoring device detects that the main memory is accessed from the cache memory at the second or subsequent system startup, and table data including the access destination address is stored in the table storage. When stored in the apparatus, it is preferable to rewrite the access time included in the table data including the access destination address to the access time when the detected access was performed.

The present invention also provides a CPU, a main storage device in which read data used by the CPU is stored, a cache memory that supplies read data read from the main storage device to the CPU and temporarily stores the read data. A system startup acceleration device comprising:
When the system is started for the first time, the access from the cache memory to the main storage device is monitored, and is included in each index consisting of some bits of the address of the main storage device to be accessed at regular intervals. A monitoring device that obtains the number of accesses to a plurality of addresses,
A table storage device that stores, as table data, an access time from power-on to the predetermined time and an index with the maximum number of accesses acquired by the monitoring device;
The monitoring device has a plurality of addresses of the main storage device corresponding to the index included in the table data in accordance with the order of access times included in the table data stored in the table storage device at the second or subsequent system startup. There is provided a start-up acceleration device characterized in that read data is read from a plurality of read data and a part of the read data is written to the cache memory.

  In this case, when the system is started for the second time or later, the number of accesses to a plurality of addresses included in an index different from the index included in the table data exceeds a threshold value for each predetermined time. Preferably, the index included in the table data is rewritten to an index exceeding the threshold value.

  According to the present invention, when the initialization program is executed for the second time or later, the monitoring device refers to the access time included in the table data stored at the previous execution and sequentially corresponds to the address included in the table data. Data is read from the address of the main storage device and written to the cache memory. Therefore, basically, access from the CPU to the main storage device does not occur, the execution of the initialization program is accelerated, and the system startup time can be shortened.

  Further, according to the present invention, the table data can be stored at regular intervals instead of storing the table data every time access is made. Therefore, the required memory capacity of the table storage device can be appropriately reduced.

It is a block diagram of one Embodiment showing the structure of the embedded system carrying the starting acceleration apparatus concerning this invention. It is a conceptual diagram showing the structure of the cache memory shown in FIG. It is a conceptual diagram showing the structure of the cache set memorize | stored in cache memory. It is a conceptual diagram showing the structure of the table data memorize | stored in a table memory | storage device. It is a flowchart showing operation | movement of the embedded system shown in FIG. It is another conceptual diagram showing the structure of the table data memorize | stored in a table memory | storage device. It is a conceptual diagram showing the relationship between the index used by cache memory, and the index used by table data. 4 is another flowchart showing the operation of the embedded system shown in FIG. 1.

  DESCRIPTION OF EMBODIMENTS Hereinafter, a startup acceleration device of the present invention will be described in detail based on a preferred embodiment shown in the accompanying drawings.

  FIG. 1 is a block diagram of an embodiment showing a configuration of an embedded system equipped with a startup acceleration device according to the present invention. The embedded system 10 shown in FIG. 1 includes a CPU 12, a cache memory 14, a main storage device 16, a monitoring device 18, and a table storage device 20. Here, the monitoring device 18 and the table storage device 20 constitute a startup acceleration device according to the present invention.

  The CPU 12 and the cache memory 14 are connected to each other. Further, the cache memory 14, the main storage device 16, and the monitoring device 18 are connected to each other via an internal bus 22. Furthermore, the monitoring device 18 and the table storage device 20 are connected to each other.

  In the embedded system 10, the CPU 12 is a control unit that controls the operation of the entire system, and loads and executes various programs (software) including an initialization program.

  Here, the initialization program is a program for initializing the embedded system 10 by being executed first by the CPU when the embedded system 10 is turned on, and is stored in the main storage device 16 in advance. .

  Subsequently, the cache memory 14 is a volatile semiconductor memory that operates at a high speed although its capacity is smaller than that of the main storage device 16. The cache memory 14 reads out read data used by the CPU 12 from the main storage device 16 via the internal bus 22 and supplies it to the CPU 12 under the control of a built-in cache controller (not shown). ) As a temporary store. When the CPU 12 reuses the same read data, if the read data is stored in the cache memory 14, the read data stored in the cache memory 14 is supplied to the CPU 12 instead of from the main storage device 16. This speeds up the read operation.

  The main storage device 16 is a volatile semiconductor memory having a large capacity but a low speed as compared with the cache memory 14. In the main storage device 16, various read data used by the CPU 12 including an initialization program are stored in advance by being copied from a nonvolatile memory (not shown) such as a flash memory immediately after the power is turned on. .

  The monitoring device 18 monitors the access from the CPU 12 (actually, the cache memory 14) to the main storage device 16 at the first (first) system startup, and the access time from when the power is turned on until the access is performed ( In the present embodiment, the number of clocks from power-on) and the address of the main storage device 16 to be accessed are acquired and written as table data in the table storage device 20. In addition, the monitoring device 18 starts the second or subsequent system startup according to the order of the access times included in the table data stored in the table storage device 20 until the access time is reached or every predetermined time. Read data is read from the address of the main storage device 16 corresponding to the address included in the data, and is written in the cache memory 14 as a cache set. By performing such processing, necessary data is efficiently written into the cache memory 14 by a necessary time. The monitoring device 18 is provided with an initialization completion register 24. The initial value of the initialization completion register 24 immediately after the power is turned on is “0” which means that the initialization is not completed, and the monitoring device 18 is initialized by the initialization program (that is, the CPU 12). The above operation is continued until 24 is changed to “1” indicating completion of initialization.

  The table storage device 20 is a nonvolatile rewritable semiconductor memory, and stores the access time and address acquired by the monitoring device 18 as table data as described above. The table storage device 20 is provided with an initial execution flag register 26 that indicates whether or not the CPU 12 has executed the initialization program for the first time. The first execution flag register 26 means that the initialization program is executed for the first time by the update program (that is, the CPU 12) of the initialization program when the initialization program is changed, for example. It is set to “1”, and after completion of the first initialization program, it is rewritten to “0” which means that the execution of the initialization program is not the first execution (the second and subsequent executions).

  Next, the cache memory 14 will be described.

  FIG. 2 is a conceptual diagram showing the configuration of the cache memory 14 shown in FIG. As shown in FIG. 2, the cache memory 14 includes a plurality of lines, and is configured to store up to four cache sets in one line. The cache set is a minimum unit when read data is stored in the cache memory 14. A memory area in which each cache set is stored is called a way. In the cache memory 14 illustrated in FIG. 2, each line is configured by four ways (Way 1 to 4).

Here, the cache set will be described.
FIG. 3 is a conceptual diagram showing the configuration of a cache set stored in the cache memory 14. As shown in FIG. 3, the cache set includes a valid bit, a lock bit, and data (DATA).

  Here, the valid bit indicates whether the stored contents of the corresponding cache set are valid or usable and meaningless invalid. For example, the valid bit is set to “1” when the cache set is valid, and is set to “0” when the cache set is invalid. In the following description, updating of the valid bit is not mentioned, but the valid bit is updated (changed) as needed by the cache controller or the monitoring device 18.

  The lock bit indicates whether the CPU 12 or the monitoring device 18 can change the contents of the corresponding cache set. The lock bit is updated by the monitoring device 18. In this embodiment, when the lock bit is set to '0', the CPU 12 can change the contents of the cache set, and when set to '1', the monitor bit is monitored. The device 18 can change the contents of the cache set. The restriction by the lock bit is only for writing to the cache set, and the reading is not restricted.

  The data is read data from the main storage device 16 and includes, for example, an instruction code string or data string composed of 64 bits. The data also includes the address (ADDRESS) of the main storage device 16 in which this data is stored.

  In the cache memory 14, when the indexes of the addresses of the data included in the cache set (parts composed of a certain number of bits from the most significant bit of the address) are the same, the cache sets are stored in the same line. . For example, if the address is 8 bits and the index is composed of the upper 5 bits of the address, the cache memory 14 stores up to 4 of the 8 cache sets of the same index (corresponding to the remaining 3 bits). The cache set corresponding to the address is stored on the same line.

  It should be noted that, for example, even if one of the ways becomes unavailable, it only functions as a cache memory constituted by three ways, and no extreme performance degradation occurs.

Next, table data stored in the table storage device 20 will be described.
FIG. 4 is a conceptual diagram showing the configuration of table data stored in the table storage device 20. As shown in FIG. 4, the table data includes an access time (AccessTime) and an address (ADDRESS).

  Here, the access time is the time from when the power is turned on to the embedded system 10 until the access from the CPU 12 to the main storage device 16 occurs. In the example of FIG. 4, the access time is represented by the number of clocks (clks). clks is an operation clock of the CPU 12. The address is an address of the main storage device 16 in which data included in the cache set is stored. The address of data included in the cache set and the address included in the corresponding table data are the same.

  Next, the operation of the embedded system 10 will be described according to the flowchart shown in FIG.

  After the power is turned on (S1), the initialization completion register 24 is set to “0” which means that the initialization is not completed. The first execution flag register 26 is set to ‘1’ when executing the first initialization program, and ‘0’ when executing the second and subsequent times.

  After the power is turned on, the monitoring device 18 sets the lock bits of all the cache sets of the ways 1 and 2 among the four ways 1 to 4 of the cache memory 14 to “0” and all the cache sets of the ways 3 and 4. Is set to '1' (S2).

  As a result, in the ways 1 and 2, the CPU 12 manages the writing of the cache set, and in the ways 3 and 4, the management device 18 manages the writing of the cache set.

  Subsequently, the monitoring device 18 checks the value of the initial execution flag register 26, and determines whether or not the current initialization program is executed for the first time (S3). That is, if the value of the initial execution flag register is “1”, the monitoring device 18 executes the initialization program for the first time, and if the value of the initial execution flag register is “0”, It is determined that this initialization program is executed for the second time or later.

  If the current initialization program is executed for the first time (“YES” in S3), the process proceeds to step S5.

  On the other hand, when the initialization program is executed for the second time or later (“NO” in S3), the monitoring device 18 refers to the access time included in the table data (in order from the shortest access time). ) Until the access time is reached or every predetermined time, the table data is read from the table storage device 20, and a predetermined bit length is read from the address of the main storage device 16 corresponding to the address included in the read table data. Data is read, and this is set as a cache set and written to way 3 or 4 of the line (index) of the cache memory 14 corresponding to the address included in the table data (S4).

  As described above, when the initialization program is executed for the second time or later, the monitoring device 18 refers to the access time included in the table data stored at the previous execution and sequentially reaches the access time. Alternatively, data is read from the address of the main storage device 16 corresponding to the address included in the table data and written to the cache memory 14 at predetermined time intervals. This speeds up the execution of the initialization program and shortens the system startup time.

  Note that the control method for overwriting the cache set on the ways 3 to 4 is not limited in any way. For example, LRU (Least Recently Used) control may be used, or the ways 3 and 4 may be overwritten alternately. Good.

  Subsequently, the monitoring device 18 detects whether or not the CPU 12 has accessed the main storage device 16 (S5).

  If there is no access from the CPU 12 to the main storage device 16 (“NO” in S5), the process returns to step S3, and the monitoring device 18 repeats the above-described operation.

  On the other hand, when there is an access from the CPU 12 to the main storage device 16 (“YES” in S5), the monitoring device 18 has table data including the same address as the address of the main storage device 16 accessed by the CPU 12 stored in the table storage device 20. (S6).

  If table data including the same address is not stored (“NO” in S6), the monitoring device 18 creates new table data from the acquired access time and address, and stores this in the table storage device 20. Add (S7). The fact that the CPU 12 has accessed the main storage device 16 means that a cache miss has occurred in the cache memory 14, so if table data including the same address is not stored in the table storage device 20, this will occur. Must be stored in the table storage device 20 in preparation for the second and subsequent execution of the initialization program.

  On the other hand, when table data including the same address is stored (“YES” in S6), the table data stored in the table storage device 20 is not functioning effectively (for example, the monitoring device 18 uses a cache memory). Therefore, the monitoring device 18 rewrites the access time included in the table data including the access destination address to the access time at which the detected access was performed (data was written later to 14). (S8). In this case, it is necessary to similarly rewrite access times of all table data after the corresponding table data.

  The time for the CPU 12 (actually the cache memory 14) to access the main storage device 16 is such that the monitoring device 18 writes (copies) the read data from the main storage device 16 to the cache memory 14, so that the cache memory Since the access to the main storage device 16 from 14 disappears, the time is shortened. For this reason, it is necessary to appropriately adjust (rewrite the access time) the access time set in the table data when the initialization program is executed for the second and subsequent times.

  Here, the method for adjusting the access time is not limited at all, but for example, the table data existing before each table data (table data including an access time shorter than the access time included in each table data). Calculate the cumulative speedup time by multiplying the calculated number of table data and the estimated speedup time per table data, and calculate the cumulative speedup time from the current access time. A method of setting the subtracted value as a new access time can be exemplified.

  Subsequently, the monitoring device 18 checks the value of the initialization completion register 24 and determines whether or not the initialization of the system by the initialization program is completed (whether or not the initialization completion register 24 is set to “1”). Is detected (S9).

  Here, if the initialization completion register 24 is “0” (“NO” in S9), it means that the initialization has not been completed. Therefore, the process returns to step S3, and the monitoring device 18 repeats the above-described operation.

  On the other hand, if the initialization completion register 24 is “1” (“YES” in S9), it means that the initialization is completed, and the monitoring device 18 therefore sets all cache sets in the ways 3 and 4 of the cache memory 14. The lock bit is set to '0' and the operation is terminated (S10).

  Here, the effect of increasing the startup speed of the system according to the present embodiment will be specifically considered. For example, assume that the following instruction is executed when an initialization program is executed.

Instructions without repetition − Cseq times per fixed time Instructions with repetition − Crpt times per fixed time Average number of repetitions − Rrpt times Time to read one instruction from the main memory 16 − Fmain
Time to read one instruction from the cache memory 14-Fcache

  In this case, the speed-up rate of the embedded system 10 is expressed by the following calculation formula.

  Here, for example, numerical values as shown in Table 1 are considered as the number of times of Cseq, Crpt, Rrpt, Fmain, Fcache.

  Substituting the values in Table 1 into the above formula, the speed-up rate is calculated to be about 72%. That is, it can be seen that the embedded system 10 of the present embodiment is three times faster than a conventional embedded system to which the present invention is not applied, and a sufficient effect can be expected.

  This calculation result is an ideal value. Actually, when the instruction execution by the CPU 12 is performed at high speed, the transfer of read data from the main storage device 16 to the cache memory 14 is not in time, so that the maximum effect is obtained. It is not unthinkable that you cannot demonstrate However, even if this point is taken into consideration, it can be said that sufficient speedup can be expected. Even in this case, as represented by the ways 1 and 2 in FIG. 2, the cache area managed by the CPU 12 can be accelerated, so that the speed is not greatly reduced.

  Next, a startup acceleration device according to the present invention will be described with another embodiment.

  The embedded system of this embodiment has the same configuration as that shown in FIG. 1, but the functions of the monitoring device 18 and the table storage device 20 are different.

  In this embodiment, the monitoring device 18 monitors the access from the cache memory 14 to the main storage device 16 at the first system startup, and indexes the address of the access destination main storage device 16 at regular intervals. The number of accesses to a plurality of addresses included in each index is acquired, and the table storage device 20 has the maximum access time from power-on to every fixed time and the number of accesses acquired by the monitoring device 18. The index is stored as table data. The monitoring device 18 corresponds to the index included in the table data, for example, every predetermined time according to the order of the access times included in the table data stored in the table storage device 20 at the second and subsequent system startups. Read data is read from a plurality of addresses of the main storage device 16 and a part of the read data is written to the cache memory 14.

  The table data stored in the table storage device 20 has a format different from that in FIG. The table data used in this embodiment includes an access time (AccessTime) and an index (Index) as shown in FIG.

  Here, the access time is the time from when power is turned on to the embedded system 10 until a certain time. In the example of FIG. 6, the access time is represented by the number of clocks (1 Mclks). 1 Mclks is the time until the clock oscillates 1 million times with the operation clock of the CPU 12 as a reference. The index has a smaller number of bits (the number of bits on the higher bit side of the address) than the index used in the cache memory 14.

  For example, consider the case where the address is 8 bits. When an index used in the cache memory 14 is composed of the upper 5 bits of an address, 8 addresses (corresponding to the remaining 3 bits) are included in one index. As shown in FIG. 7, when the index used in the cache memory 14 is, for example, 10000XXX (index 10000 is a binary number), the address included in this index is XXX = 000 to 111 (XXX is a binary number) A plurality of (eight) addresses up to (display).

  On the other hand, when the index used in the table data is composed of the upper 4 bits of the address, 16 addresses are included in one index. Similarly, as shown in FIG. 7, when the index used in the table data is, for example, 1000XXXX, the addresses included in this index include a plurality (16) of addresses from XXXX = 0000 to 1111.

  That is, the index used in the table data is set so that the number of addresses included in one index is larger than the index used in the cache memory 14.

  In the present embodiment, when the initialization program is executed for the first time, one index is stored as table data once per million times (1 Mclks), in other words, every time that is an integral multiple of 1 Mclks.

  Next, the operation of the embedded system 10 will be described according to the flowchart shown in FIG.

  The operation from step S11 to step S13 is the same as the operation from step S1 to step S3 in FIG.

  Here, when the execution of the initialization program this time is the first execution (“YES” in S13), the monitoring device 18 has accessed the main storage device 16 from the CPU 12 during the next 1 Mclks. The hour index and the number of accesses are acquired (S14).

  Subsequently, the monitoring device 18 detects whether or not the next 1 Mclks boundary has been reached (S15).

  If the next 1 Mclks boundary has not been reached (NO in S15), the process returns to step S14, and the monitoring device 18 repeats the above-described operation.

  On the other hand, when the next 1Mclks boundary is reached (“YES” in S15), the monitoring device 18 uses the access time at that time and the acquired index with the highest number of accesses as a table index. 20 (S16).

  On the other hand, when the current initialization program is executed for the second time or later (“NO” in S13), the monitoring device 18 refers to the access time of the table data (in order from the shortest access time), The table data is read from the table storage device 20 every predetermined time, read data having a predetermined bit length is read from a plurality of addresses of the main storage device 16 corresponding to the index included in the read table data, and the plurality of addresses are read. Two pieces of read data among the data are written as cache sets in ways 3 or 4 of the line of the cache memory 14 (index of the cache memory 14) corresponding to the index of the table data (S17).

  The operations in steps S18 and S19 are the same as the operations in steps S14 and S15.

  Subsequently, in the monitoring device 18, the number of accesses from the CPU 12 to another index (a plurality of addresses included in an index different from the index included in the table data of the corresponding access time) from the CPU 12 exceeds the threshold. It is detected whether or not (S20). The threshold is preferably set to a value equal to or greater than the number of accesses detected when the index included in the corresponding access time table data is acquired.

  If the number of accesses to other indexes does not exceed the threshold (“NO” in S20), the process proceeds to step S22. The fact that the threshold value is not exceeded means that the cache set written to the cache memory 14 in step S17 is functioning effectively, and the cache miss occurring in the cache memory 14 is less than the threshold value. It is not necessary to replace the cache set written in 14.

  On the other hand, when the access count exceeds the threshold (“YES” in S20), the monitoring device 18 rewrites the index included in the corresponding access time table data to an index exceeding the threshold (S21). The fact that the threshold value has been exceeded means that the cache set written to the cache memory 14 in step S17 is not functioning effectively, and the cache memory 14 has generated cache misses that exceed the threshold value. It is necessary to rewrite the index included in the data to an index that exceeds the threshold.

  For this reason, the index set in the table data is appropriately adjusted (the representative index is appropriately changed) when the initialization program is executed for the second and subsequent times.

  Accordingly, when the initialization program is executed next time, a predetermined address (in the case of this embodiment, the first two addresses or a predetermined address) is selected from a plurality of addresses corresponding to the index of the corresponding table data. A cache set corresponding to an interval or the like is written in the cache memory 14.

  The subsequent operations in steps S22 and S23 are the same as the operations in steps S9 and S10 in FIG.

  In the embodiment using the table data shown in FIG. 4, the table storage device 20 having a large memory capacity is required to store the table data for all accesses. On the other hand, in the present embodiment, the table data is stored at a fixed time of 1 Mclks, so that the necessary memory capacity of the table storage device 20 can be reduced as appropriate. Note that it is desirable to set the fixed time as appropriate in consideration of the speed-up rate and the memory capacity.

  On the other hand, in the present embodiment, two 1/8 out of 16 from the main storage device 16 and all the read data cannot be cached. Therefore, in the embodiment using the table data shown in FIG. Compared to the case, the speed-up rate decreases. However, in this case as well, it is possible to increase the number of data that can be cached, and those that are not cached by the monitoring device 18 should be cached by the cache memory managed by the CPU 12, so the speed-up rate is sufficient Is obtained.

  The present invention is not limited to an embedded system, but can be applied to various systems including a CPU, a main storage device, and a cache memory connected between the two. In addition, the specific configuration of the monitoring device is not limited at all, and any configuration can be used as long as it has a similar function. Further, the access time included in the table data is not limited to the number of clocks, and any expression method may be used as long as the time from power-on can be expressed.

The present invention is basically as described above.
Although the present invention has been described in detail above, the present invention is not limited to the above-described embodiment, and it is needless to say that various improvements and modifications may be made without departing from the gist of the present invention.

10 Embedded system 12 CPU
14 cache memory 16 main storage device 18 monitoring device 20 table storage device 22 internal bus 24 initialization completion register 26 first execution flag register

Claims (4)

High-speed startup of a system comprising a CPU, a main storage device storing read data used by the CPU, and a cache memory for temporarily supplying the read data read from the main storage device to the CPU Device.
A monitoring device that monitors the access from the cache memory to the main storage device at the first system startup, and obtains the access time from power-on to the access and the address of the access destination main storage device When,
A table storage device for storing the access time and address acquired by the monitoring device as table data;
The monitoring device corresponds to the address corresponding to the address included in the table data before reaching the access time according to the order of the access time included in the table data stored in the table storage device at the second or subsequent system startup. A start-up acceleration device characterized in that read data is read from an address of a main storage device, and the read data is written to the cache memory.   The monitoring device detects that the main memory is accessed from the cache memory at the second and subsequent system startups, and stores the table data including the access destination address in the table memory. 2. The startup acceleration device according to claim 1, wherein when the access is performed, the access time included in the table data including the address of the access destination is rewritten to the access time when the detected access is performed. High-speed startup of a system comprising a CPU, a main storage device storing read data used by the CPU, and a cache memory for temporarily supplying the read data read from the main storage device to the CPU Device.
When the system is started for the first time, the access from the cache memory to the main storage device is monitored, and is included in each index consisting of some bits of the address of the main storage device to be accessed at regular intervals. A monitoring device that obtains the number of accesses to a plurality of addresses,
A table storage device that stores, as table data, an access time from power-on to the predetermined time and an index with the maximum number of accesses acquired by the monitoring device;
The monitoring device has a plurality of addresses of the main storage device corresponding to the index included in the table data in accordance with the order of access times included in the table data stored in the table storage device at the second or subsequent system startup. Read start data is read out, and a part of the read out read data is written in the cache memory.   The monitoring device, when the system is started for the second time or later, if the number of accesses to a plurality of addresses included in an index different from the index included in the table data exceeds a threshold at each predetermined time, the table The startup acceleration device according to claim 3, wherein an index included in the data is rewritten to an index exceeding the threshold.

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