JP2010225701A - Three-dimensional laminated semiconductor integrated circuit and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To simultaneously achieve an increase in the high density of a through-silicon via, an improvement in a yield on a manufacture and the reduction of a manufacturing cost. <P>SOLUTION: A three-dimensional laminated semiconductor integrated circuit includes: first and second chips C1 and C2 mutually laminated towards the same direction; and the through silicon vias 13 penetrating a first semiconductor substrate 21 configuring the first chip C1 and a second semiconductor substrate 21 configuring the second chip C2 and penetrating first electrodes 14 connected to a semiconductor element mounted in the first chip C1. The first and second chips C1 and C2 are coupled on their surfaces. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a three-dimensional stacked semiconductor integrated circuit and a method for manufacturing the same.

  In recent years, a three-dimensional stacked semiconductor integrated circuit in which a plurality of chips are stacked has been proposed as a method for reducing the increasing wiring delay while increasing the degree of integration of the semiconductor integrated circuit. As one of them, a three-dimensional stacked semiconductor integrated circuit using a through silicon via (TSV) is known.

  The through-silicon via is a via that penetrates a plurality of stacked chips (semiconductor substrates), and is known as an interface technology that interconnects semiconductor integrated circuits formed in the plurality of chips.

  Here, even though the term “through silicon via” is used in this specification, the chip to which it is provided is not limited to silicon (Si).

  Through-silicon vias can easily increase the number of chips that can be mounted in a single package compared to bonding wires, and the parasitic resistance and parasitic capacitance related to the interface can be kept low. is there.

  In order to manufacture such a three-dimensional semiconductor integrated circuit, it is necessary to form through silicon vias in each of a plurality of chips, and then stack the plurality of chips.

  However, in the conventional method, the number of steps required for this stacking is large, which is one of the causes of an increase in manufacturing cost.

  The plurality of stacked chips are fixed to each other by electrodes (micro bumps) arranged between them. Therefore, a technique is adopted in which the size of the electrode in the lateral direction (direction perpendicular to the stacking direction; hereinafter the same) is increased to increase the bonding strength of the plurality of chips. This becomes a factor that hinders high density of through silicon vias.

  Furthermore, without increasing the size of the electrode, it is possible to fill the adhesive between the plurality of electrodes and reinforce the bonding strength of the plurality of chips (see, for example, Patent Documents 1 to 3). When the adhesive is poured, the electrode is destroyed, and a new problem occurs that the manufacturing yield is lowered.

JP 2002-50736 A JP 2001-177047 A JP 2000-252411 A

  The present invention proposes a three-dimensional stacked semiconductor integrated circuit that simultaneously realizes a high density of through silicon vias, an improvement in manufacturing yield, and a reduction in manufacturing cost.

  A three-dimensional stacked semiconductor integrated circuit according to an example of the present invention includes a first chip and a second chip stacked in the same direction, a first semiconductor substrate that forms the first chip, and a second chip. A first via penetrating a second semiconductor substrate and penetrating a first electrode connected to a semiconductor element provided in the first chip is provided, and the first and second chips are coupled by a surface.

  A method of manufacturing a three-dimensional stacked semiconductor integrated circuit according to an example of the present invention includes a step of forming a first semiconductor chip having a first semiconductor substrate and a second chip having a second semiconductor substrate, and the first semiconductor substrate side Bonding the holder to the surface of the first chip opposite to the first chip, polishing the first semiconductor substrate of the first chip bonded to the holder, and the same direction as the first chip Stacking the second chip facing on the first semiconductor substrate to couple the first and second chips, and the second chip coupled to the holder via the first chip. Polishing the semiconductor substrate; and passing through the first and second semiconductor substrates of the first and second chips coupled to the holder and passing through the first electrode in the first chip. Forming a via

  According to the present invention, it is possible to simultaneously increase the density of through silicon vias in a three-dimensional stacked semiconductor integrated circuit, improve the manufacturing yield, and reduce the manufacturing cost.

It is a figure which shows the basic composition of this invention. It is a figure which shows a 1st modification. It is a figure which shows a 2nd modification. It is a figure which shows the shape of an electrode. It is a figure which shows the shape of an electrode. It is a figure which shows all the processes of the manufacturing method of this invention. It is a figure which shows the manufacturing method as a comparative example. It is a figure which shows 1 process of the manufacturing method of this invention. It is a figure which shows 1 process of the manufacturing method of this invention. It is a figure which shows 1 process of the manufacturing method of this invention. It is a figure which shows 1 process of the manufacturing method of this invention. It is a figure which shows 1 process of the manufacturing method of this invention. It is a figure which shows 1 process of the manufacturing method of this invention. It is a figure which shows 1 process of the manufacturing method of this invention. It is a figure which shows 1 process of the manufacturing method as a comparative example. It is a figure which shows 1 process of the manufacturing method as a comparative example. It is a figure which shows 1 process of the manufacturing method as a comparative example. It is a figure which shows 1 process of the manufacturing method as a comparative example. It is a figure which shows 1 process of the manufacturing method as a comparative example. It is a figure which shows 1 process of the manufacturing method as a comparative example. It is a figure which shows 1 process of the manufacturing method as a comparative example. It is a figure which shows 1 process of the modification of the manufacturing method of this invention. It is a figure which shows 1 process of the modification of the manufacturing method of this invention. It is a figure which shows 1 process of the modification of the manufacturing method of this invention. It is a figure which shows 1 process of the modification of the manufacturing method of this invention. It is a figure which shows 1 process of the modification of the manufacturing method of this invention. It is a figure which shows 1 process of the modification of the manufacturing method of this invention. It is a figure which shows 1 process of the modification of the manufacturing method of this invention. It is a figure which shows 1 process of the modification of the manufacturing method of this invention. It is a figure which shows the example of application. It is a figure which shows the example of application.

  The best mode for carrying out an example of the present invention will be described below in detail with reference to the drawings.

1. Basic configuration
In the example of the present invention, the following basic configuration is adopted for a three-dimensional stacked semiconductor integrated circuit in order to simultaneously realize a high density of through silicon vias, an improvement in manufacturing yield, and a reduction in manufacturing cost.

  FIG. 1 shows a basic configuration of a three-dimensional stacked semiconductor integrated circuit.

  The holder 11 constitutes a part of the package. The holder 11 is used to fix a plurality of chips C1, C2, C3, and C4 when manufacturing a three-dimensional stacked semiconductor integrated circuit, and this is used as a part of the package as it is.

  A via 15 extending from the first surface to the second surface is formed in the holder 11, and elements (a plurality of chips C 1, C 2, C 3, C 4) are formed on the second surface of the holder 11 via the via 15. External electrodes (for example, bumps) 16 connected to E (transistor, resistor, capacitor, etc.) E are arranged.

  On the holder 11, a plurality of chips C1, C2, C3, and C4 are stacked on each other in the same direction. In this example, the number of chips C1, C2, C3, and C4 is four. However, the number is not limited to this, and two or more chips may be used.

  On the plurality of chips C1, C2, C3, C4, a cap layer 12 constituting a part of the package is disposed.

  Each of the plurality of chips C1, C2, C3, and C4 includes a semiconductor substrate 21, a plurality of elements E formed on the semiconductor substrate 21, and a multilayer wiring layer 22 that connects between the plurality of elements E in the same chip. The insulating layer 23 covering the multilayer wiring layer 22 and the first electrode 14 disposed in the insulating layer 23 are included.

  Here, the multilayer wiring layer 22 includes a plurality of conductive layers and a plurality of interlayer insulating layers. The insulating layer 23 means an interlayer insulating layer. That is, the first electrode 14 is different from an electrode (for example, a micro bump) formed outside the insulating layer 23.

  The surfaces of the plurality of chips C1, C2, C3, and C4 opposite to the semiconductor substrate 21 side, that is, the surface of the insulating layer 23 are flat. The first electrode 14 may be buried in the insulating layer 23, or only the surface thereof may be exposed from the insulating layer 23.

  The surface of the chip C <b> 1 opposite to the first semiconductor substrate 21 side is coupled to the first surface of the holder 11. This bonding is performed using, for example, an adhesive such as BCB (bis-benzocyclobutene), or an insulating layer (for example, silicon oxide) is provided on the uppermost surface of the chip C1, and the two chips C1 and C2 are connected to the insulating layer. Through thermocompression bonding. In either case, the chips C1 and C2 are bonded to each other, and no electrode (for example, a micro bump) exists between the holder 11 and the chip C1.

  Further, the surface of the chip C2 opposite to the first semiconductor substrate 21 side is coupled to the chip C1. This bonding is performed using, for example, an adhesive, but is a surface-to-surface bonding, and there is no electrode (for example, a micro bump) between the chip C1 and the chip C2.

  Similarly, chip C3 is coupled to chip C2, and chip C4 is coupled to chip C3.

  The through silicon via 13 penetrates through the semiconductor substrate 21 constituting the plurality of chips C1, C2, C3, C4, and penetrates through the first electrode 14 in the plurality of chips C1, C2, C3, C4.

  In this example, the through silicon via 13 is formed by etching in a state where a plurality of chips C 1, C 2, C 3, and C 4 are coupled to the holder 11, so that the through silicon via 13 extends to the holder 11. .

  With such a stacked structure, the through silicon vias 13 can be densified, the manufacturing yield can be improved, and the manufacturing cost can be reduced at the same time.

  FIG. 2 shows a first modification of the basic configuration of FIG.

  This modification is characterized in that the depth (length) of the through silicon via 13 is different.

  The plurality of chips C 1, C 2, C 3 and C 4 have a second electrode 17 different from the first electrode 14. The second electrode 17 is made of a material that functions as an etching stopper when the through silicon via 13 is formed.

  For example, the first electrode 14 is made of aluminum, copper, or the like, and the second electrode 17 is made of tungsten, titanium carbide, tungsten carbide, or the like.

  The through silicon via 13 penetrates the semiconductor substrate 21 constituting the plurality of chips C1, C2, C3, C4 and stops at the second electrode 17 in the plurality of chips C1, C2, C3, C4.

  Even in such a stacked structure, it is possible to simultaneously realize a high density of the through silicon vias 13, an improvement in manufacturing yield, and a reduction in manufacturing cost.

  Of course, the structure of FIG. 1 and the structure of FIG. 2 can be combined.

  FIG. 3 shows a second modification of the basic configuration of FIG.

  This modification is characterized by the structure of the holder 11.

  In the structure of FIGS. 1 and 2, the via 15 and the electrode 16 are formed in the holder 11, but in the structure of FIG. 3, they are not formed in the holder 11.

  In this example, the three-dimensional stacked semiconductor integrated circuit is configured by leaving the holder 11 used at the time of manufacture. The holder 11 may be removed if unnecessary.

  Even in such a stacked structure, it is possible to simultaneously realize a high density of the through silicon vias 13, an improvement in manufacturing yield, and a reduction in manufacturing cost.

2. Electrode shape
The shapes of the electrodes 14 and 17 in the chips C1, C2, C3, and C4 constituting the three-dimensional stacked semiconductor integrated circuit of FIGS. 1 to 3 will be described.

  In the three-dimensional stacked semiconductor integrated circuit according to the example of the present invention, the through silicon via 13 penetrates the electrode 14.

  In this case, the through silicon via 13 contacts only the lateral side surface of the electrode 14. Further, the contact area at this time is substantially smaller than the contact area when the bottom surface of the through silicon via 13 is brought into contact with the electrode 14. This is because the side surface of the through silicon via 13 has irregularities, so that a void is easily formed between the through silicon via 13 and the electrode 14. Due to these causes, the contact resistance increases.

  Therefore, here, a technique for reducing the contact resistance between the through silicon via 13 and the electrode 14 by devising the shape of the electrode 14 will be described.

  FIG. 4 shows an example of the structure of the electrode 14 shown in FIGS.

  The electrode 14 includes a flat portion having a lateral width of W1 × W2 and a height of H1, and a protruding portion protruding in a direction in which the through silicon via 13 extends.

  The protrusion has a width in the horizontal direction of W3 × W4 and a height of H2.

  The through silicon via 13 penetrates the protruding portion.

In this case, when the diameter of the through silicon via 13 is φ, the contact area between the through silicon via 13 and the electrode 14 is (H1 + H2) × φπ. In addition, the contact area when there is no protrusion is H1 × φπ, and the contact area when the bottom surface of the through silicon via 13 is in contact with the electrode 14 is (φ / 2) ² × π.

  Here, as an example, consider a case where W1 = W2 = 2.5 μm, W3 = W4 = 1.5 μm, H1 = 0.3 μm, H2 = 0.7 μm, and φ = 1 μm. However, unevenness on the side surface of the through silicon via is not considered.

In this case, in the structure of FIG. 4, the contact area between the through silicon via 13 and the electrode 14 is about 3 μm ² . In contrast, the contact area in the case where the projecting portion does not exist, the contact area when taking 0.9 .mu.m ^2, and the contact between the electrode 14 on the bottom surface of the through silicon via 13 is about 0.75 .mu.m ^2.

  The contact area when there is no protrusion is almost the same as the contact area when the bottom surface of the through silicon via 13 is in contact with the electrode 14. However, in consideration of the unevenness of the side surface of the through silicon via 13, the contact area when no protrusion is present is substantially smaller than the contact area when the bottom surface of the through silicon via 13 is in contact with the electrode 14. .

  On the other hand, the contact area in the structure of FIG. 4 is more than three times the contact area when the bottom surface of the through silicon via 13 is in contact with the electrode 14. Even if it considers, sufficiently low contact resistance is securable.

  FIG. 5 shows an example of the structure of the electrode 17 shown in FIGS.

  As already described, the electrode 17 has a function as an etching stopper when the through silicon via 13 is formed.

  Therefore, the electrode 17 is composed of only a flat portion and may not have a protruding portion.

  However, as shown in the figure, the shape of the electrode 17 may be a shape having a flat portion and a protruding portion, or may be the same as the shape of the electrode 14.

3. Production method
A method for manufacturing a three-dimensional stacked semiconductor integrated circuit according to an example of the present invention will be described.

  FIG. 6 shows all the steps of the production method of the present invention. FIG. 7 shows all the steps of the manufacturing method as a comparative example.

  Here, in the manufacturing method described below, a chip means one of a plurality of chip areas formed in a wafer or a semiconductor substrate in addition to a single chip. The chip area means a chip in a state before being separated into individual chips by dicing.

(1) Production method of the present invention
Initially, the manufacturing method of this invention is demonstrated, referring the flowchart of FIG. 6, and FIG. 8 thru | or FIG.

  First, a plurality of wafers that have finished the normal front-end process and back-end process are formed (step ST1).

  That is, as shown in FIG. 8, each of the chips C1, C2, C3, and C4 includes a semiconductor substrate 21, a plurality of elements E formed on the semiconductor substrate 21, and a multilayer wiring that connects the plurality of elements E. It has a layer 22, an insulating layer 23 covering the multilayer wiring layer 22, and an electrode 14 formed in the insulating layer 23.

  Next, the first wafer is bonded to the holder (step ST2).

  That is, as shown in FIG. 9, the first surface of the holder 11 and the surface of the chip C1 opposite to the semiconductor substrate 21 are bonded using, for example, a BCB adhesive. Here, since the holder 11 and the chip C1 are bonded to each other on the surface, the bonding strength is increased.

  Next, the first wafer bonded to the holder is polished from the surface opposite to the surface bonded to the holder (step ST3).

  That is, as shown in FIG. 10, the semiconductor substrate 21 constituting the chip C1 is polished and thinned by a method such as CMP. At this time, the holder 11 serves to reinforce the strength of the thinned chip C1.

  Thereafter, the next wafer is bonded to the first wafer (step ST4).

  That is, as shown in FIG. 11, the two chips C1 and C2 are coupled with the two chips C1 and C2 facing in the same direction. Specifically, the back surface (the surface on the semiconductor substrate 21 side) of the chip C1 and the surface of the chip C2 opposite to the semiconductor substrate 21 side are bonded using, for example, a BCB adhesive.

  Here, since the two chips C1 and C2 are coupled with each other, the coupling strength is increased. In addition, since there is no electrode (for example, microbump) between the two chips C1 and C2, the density of the through silicon via can be increased and the manufacturing yield can be improved.

  Next, the next wafer bonded to the holder is polished (step ST5).

  That is, as shown in FIG. 12, the semiconductor substrate 21 constituting the chip C2 is polished and thinned by a method such as CMP.

  Thereafter, steps ST4 and ST5 are repeated until all the wafers are stacked on the holder (step ST6).

  In this example, as shown in FIG. 13, four chips C1, C2, C3, and C4 are stacked on the holder 11. Here, in stacking all these chips, the holder 11 is not removed. For this reason, the number of steps required for stacking is reduced, which can contribute to a reduction in manufacturing cost.

  Finally, a through silicon via is formed (step ST7).

  That is, as shown in FIG. 14, through-holes are formed using an etching method such as ICP (Inductive Coupled Plasma) -RIE (Reactive Ion Etching).

  Further, the inner surface of the through hole is oxidized. Here, a semiconductor substrate (for example, a silicon substrate) is oxidized. The electrodes 14 in the chips C1, C2, C3, and C4 are preferably made of a material that is not easily oxidized or covered with a material that is not easily oxidized.

  Then, the through silicon via 13 is formed by filling the through hole with a conductive material. Since the through silicon via 13 is formed at a time after the four chips C1, C2, C3, and C4 are stacked, the manufacturing process is simplified.

  The conductive material is formed by a method suitable for filling the through hole. For example, the conductive material can be composed of carbon nanotubes that can be grown based on a catalytic metal.

  As a result, the through silicon via 13 penetrates the semiconductor substrate 21 of the four chips C1, C2, C3, and C4 coupled to the holder 11 and is the first in the four chips C1, C2, C3, and C4. It penetrates the electrode 14.

  In this example, since there is no electrode (for example, micro bump) between the four chips C1, C2, C3, and C4, the density of the through silicon via 13 is not affected by the size of the electrode. For this reason, high density of the through silicon via 13 can be realized.

  Moreover, the holder 11 can be used as a package as it is.

  In the manufacturing method of the present invention, in order to increase the alignment accuracy of the four chips C1, C2, C3, and C4 to be stacked, for example, alignment using an infrared aligner or alignment using an inductive coupling alignment sensor is used in combination. May be.

  Here, the inductive coupling is an alignment technique using a magnetic force generated by a magnetic field generated by an inductor.

(2) Manufacturing method as a comparative example
Next, a manufacturing method as a comparative example will be described with reference to the flowchart of FIG. 7 and FIGS. 15 to 20.

  First, a plurality of wafers that have finished the normal front-end process and back-end process are formed (step ST1).

  Here, the through silicon via 13 is formed for each wafer in the back-end process.

  That is, as shown in FIG. 15, each of the chips C1, C2, C3, and C4 includes a semiconductor substrate 21, an element E formed on the semiconductor substrate 21, insulating layers 22 and 23 covering the element E, and an insulating material. The electrode 14 is formed in the layer 23 and the through silicon via 13 connected to the electrode 14.

  Next, the first wafer is attached to the holder (step ST2).

  That is, as shown in FIG. 16, the first surface of the holder 31 and the surface of the chip C2 opposite to the semiconductor substrate 21 side are bonded using, for example, an adhesive.

  Next, the first wafer bonded to the holder is polished (step ST3).

  That is, as shown in FIG. 17, the semiconductor substrate 21 constituting the chip C2 is polished by a method such as CMP to reduce its thickness. By polishing the semiconductor substrate 21, one end of the through silicon via 13 is exposed from the semiconductor substrate 21. At this time, the holder 31 serves to reinforce the strength of the thinned chip C2.

  Thereafter, the first wafer is bonded to another wafer (step ST4).

  That is, as shown in FIG. 18, first, the chip C1 is prepared. Then, the two chips C1 and C2 are coupled with the two chips C1 and C2 facing in the same direction. Specifically, the back surface (the surface on the semiconductor substrate 21 side) of the chip C2 and the surface of the chip C1 opposite to the semiconductor substrate 21 side are coupled to each other through, for example, micro bumps 24.

  Here, since the two chips C1 and C2 are coupled via the micro bumps 24, the coupling strength is generally weak.

  Therefore, as shown in FIG. 19, for example, an adhesive 25 may be interposed between the two chips C1 and C2. However, in this case, there is a risk that the microbumps 24 are destroyed by the stress of the adhesive 25.

  Next, the holder is removed (step ST5).

  That is, as shown in FIG. 20, the holder 31 is separated from the two stacked chips C1 and C2.

  Thereafter, step ST3 and step ST4 are repeated until all the wafers are stacked on the holder (step ST6).

  That is, the next wafer is attached to the holder (step ST7), polished (step ST3), and then the next wafer is bonded onto the first wafer (step ST4).

  In this example, as shown in FIG. 21, four chips C1, C2, C3, and C4 are stacked. Here, in stacking all these chips, in the comparative example, the attachment and detachment of the holder 11 are repeated.

  There is a possibility that the bonding between the micro-bump and the through-silicon via may be disconnected due to repeated mounting and removal of the holder 11. If even this part of the joint is removed, the entire integrated circuit becomes defective.

  Further, the holder 31 cannot be used as a package as it is.

(3) Advantage of the manufacturing method of the present invention
As mentioned above, although the manufacturing method of this invention was demonstrated with the comparative example, the manufacturing method of this invention has the following advantages with respect to a comparative example.

First, there is no need to repeat the attachment and removal of the retainer.
Secondly, there is no need to handle thinned wafers individually.
Third, it is not necessary to form through silicon vias for each chip.
Fourth, there is no need for micro bumps between chips.

  Fifth, the holder can be used as a package.

  From such advantages, it is possible to simultaneously increase the density of through silicon vias in a three-dimensional stacked semiconductor integrated circuit, improve the manufacturing yield, and reduce the manufacturing cost.

(4) Modification of the production method of the present invention
In a three-dimensional stacked semiconductor integrated circuit having through silicon vias, alignment when stacking a plurality of chips is important.

  Here, in the manufacturing method of the present invention, the alignment when stacking a plurality of chips becomes difficult due to the feature that the attachment and removal of the holder are not repeated.

  That is, in the manufacturing method as a comparative example, for example, as shown in FIG. 18, the chip C2 is stacked on the surface of the chip C1 opposite to the semiconductor substrate 21 (on the insulating layer 23). It is easy to recognize alignment marks formed on the surface (on the insulating layer 23). The same applies to the case where the chip C3 is further stacked on the chip C2.

  On the other hand, in the manufacturing method of the present invention, for example, as shown in FIG. 11, since the chip C2 is stacked on the back surface of the chip C1 on the semiconductor substrate 21 side, on the surface of the chip C1 (on the insulating layer 23). It is difficult to recognize the alignment mark formed on the surface. The same applies to the case where the chip C3 is further stacked on the chip C2.

  Therefore, in order to make the manufacturing method of the present invention effective, it is necessary to study an alignment technique for stacking a plurality of chips.

  This problem can be dealt with by combining, for example, alignment using an infrared aligner and alignment using an inductive coupling alignment sensor, as already described in the manufacturing method of the present invention.

  In addition to this, the following problems can be solved by the following manufacturing method. The manufacturing method will be described with reference to the flowchart of FIG. 6 and FIGS. 22 to 29.

  First, a plurality of wafers that have finished the normal front-end process and back-end process are formed (step ST1).

  That is, as shown in FIG. 22, the chips C1, C2, C3, and C4 are insulated from the semiconductor substrate 21, the element E formed on the semiconductor substrate 21, and the insulating layers 22 and 23 covering the element E, respectively. The electrode 14 formed in the layer 23 and the alignment mark 41 formed on the insulating layer 23 are included.

  Next, the first wafer is bonded to the holder (step ST2).

  That is, as shown in FIG. 23, the first surface of the holder 11 and the surface of the chip C1 opposite to the semiconductor substrate 21 are bonded using, for example, an adhesive. Here, since the holder 11 and the chip C1 are bonded to each other on the surface, the bonding strength is increased.

  Next, the first wafer bonded to the holder is polished (step ST3).

  That is, as shown in FIG. 24, the semiconductor substrate 21 constituting the chip C1 is polished by a method such as CMP to reduce its thickness. At this time, the holder 11 serves to reinforce the strength of the thinned chip C1.

  Further, the semiconductor substrate 21 and the insulating layers 22 and 23 of the chip C1 on the alignment mark 41 are removed by an etching method such as RIE to expose the alignment mark 41. Then, the concave portion on the alignment mark 41 is filled with an optically transparent material 42-1, for example, a material that transmits infrared rays, so that the alignment mark 41 can be recognized.

  The recess on the alignment mark 41 may be left in a space without being filled with the optically transparent material 42-1.

  Thereafter, the next wafer is bonded to the first wafer (step ST4).

  That is, as shown in FIG. 25, the two chips C1 and C2 are coupled with the two chips C1 and C2 facing in the same direction. Specifically, the back surface (the surface on the semiconductor substrate 21 side) of the chip C1 and the surface of the chip C2 on the opposite side to the semiconductor substrate 21 side are bonded using, for example, an adhesive.

  Here, since the two chips C1 and C2 are coupled with each other, the coupling strength is increased. In addition, since there is no electrode (for example, a micro bump) between the two chips C1 and C2, the manufacturing yield can be improved.

  Further, when the chip C2 is stacked on the chip C1, the alignment mark of the chip C1 can be clearly recognized, so that high-precision alignment is possible.

  Next, the next wafer bonded to the holder is polished (step ST5).

  That is, as shown in FIG. 25, the semiconductor substrate 21 constituting the chip C2 is polished and thinned by a method such as CMP.

  Further, as shown in FIG. 26, the semiconductor substrate 21 and the insulating layers 22 and 23 of the chip C2 on the alignment mark 41 are removed by an etching method such as RIE.

  Then, as shown in FIG. 27, the concave portion on the alignment mark 41 is filled with an optically transparent material 42-2, for example, a material that transmits infrared rays, so that the alignment mark 41 can be recognized.

  The concave portion on the alignment mark 41 may be left as a space without being filled with the optically transparent material 42-2.

  Thereafter, steps ST4 and ST5 are repeated until all the wafers are stacked on the holder (step ST6).

  In this example, four chips C1, C2, C3, and C4 are stacked on the holder 11 as shown in FIG. Here, in stacking all these chips, the holder 11 is not removed. For this reason, the number of steps required for stacking is reduced, which can contribute to a reduction in manufacturing cost.

  Further, when the chips C3 and C4 are stacked, the alignment mark of the chip C1 can be clearly recognized, so that highly accurate alignment is possible.

  Finally, a through silicon via is formed (step ST7).

  That is, as shown in FIG. 29, through holes are formed using an etching method such as ICP-RIE.

  Further, the inner surface of the through hole is oxidized. Here, a semiconductor substrate (for example, a silicon substrate) is oxidized. The electrodes 14 in the chips C1, C2, C3, and C4 are preferably made of a material that is not easily oxidized or covered with a material that is not easily oxidized.

  Then, the through silicon via 13 is formed by filling the through hole with a conductive material. Since the through silicon via 13 is formed at a time after the four chips C1, C2, C3, and C4 are stacked, the manufacturing process is simplified.

  In this example, since there is no electrode (for example, a micro bump) between the four chips C1, C2, C3, and C4, the density of the through silicon via 13 is not affected by the size of the electrode. For this reason, high density of the through silicon via 13 can be realized.

  When the insulating layers 22 and 23 are made of an optically transparent material, it is not necessary to etch the insulating layers 22 and 23 in order to expose the alignment marks.

4). Application examples
An example of a three-dimensional stacked semiconductor integrated circuit to which the present invention is applied is shown below.

FIG. 30 shows a semiconductor integrated circuit composed of two chips.
This semiconductor integrated circuit functions as, for example, a processor. In this case, the chip C1 is, for example, a bus circuit, and the chip C2 is, for example, a CPU core.

FIG. 31 shows a semiconductor integrated circuit composed of three chips.
This semiconductor integrated circuit functions as, for example, a processor. In this case, each of the chips C1 and C2 is, for example, a cache memory, and the chip C3 is, for example, a CPU core.

  Further, this semiconductor integrated circuit functions as, for example, a system LSI. In this case, each of the chips C1 and C2 is, for example, a DRAM, and the chip C3 is, for example, a CPU core.

  Furthermore, this semiconductor integrated circuit functions as, for example, a NAND storage. In this case, the chip C1 is, for example, a NAND controller, and the chips C2 and C3 are, for example, NAND flash memories.

6). Conclusion
According to the present invention, it is possible to simultaneously increase the density of through silicon vias in a three-dimensional stacked semiconductor integrated circuit, improve the manufacturing yield, and reduce the manufacturing cost.

  The example of the present invention is not limited to the above-described embodiment, and can be embodied by modifying each component without departing from the scope of the invention. Various inventions can be configured by appropriately combining a plurality of constituent elements disclosed in the above-described embodiments. For example, some constituent elements may be deleted from all the constituent elements disclosed in the above-described embodiments, or constituent elements of different embodiments may be appropriately combined.

  The present invention is applicable to a three-dimensional stacked semiconductor integrated circuit having through silicon vias, and has a great industrial advantage.

  11, 31: Holder, 12: Cap layer, 13: Through-silicon via, 14, 16, 17: Electrode, 15: Via, 21: Semiconductor substrate, 22, 23: Insulating layer, 24: Micro bump, 25: Adhesion Agent, C1, C2, C3, C4: Chip.

Claims (6)

  The first and second chips stacked in the same direction, the first semiconductor substrate constituting the first chip and the second semiconductor substrate constituting the second chip, and in the first chip A three-dimensional stacked semiconductor integrated circuit comprising: a first via penetrating a first electrode connected to a semiconductor element provided in the first and second chips, wherein the first and second chips are coupled to each other in a plane.   The first, second and third chips stacked in the same direction, the first semiconductor substrate constituting the first chip, the second semiconductor substrate constituting the second chip, and the third chip are constituted. A first via penetrating a third semiconductor substrate and penetrating a first electrode connected to a semiconductor element provided in the first chip, wherein the first, second and third chips face each other A three-dimensional stacked semiconductor integrated circuit characterized by being coupled with each other.   3. The device according to claim 1, further comprising a second via that penetrates through the first and second semiconductor substrates and stops at a second electrode connected to a semiconductor element provided in the first chip. Three-dimensional stacked semiconductor integrated circuit.   A holder in which a surface of the first chip opposite to the first semiconductor substrate is coupled to a first surface, and an external electrode connected to the first electrode in the first chip is disposed on a second surface The three-dimensional stacked semiconductor integrated circuit according to claim 1, further comprising:   The first electrode includes a flat portion and a protruding portion protruding in a direction in which the first via extends, and the first via penetrates the flat portion and the protruding portion. 5. The three-dimensional stacked semiconductor integrated circuit according to any one of items 1 to 4.   Forming a first semiconductor chip having a first semiconductor substrate and a second chip having a second semiconductor substrate, and bonding a holder to the surface of the first chip opposite to the first semiconductor substrate side; Polishing the first semiconductor substrate of the first chip coupled to the holder, and stacking the second chip facing the same direction as the first chip on the first semiconductor substrate. And bonding the second chip; polishing the second semiconductor substrate of the second chip bonded to the holder via the first chip; and the first chip bonded to the holder And forming a first via penetrating the first and second semiconductor substrates of the second chip and penetrating the first electrode in the first chip. Type semiconductor integrated circuit manufacturing method.

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