JP2010225218A - Nonvolatile storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile storage device in which recorded information can be erased efficiently and collectively. <P>SOLUTION: The nonvolatile storage device is provided with a storage element part having a plurality of first wiring extended to a first direction, a plurality of second wiring extended to a second direction being not in parallel to the first direction, and a plurality of recording layers which are held between the first wiring and the second wiring and which can be transited reversibly between the first state and the second state by a current supplied through the first wiring and the second wiring; and an erasing part raising collectively at least any temperature out of a plurality of recording layers and erasing information recorded in the recording layer. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a nonvolatile memory device.

  In a NAND-type nonvolatile memory device using a transistor, device operation has become difficult due to the influence of a so-called short channel effect accompanying the miniaturization of the device. The “short channel effect” is a phenomenon that occurs when the distance between the source portion and the drain portion is reduced due to miniaturization of the device, and includes, for example, an increase in leakage current that occurs between the source and the drain. Therefore, a memory device that replaces the memory device using a transistor is required. As one of them, a nonvolatile memory device (resistance-change memory, ReRAM) using a characteristic that resistance of a substance changes when an electric field pulse is applied to a transition metal insulating film or the like has been studied (for example, Patent Document 1). See).

  In order to perform a recording (writing) operation in such a nonvolatile memory device (resistance change type memory, ReRAM), a voltage is applied to a selected memory cell, and a potential gradient is generated in the memory cell to generate a current. A pulse is made to flow. A recording (writing) operation is performed by changing the resistance state of the memory cell by applying an electric field pulse.

The read operation is performed by flowing a current pulse through the selected memory cell and detecting the resistance value of the memory cell.
In order to perform the erase (reset) operation, a large current pulse is supplied to the selected memory cell, and the resistance state of the memory cell is returned to the original state by using the generated Joule heat. Therefore, the erase operation is performed only in the selected memory cell.

  However, depending on the usage environment of the nonvolatile storage device, it may be preferable to erase a predetermined amount of recorded information all at once. For example, when taking out a non-volatile storage device from an information management area, it may be preferable to forcibly and efficiently erase all recorded information collectively.

JP 2007-149170 A

  The present invention provides a non-volatile storage device that can efficiently erase a predetermined amount of recorded information collectively.

  According to one aspect of the present invention, a plurality of first wirings extending in a first direction, a plurality of second wirings extending in a second direction non-parallel to the first direction, Between the first state and the second state by a current sandwiched between the first wiring and the second wiring and supplied via the first wiring and the second wiring. A storage element unit having a plurality of reversibly transitionable recording layers, and an erasing unit that collectively raises the temperature of at least one of the plurality of recording layers and erases information recorded on the recording layer And a non-volatile storage device characterized by comprising:

  According to the present invention, there is provided a non-volatile storage device that can efficiently and collectively erase a predetermined amount of recorded information.

1 is a schematic diagram of a nonvolatile memory device according to an embodiment of the present invention. It is a schematic cross section of a non-volatile memory device. It is a schematic cross section for illustrating the case where two or more layers of a memory cell are provided. It is a schematic diagram for illustrating the case where the erase | elimination part is provided in the insulating layer between elements. It is a schematic cross section for illustrating the case where the erasing part and the memory element part are provided separately.

Hereinafter, embodiments of the present invention will be illustrated with reference to the drawings. In addition, in each drawing, the same code | symbol is attached | subjected to the same component and detailed description is abbreviate | omitted suitably.
FIG. 1 is a schematic diagram of a nonvolatile memory device according to an embodiment of the present invention. 1A is a schematic perspective view of a nonvolatile memory device, and FIG. 1B is a schematic circuit diagram of a memory element portion of the nonvolatile memory device.
FIG. 2 is a schematic cross-sectional view of a nonvolatile memory device. 2A is a schematic cross-sectional view of the nonvolatile memory device viewed from the first direction (X-axis direction), and FIG. 2B is a cross-sectional view taken along the line AA in FIG. is there.
Note that one recording unit 40 provided in a region where one first wiring 20 and one second wiring 50 intersect is one recording unit element, which is referred to as a “memory cell”.
FIGS. 1 and 2 show a case where the number of memory cell layers is one, but the present invention is not limited to this. A plurality of memory cell layers may be provided so as to be stacked.

  FIG. 3 is a schematic cross-sectional view for illustrating a case where a plurality of memory cell layers are provided. FIG. 3 exemplifies memory cells stacked in two layers as an example. 3A illustrates a case where word lines of stacked memory cells are provided for each layer, and FIG. 3B illustrates a case where word lines of stacked memory cells are shared. Is.

As shown in FIG. 1A, the nonvolatile memory device 1 includes a memory element unit 2 and an erasing unit 3.
First, the memory element unit 2 will be illustrated.
The memory element unit 2 is provided on the main surface of the substrate 10, the first wiring 20 (bit line BL) extending in the first direction (X-axis direction), the first direction, Sandwiched between the second wiring 50 (word line WL) extending in the non-parallel (crossing) second direction (Y-axis direction) and the first wiring 20 and the second wiring 50; A recording layer 44 that can reversibly transition between a first state and a second state by a current supplied via the first wiring 20 and the second wiring 50 is provided.

  In addition, a rectifying element 30 is provided between the first wiring 20 and the recording layer 44 so as to be sandwiched between them. Here, the “main surface” means a surface (in FIG. 1) perpendicular to the direction in which the first wiring 20, the rectifying element 30, the recording layer 44, etc. are stacked (in FIG. 1, the Z-axis direction; the vertical direction). , XY plane).

In addition, as shown in FIG. 2, electrode layers 42 and 46 that sandwich the recording layer 44 may be provided on both sides of the recording layer 44 in the Z-axis direction. Here, the recording layer 44 and the electrode layers 42 and 46 are collectively referred to as a “recording unit 40”. Further, a barrier layer 32 may be provided between the first wiring 20 and the rectifying element 30.
A conductive material can be used for the wiring L (the first wiring 20 and the second wiring 50). Further, it can be a material having heat resistance. For example, tungsten (W) can be used as a material having conductivity and heat resistance.

  As shown in FIGS. 1 and 2, a stopper layer 52 required in the manufacturing process (planarization process) is provided between the recording layer 44 (recording unit 40) and the second wiring 50. can do. In this case, for example, when a CMP (Chemical Mechanical Polishing) method is used in the planarization step, the stopper layer 52 can be a CMP stopper layer. However, the stopper layer 52 is not necessarily required and may be provided as necessary. For example, if the electrode layer 46 is sufficiently thick and the electrode layer 46 is given the function of a stopper layer, the stopper layer 52 need not be provided.

  Here, if the stopper layer 52 and the second wiring 50 are formed of the same material, the two layers are integrated to serve as the second wiring. The second wiring in such a case is referred to as “second wiring 54”. Therefore, the second wiring 54 has a protruding portion (stopper layer 52) protruding toward the recording layer 44 in each memory cell.

The rectifying element 30 has a rectifying characteristic and is provided to give direction to the polarity of the voltage applied to the recording layer 44. Examples of the rectifying element 30 include a PN junction diode, a Zener diode, and a Schottky diode.
FIG. 1 illustrates the case where the rectifying element 30 is provided between the bit line BL and the electrode layer 42, but the rectifying element 30 is provided between the word line WL and the electrode layer 46. Also good. The rectifying element 30 may be provided in a region other than the region where the bit line BL and the word line WL are opposed to each other.
A barrier layer 32 can be provided between the first wiring 20 and the rectifying element 30 in order to suppress diffusion of elements between them.

Next, the recording unit 40 will be illustrated with reference to FIG.
As illustrated in FIG. 2, the recording unit 40 includes a recording layer 44 and electrode layers 42 and 46 that sandwich the recording layer 44 from the Z-axis direction (vertical direction).
The electrode layers 42 and 46 are provided as necessary so that the recording layer 44 can easily obtain electrical connection. The electrode layers 42 and 46 may also have a function as a barrier layer for suppressing element diffusion between the recording layer 44 and constituent elements in the Z-axis direction (vertical direction), for example. Good.

Next, the recording layer 44 is illustrated.
As will be described later, the memory element unit 2 can change the voltage applied to each recording unit 40 by a combination of potentials applied to the first wiring 20 and the second wiring 50. Information can be recorded (written) or erased according to the characteristics (for example, resistance value) of the recording unit 40 at that time. Therefore, the characteristics of the recording layer 44 are changed depending on the applied voltage. Examples of the recording layer 44 include a variable resistance layer whose resistance value can be reversibly transitioned and a phase change layer capable of reversibly transitioning between a crystalline state and an amorphous state by an applied voltage. can do.

Moreover, as a material of the recording layer 44, a metal oxide can be illustrated, for example. In this case, for example, chromium (Cr), tungsten (W), vanadium (V), niobium (Nb), tantalum (Ta), titanium (Ti), zirconium (Zr), hafnium (Hf), scandium (Sc), Yttrium (Y), Thorium (Tr), Manganese (Mn), Iron (Fe), Ruthenium (Ru), Osmium (Os), Cobalt (Co), Nickel (Ni), Copper (Cu), Zinc (Zn), Cadmium (Cd), aluminum (Al), gallium (Ga), indium (In), silicon (Si), germanium (Ge), tin (Sn), lead (Pb), antimony (Sb), bismuth (Bi), Alternatively, oxides such as so-called rare earth elements from lanthanum (La) to lutetium (Lu) can be used.
Alternatively, aluminum oxide (Al ₂ O ₃ ), copper oxide (CuO), silicon oxide (SiO ₂ ), or the like can be used.

Moreover, it can also be set as complex oxide. In this case, for example, barium titanate (BaTiO ₃ ), strontium titanate (SrTiO ₃ ), calcium titanate (CaTiO ₃ ), potassium niobate (KNbO ₃ ), bismuth iron oxide (BiFeO ₃ ), lithium niobate (LiNbO) _3), sodium vanadate _(Na 3 _VO 4), vanadium iron (FeVO _3), titanate vanadium (TiVO _3), chromic acid vanadium (CRVO _3), vanadium, nickel (NiVO _3), magnesium vanadate (MgVO _3), calcium vanadate (Cavo _3), vanadium lanthanum (LaVO _3), molybdate vanadium (VMoO _5), molybdate vanadium _(V 2 _MoO 8), lithium vanadate _{(LiV 2 O} 5), silicates Magne Cium (Mg ₂ SiO ₄ ), magnesium silicate (MgSiO ₃ ), zirconium titanate (ZrTiO ₄ ), strontium titanate (SrTiO ₃ ), lead magnesium acid (PbMgO ₃ ), lead niobate (PbNbO ₃ ), barium borate (BaB ₂ O ₄ ), lanthanum chromate (LaCrO ₃ ), lithium titanate (LiTi ₂ O ₄ ), lanthanum cuprate (LaCuO ₄ ), zinc titanate (ZnTiO ₃ ), calcium tungstate (CaWO ₄ ), etc. can do.

Also, a chalcogenide-based variable resistance material can be used. Chalcogenide is a general term for compounds containing group 16 elements such as Se and Te, and is derived from the fact that group 16 elements are called chalcogens. This chalcogenide-based material is a kind of variable resistance material that can reversibly transition between a crystalline state and an amorphous state by applying a voltage.
Further, as the material of the recording layer 44, carbon (C) can also be used. In this case, the carbon nanotube-like structure can be used, and nitrogen-doped amorphous carbon (ta-C: N; nitrogen doped tetrahedral amorphous carbon) can also be used.
Further, an inter-element insulating layer 70 is provided between the memory cells as shown in FIG.

Further, a contact plug (not shown) is provided on the outside in the extending direction of the wiring L (first wiring 20 and second wiring 50; bit line BL and word line WL) with reference to the position of the memory cell. The contact plug is connected to a peripheral circuit (not shown) such as a read / record circuit (write circuit) for recording (writing) and reading information (data). A current is passed through the recording unit 40 through the contact plug and the wiring L, whereby various operations such as recording (writing) and erasing of the recording unit 40 can be performed.
As described above, the nonvolatile memory device 1 (memory element unit 2) in which the recording unit 40 is provided at the intersection of the bit line BL and the word line WL is called a so-called cross-point type nonvolatile memory device (memory). It is.

  In addition, the nonvolatile memory device 1 (memory element unit 2) including one layer of memory cells can be used, but the memory cells are stacked in the Z-axis direction (vertical direction) in order to increase the storage capacity. It can also be made. In this case, for example, as shown in FIG. 3A, an interlayer insulating film 71 can be provided so that the second wiring 50 (word line WL) is provided for each layer. Further, for example, as shown in FIG. 3B, the second wirings 50 (word lines WL) can be stacked so as to be shared. 3 illustrates the memory cell layer stacked in two layers as an example, but it may be stacked in three or more layers.

Next, the erasing unit 3 will be illustrated.
In the case of the nonvolatile memory device 1 illustrated in FIGS. 1 and 2, the erasing section 3 is provided on the main surface of the second wiring 50 via the insulating layer 4.
The erasing unit 3 is provided for collectively erasing information recorded (written) on each recording layer 44 (a predetermined amount of information in the entire nonvolatile memory device 1).
As described above, when the recording layer 44 is formed of a metal oxide, a composite oxide, or the like, the resistance value can be changed by increasing the temperature of the recording layer 44. For example, by raising the temperature of the recording layer 44, the oxidation reaction can be advanced to make a transition to high resistance.
Even when the recording layer 44 is formed of a chalcogenide-based variable resistance material or the like, the resistance value can be changed by raising the temperature of the recording layer 44. For example, by raising the temperature of the recording layer 44 and then cooling it, the crystalline state can be changed to the amorphous state so that the resistance can be increased.
Therefore, if the erasing unit 3 raises the temperature of each target recording layer 44 at a time, the information recorded (written) on each recording layer 44 can be erased at once. That is, the erasing unit 3 can collectively raise the temperature of the plurality of recording layers 44 in order to erase a predetermined amount of recorded information.

Examples of the erasing unit 3 include a heating element that can generate Joule heat by applying a voltage. In this case, the erasing part 3 can be formed of a material having a high resistivity (for example, a material having a resistivity of about 10 ⁻⁵ Ωcm or more) and high heat resistance. For example, polysilicon, tungsten (W), ruthenium (Ru), rhodium (Rh), iridium (Ir), osmium (Os), and oxides thereof, titanium nitride (TiN), silicon carbide (SiC), etc. can do. If the material of the erasing unit 3 and the material of the elements (for example, the first wiring 20 and the second wiring 50) constituting the memory element unit 2 are the same, the production process can be simplified. it can. However, the material of the erasing part 3 is not limited to the illustrated material, and can be changed as appropriate.

Further, the erasing unit 3 is provided on the main surface of the second wiring 50 via the insulating layer 4, but the erasing unit 3 is interposed between the first wiring 20 and the substrate 10 via the insulating layer 4. Can also be provided.
However, in consideration of the thermal influence on the rectifying element 30, it is preferable to provide the erasing unit 3 and the rectifying element 30 at positions facing each other across the recording layer 44. That is, it is preferable to provide the erasing unit 3 so as to be closer to the recording layer 44 than the rectifying element 30.

  Further, when a plurality of memory cell layers are provided, the erasing section 3 can be provided for each layer via the insulating layer 4 as shown in FIG. As shown in b), one erasing portion 3 may be provided via the insulating layer 4.

As mentioned above, although an example of the non-volatile memory device 1 was illustrated, it is not necessarily limited to the configuration described above, and can be changed as appropriate.
For example, the number, arrangement, and the like of the first wiring 20, the second wiring 50, and the memory cells are not limited to those illustrated in FIG. 1, and can be changed as appropriate.
In the case described above, the first wiring 20 is called a “bit line BL” and the second wiring 50 is called a “word line WL”. Conversely, the first wiring 20 is called a “word line”. WL ”and the second wiring 50 may be called“ bit line BL ”.
Further, the same kind of wiring (for example, two bit lines BL or two word lines WL) may be arranged at both ends in the Z-axis direction (vertical direction) of the nonvolatile memory device 1, and different kinds of wiring (for example, for example, Bit lines BL and word lines WL) may be arranged.

  Next, a case where a recording (writing) operation to a memory cell, a reading operation, and an erasing operation in a normal use state will be described. The operation of erasing a predetermined amount of recorded information all at once will be described later.

In order to perform a recording (writing) operation, a voltage is applied to a selected memory cell, a potential gradient is generated in the memory cell, and a current pulse is supplied. In this case, for example, the bit line BL may be grounded and a negative potential may be applied to the word line WL so that the potential of the word line WL is relatively lower than the potential of the bit line BL.
Since the selected memory cell has electronic conductivity due to phase change or the like, the recording (writing) operation is completed.
Note that the current pulse for the recording (writing) operation may be generated by creating a state in which the potential of the word line WL is relatively higher than the potential of the bit line BL.

  The read operation is performed by passing a current pulse through the selected memory cell and detecting the resistance value of the memory cell. However, the current pulse needs to have a minute value that does not cause a change in resistance of the material constituting the memory cell.

  In order to perform an erasing (reset) operation in a normal use state, the selected memory cell may be Joule-heated by a large current pulse to restore the resistance state of the memory cell.

Next, an operation for erasing a predetermined amount of recorded information at once is illustrated.
Depending on the usage environment of the nonvolatile storage device 1 and the like, it may be preferable to erase all of the recorded information in a batch. For example, when taking out the non-volatile storage device 1 from the information management area, it may be preferable to forcibly erase all of the recorded information in a batch.
Therefore, in the nonvolatile memory device 1, all of the information amount recorded by the action of the erasing unit 3 can be erased collectively.

  In order to erase the recorded information all at once, a voltage is applied to the erasing unit 3 that is a heating element to generate Joule heat. Then, the generated Joule heat is applied to raise the temperature of each recording layer 44 at a time, so that the information recorded in all the memory cells is erased at a time.

  In addition, a voltage can be applied to the erasing unit 3 that is a heating element, and a voltage can be applied to all the memory cells to generate Joule heat in the erasing unit 3 and the memory cells. By doing so, the temperature of each recording layer 44 can be increased efficiently. Further, the erasing time can be shortened. Further, since the voltage applied to the memory cell can be lowered, the burden on the recording layer 44 and the like can be reduced.

1 to 3 are provided such that the erasing unit 3 and the memory element unit 2 are stacked, the present invention is not limited to this.
For example, the erasing unit 3 can be provided between the first wiring 20 and the second wiring 50. Alternatively, the erasing part 3 can be provided in the inter-element insulating layer 70.
FIG. 4 is a schematic diagram for illustrating the case where the erasing part 3 is provided in the inter-element insulating layer 70.
As shown in FIG. 4, when the erasing part 3 is provided in the inter-element insulating layer 70, it is preferably provided so as to be close to the recording layer 44. By doing so, heat can be efficiently transferred from the erasing unit 3 to the recording layer 44.
In the example illustrated in FIG. 4, the erasing unit 3 is provided substantially parallel to the first wiring 20, but the erasing unit 3 may be provided substantially parallel to the second wiring 50.

Further, the erasing unit 3 and the memory element unit 2 can be provided separately from each other.
FIG. 5 is a schematic cross-sectional view for illustrating a case where the erasing unit 3 and the storage element unit 2 are provided apart from each other.
As shown in FIG. 5A, the erasing section 3 and the storage element section 2 can be provided separately from each other inside a package 5 made of resin, ceramics, or the like. For example, the erasing unit 3 and the memory element unit 2 can be separated from each other inside the package 5 by resin molding in a state where the erasing unit 3 and the memory element unit 2 are separated from each other or by being housed in a ceramic package. Can be provided.

  Further, as shown in FIG. 5B, the erasing section 3 and the storage element section 2 can be provided separately on the lead frame 6. In this case, the erasing unit 3 and the storage element unit 2 can be provided on the same side surface of the lead frame 6 or can be provided on the opposite sides of the lead frame 6. it can. If the erasing unit 3 and the storage element unit 2 are provided in the lead frame 6, the lead frame 6 can be used as a heat transfer body.

The above is a case where the erasing unit 3 is used as a heating element and a voltage is applied to the erasing unit 3 to cause the erasing unit 3 to generate heat, but is not limited thereto.
For example, the erasing unit 3 may include a heating element that generates Joule heat by applying a voltage, and a heat transfer body that transmits the generated Joule heat to the recording layer 44. The heat transfer body and the storage element unit 2 can be provided so as to be laminated, or the heat transfer body can be provided in the inter-element insulating layer 70 in the vicinity of the recording layer 44. In such a case, what is necessary is just to thermally connect a heat generating body and a heat exchanger. That is, a heat transfer body may be provided at the position of the erasing unit 3 illustrated in FIGS. 1 to 5 and the heat transfer body and the heating element may be thermally connected.

In this case, the heat transfer body can be formed from a metal such as aluminum or copper having a high heat transfer coefficient. In addition, the heating element can be made of a material having a high resistivity (for example, a material having a resistivity of about 10 ⁻⁵ Ωcm or more).
A voltage can be applied to the heating element to generate Joule heat, and the heat can be transmitted to the recording layer 44 via the heat transfer element.
In this way, since the heating element to which a voltage is applied can be separated from the recording layer 44 and the like, the electric field generated when the recorded information is erased all at once has an influence on the recording layer 44 and the like. Can be suppressed. In particular, even if a heat transfer body is provided in the vicinity of the recording layer 44, the influence of the electric field on the recording layer 44 can be suppressed. Therefore, since a heat transfer body can be provided in the vicinity of the recording layer 44, the heating efficiency can be improved.

  In addition, the above description is a case where the erasing unit 3 has a heating element. For example, the erasing unit 3 can be a control circuit that can apply a voltage to all the memory cells. That is, the erasing unit 3 can be a control circuit that collectively applies a voltage to all of a plurality of regions where the plurality of first wirings 20 and the plurality of second wirings 50 intersect. It is also possible to receive a signal from the outside and apply a voltage to all the memory cells to generate Joule heat so that the temperature of each recording layer 44 is raised all at once. Therefore, according to such a control circuit (erase unit 3), all the recorded information can be erased collectively.

When the erase unit 3 is a control circuit that can apply a voltage to all memory cells, or when a voltage is applied to the erase unit 3 that is a heating element and a voltage is also applied to all memory cells. Is a heater layer (for example, a layer formed of a material having a resistivity of about 10 ⁻⁵ Ωcm or more) on the cathode side of the recording layer 44 (in the case of the example illustrated in FIG. 1, the word line WL side). It may be provided. In this case, a barrier layer can be provided between the heater layer and the word line WL. By doing so, the recording layer 44 can be efficiently heated.

As illustrated above, according to the present embodiment, a predetermined amount of recorded information can be erased collectively. In this case, for example, a control circuit for operating the erasing unit 3 in response to an external signal can be provided.
Further, depending on the usage environment of the nonvolatile memory device 1 and the like, it is possible to forcibly erase all of the recorded information. For example, when the nonvolatile storage device 1 is taken out from the information management area, the erasing unit 3 is operated in response to an external signal to forcibly erase all of the recorded information. be able to.

Heretofore, the present embodiment has been illustrated. However, the present invention is not limited to these descriptions.
As long as the features of the present invention are provided, those skilled in the art appropriately modified the design of the above-described embodiments are also included in the scope of the present invention.
For example, the shape, size, material, arrangement, and the like of each element included in the nonvolatile memory device 1 are not limited to those illustrated, but can be changed as appropriate.
Moreover, each element with which each embodiment mentioned above is combined can be combined as much as possible, and what combined these is also included in the scope of the present invention as long as the characteristics of the present invention are included.

  DESCRIPTION OF SYMBOLS 1 Nonvolatile memory device, 2 Memory element part, 3 Erase part, 4 Insulating layer, 5 Package, 6 Lead frame, 30 Rectifier element, 44 Recording layer

Claims (7)

A plurality of first wirings extending in a first direction; a plurality of second wirings extending in a second direction non-parallel to the first direction; the first wirings; A plurality of records that can be reversibly transitioned between the first state and the second state by a current that is sandwiched between the first and second wirings and supplied via the first wiring and the second wiring. A storage element portion having a layer;
An erasing unit that collectively raises the temperature of at least one of the plurality of recording layers and erases information recorded on the recording layer;
A non-volatile storage device comprising:   The erasure unit is thermally connected to the recording layer, generates Joule heat by applying a voltage, and information recorded on the recording layer by causing the Joule heat to thermally act on the recording layer The nonvolatile memory device according to claim 1, wherein the non-volatile memory device is erased.   3. The erasing unit includes a heating element that generates Joule heat by applying a voltage, and a heat transfer body that transmits the generated Joule heat to the recording layer. The non-volatile memory device described in 1.   The nonvolatile memory device according to claim 3, wherein the heat transfer body is provided between the first wiring and the second wiring.   The non-volatile memory device according to claim 3, wherein the heat transfer body is provided between the plurality of recording layers.   2. The erasing unit is a control circuit that collectively applies a voltage to a plurality of regions where the plurality of first wirings and the plurality of second wirings cross each other. Nonvolatile storage device.   The non-volatile memory device according to claim 1, wherein the erasing unit operates in response to an external signal.

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