JP2010220413A - Equalization control circuit of capacitor module, and equalization control device with equalization control circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an equalization control circuit, along with an equalization control device with the same, in which a voltage of a capacitor module does not change greatly due to reduced power consumption at normal time of the equalization control circuit, for stableness in long term preservation. <P>SOLUTION: The equalization control circuit equalizes a module voltage of an energy storage device in which a plurality of capacitor modules containing at least a plurality of capacitor cells are connected. The equalization control circuit includes a DC/DC converter. When equalizing a module voltage of a plurality of capacitor modules, an internal loss of the DC/DC converter is utilized to step down the module voltage. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a capacitor module including a plurality of power storage devices each including a plurality of capacitor cells connected in series with each other, and when the plurality of capacitor modules are connected, equalization is performed for equalizing the voltages of the capacitor modules. The present invention relates to a control circuit and an equalization control device including the equalization control circuit.

  Conventionally, it has been used as a large-capacity power storage device by connecting a plurality of capacitor modules including, for example, an electric double layer capacitor or a lithium ion capacitor.

  When a plurality of capacitor modules are connected in this way, it is necessary to balance the voltage of each capacitor module. If there is a variation between the voltages of each capacitor module, the voltage concentrates on the specific capacitor module, causing a large load on the specific capacitor module, resulting in damage to the capacitor module or shortening the life of the power storage device. Problem arises.

Therefore, for example, as shown in FIG. 7, for each block B _{11 to} B ₁₅ (capacitor module) obtained by dividing a plurality of unit cells C _{110 to} C ₁₅₉ (capacitor cells), block discharge is generated at both ends thereof. By connecting the resistor Rdb and controlling on / off of the block discharge switch Sdb connected in series with the block discharge resistor Rdb, the unit cells C ₁₁₀ to C are discharged after being discharged for each of the blocks B _{11 to} B _15. by connecting to the cell discharge resistor Rdc every _159, state of charge adjustment apparatus for adjusting the state of charge so that the target voltage determined based on the minimum of the voltage across one of the unit cells C ₁₁₀ -C ₁₅₉ is disclosed (Patent Document 1).

JP 2007-28259 A

  However, when the cell discharge resistor Rdc for lowering the voltage of the unit cell and the block discharge resistor Rdb for lowering the voltage for each block are provided in this way, each discharge resistor and the discharge resistor are turned on. Since a switch for controlling / off is required, a space for configuring a circuit is increased.

Further, as shown in FIG. 7, it has a high voltage system CPU for controlling a selection switch group, a cut-off switch, and the like, and a low voltage system CPU for performing voltage equalization control for each of the blocks B _{11 to} B _15. Therefore, in the case of such a configuration, power for operating the high-voltage CPU and the low-voltage CPU is consumed, and the current consumption of the entire charging state adjusting device (equalization control circuit) increases.

  Generally, in the equalization control circuit, the circuit current necessary for operating the equalization control circuit is taken out from the capacitor cell. Therefore, the larger the current consumption in the equalization control circuit, the more the capacitor cell energy is consumed. It will be. For this reason, even if the power storage device is not in use, the energy of the capacitor cell is consumed successively, making long-term power storage difficult.

  In particular, when a capacitor cell is configured using a lithium ion capacitor, if the voltage value of the lithium ion capacitor is equal to or lower than a predetermined voltage value (overdischarge state), it cannot be used even after recharging. .

  In view of such a situation, the present invention reduces the current consumption in the equalization control circuit at normal times, is stable even during long-term storage, and the equalization control circuit in which the voltage of the capacitor module does not greatly change An object of the present invention is to provide an equalization control device including an equalization control circuit.

  Furthermore, the present invention includes an equalization control circuit that can reduce the space for configuring the circuit and reduce the manufacturing cost by simplifying the configuration of the equalization control circuit, and the equalization control circuit. An object is to provide an equalization control device.

The present invention has been invented in order to achieve the above-described problems and objects in the prior art, and the equalization control circuit of the present invention includes:
An equalization control circuit for equalizing a module voltage of a power storage device formed by connecting a plurality of capacitor modules including at least a plurality of capacitor cells,
The equalization control circuit comprises a DC / DC converter;
When equalizing the module voltage of the plurality of capacitor modules, the module voltage is stepped down by using an internal loss of the DC / DC converter.

Further, the equalization control circuit of the present invention, in the capacitor module, when stepping down the module voltage,
Among the plurality of capacitor cells in the capacitor module, the module voltage is reduced by charging the capacitor cell whose cell voltage is lower than the cell voltage of other capacitor cells through the DC / DC converter. It is characterized by making it.

The equalization control circuit of the present invention is characterized in that two or more capacitor cells among the plurality of capacitor cells are charged simultaneously.
In the equalization control circuit of the present invention, the equalization control circuit includes an arithmetic processing unit.
In the module voltage equalization control, the module voltage is stepped down to a predetermined voltage value by controlling a DC / DC converter based on a signal from the arithmetic processing unit.

The equalization control circuit according to the present invention is characterized in that the equalization control circuit is incorporated in each capacitor module.
The equalization control circuit according to the present invention is characterized in that the equalization control circuit incorporated for each of the plurality of capacitor modules includes a communication device for transmitting and receiving signals between the capacitor modules. .

In the equalization control circuit of the present invention, the equalization control circuit includes a communication device power supply for driving the communication device,
When performing communication between capacitor modules, the communication device power is turned on and the communication device is driven,
When the communication between the capacitor modules is not performed, the communication device is configured to be controlled to be turned off to stop the communication device.

The equalization control circuit of the present invention is configured such that a specific capacitor module among the plurality of capacitor modules is set as a master module, and the master module recognizes a capacitor module other than the master module as a slave module. And
The module voltages of the plurality of capacitor modules are equalized by controlling the module voltage of the slave module based on the signal from the master module.

In the master module, the equalization control circuit of the present invention compares the module voltage of the master module with the module voltage of the slave module,
When the module voltage of the slave module is higher than the module voltage of the master module, the slave module is configured to temporarily operate as a master module.

The equalization control circuit according to the present invention is configured to equalize cell voltages of a plurality of capacitor cells for each capacitor module.
In the equalization control circuit of the present invention, the equalization control circuit includes a power supply for an arithmetic processing device for operating the arithmetic processing device,
The power supply for the arithmetic processing unit is configured to be able to select a power output for normal operation of the arithmetic processing device and a power output for sleep operation whose output is smaller than the power output for normal operation. To do.

  In the equalization control circuit of the present invention, the power supply for the arithmetic processing unit is divided into two types, that is, an operation power supply for normal operation power output and a sleep operation power supply for sleep operation power output. It is characterized by comprising a power source.

  The equalization control circuit of the present invention stops the power output for normal operation based on a signal from the arithmetic processing unit when at least one of the plurality of capacitor cells becomes a predetermined cell voltage or less. The power output for sleep operation is activated.

The equalization control circuit of the present invention transmits a sleep signal to the power supply for the arithmetic processing unit when the arithmetic processing unit shifts from the normal operation to the sleep operation, and sleeps from the power output for the normal operation. While switching to the power output for operation,
When the arithmetic processing unit shifts from the sleep operation to the normal operation, a wake-up signal is transmitted to the arithmetic processing device power supply to switch from the power supply output for the sleep operation to the power output for the normal operation. And

  Further, the equalization control circuit of the present invention transmits a sleep signal to the arithmetic processing unit of the slave module when the arithmetic processing unit of the master module shifts from the normal operation to the sleep operation, so that the arithmetic processing unit of the slave module The power supply for operation is switched from the power supply output for normal operation to the power supply output for sleep operation.

  Further, the equalization control circuit of the present invention transmits a wake-up signal to the arithmetic processing unit of the slave module when the arithmetic processing unit of the master module shifts from the sleep operation to the normal operation, so that the arithmetic processing of the slave module The apparatus power supply is switched from a power supply output for sleep operation to a power supply output for normal operation.

  The equalization control circuit according to the present invention is characterized in that, when an abnormality occurs in the slave module, the slave module notifies the master module of the abnormality occurrence via the communication device.

  The equalization control circuit of the present invention is characterized in that the plurality of capacitor modules are connected in series connection, parallel connection, or a combination of series connection and parallel connection.

In the equalization control circuit of the present invention, the capacitor cell is a lithium ion capacitor.
In addition, a capacitor module according to the present invention includes any of the equalization control circuits described above.

  The power storage device of the present invention is characterized in that a plurality of the capacitor modules described above are connected.

According to the present invention, it is possible to reduce current consumption during normalization in the equalization control circuit, and to stably change the voltage of the capacitor module even during long-term storage.
In addition, the configuration of the equalization control circuit can be simplified, and the module voltage and cell voltage can be equalized in the same circuit, thereby reducing the space for configuring the circuit and reducing the manufacturing cost. Can be made.

  Furthermore, the arithmetic processing unit for equalization control is configured to operate by switching between normal operation and sleep operation, and uses a unique power output during normal operation and sleep operation, respectively. The power consumption of the arithmetic processing unit can be reduced, and the current consumption as the equalization control circuit can be reduced, so that the deterioration of the capacitor module with time can be suppressed.

FIG. 1 is a circuit configuration diagram of a capacitor module using the equalization control circuit of the present invention. FIG. 2 is a schematic circuit configuration diagram of a power storage device in which a plurality of capacitor modules of FIG. 1 are connected. FIG. 3 is a circuit configuration diagram showing an example of a DC / DC converter in the equalization control circuit of the present invention. FIG. 4 is a data configuration diagram showing a data format used in communication between the capacitor modules. FIG. 5 is a circuit configuration diagram of a capacitor module using an equalization control circuit according to another embodiment of the present invention. FIG. 6 is a schematic circuit configuration diagram of a power storage device in which a plurality of capacitor modules in FIG. 5 are connected. FIG. 7 is a circuit configuration diagram of a conventional equalization control circuit.

Hereinafter, embodiments (examples) of the present invention will be described in more detail based on the drawings. In addition, although embodiment of a present Example is described below, it is not restricted to this embodiment.
FIG. 1 is a circuit configuration diagram of a capacitor module using the equalization control circuit of the present invention, FIG. 2 is a schematic circuit configuration diagram of a power storage device in which a plurality of capacitor modules of FIG. 1 are connected, and FIG. 4 is a circuit configuration diagram showing an example of a DC / DC converter in the control circuit, and FIG. 4 is a data configuration diagram showing a data format used in communication between the capacitor modules.

  The equalization control circuit 12 of the capacitor module 10 according to the present embodiment includes an arithmetic processing unit 20, an operation power source 22 for the arithmetic processing unit, a DC / DC converter 30, a decoder 40, and a bidirectional communication insulating circuit 50.

  The arithmetic processing unit 20 includes a CPU (Central Processing Unit), a RAM (Random Access Memory), a ROM (Read Only Memory) in which an arithmetic processing program is stored, and the like. It is configured.

  The arithmetic processing unit 20 is provided with a function selection dip switch 26. This function selection DIP switch 26 is used to switch the role of the arithmetic processing unit 20 of each capacitor module 10 when a plurality of capacitor modules 10 are connected.

  Here, as will be described later, the role of the arithmetic processing device 20 indicates the master-slave relationship of each arithmetic processing device 20, and when a specific arithmetic processing device is set as a master (main), other arithmetic processing devices. Is a slave (subordinate), and the slave arithmetic processing unit is configured to operate based on a command signal from the master arithmetic processing unit.

On the other hand, the electricity storage device 14 is configured by connecting _twelve capacitor cells C _{1 to} C ₁₂ made of lithium ion capacitors in series.
The capacitor cells C _{1 to} C ₁₂ are connected via relays R _{1 to} R ₁₂ so as to be connected in parallel when viewed from the arithmetic processing unit 20 and the DC / DC converter 30. The relays R _{1 to} R ₁₂ can be switched on and off based on a signal from the arithmetic processing unit 20. The arithmetic processing unit 20 is connected via operational amplifiers A ₁ and A ₂ and an A / D converter (not shown). The A / D converter is more preferably built in the arithmetic processing unit 20.

Reference numerals 18a and 18b denote external terminals (charge / discharge terminals), and when connecting to other capacitor modules, the external terminals 18a and 18b are electrically connected to each other.
In the present embodiment, a signal from the processing unit 20 and coded by decoder 40, by transmitting the data to the relay R ₁ to R _12, performs control of ON and OFF of the relay R ₁ to R ₁₂ ing.

  Although it does not specifically limit as a relay used as a present Example, It is preferable to use a photoMOS relay. By using the photo MOS relay, the relay can be turned on and off with a small amount of electric power, and power saving as the entire equalization control circuit 12 can be achieved.

Further, the DC / DC converter 30 and the operation power source 22 are connected so as to supply power to the capacitor cells C _{1 to} C ₁₂ . The operation and stop of the DC / DC converter 30 are controlled by controlling ON / OFF of the relay R _DC by a signal from the arithmetic processing unit 20.

  In this embodiment, the DC / DC converter 30 is, for example, a constant current type insulation type such as a flyback converter shown in FIG. 3A or a forward coupled converter shown in FIG. A converter is used.

  Generally, when such a converter is used to increase / decrease the input voltage, a loss occurs inside the converter. Examples of the loss inside the converter include the following.

(1) Iron loss, copper loss, hysteresis loss, eddy current loss, etc. in the transformer constituting the insulating converter (2) Copper loss, hysteresis loss, etc. of the smoothing choke coil on the secondary side of the converter transformer (3) ) Copper loss, hysteresis loss, etc. of the noise prevention choke coil on the power input side of the converter (4) Voltage drop due to the forward bias Vf of the rectifying diode on the secondary side of the converter transformer (5) Smoothing electrolytic capacitor on the secondary side Due to the loss inside the converter, the conversion efficiency of the converter expressed by Equation 1 is generally 80 to 90%. That is, about 10 to 20% of the input current to the DC / DC converter 30 is consumed in the DC / DC converter 30 as a loss.

本発明の均等化制御回路においては、このＤＣ／ＤＣコンバーター３０の内部損失を利用して、キャパシタモジュール１０の電荷を消費させ、キャパシタモジュール間の電圧の均等化制御を行っている。

In the equalization control circuit of the present invention, the internal loss of the DC / DC converter 30 is used to consume the charge of the capacitor module 10 and to control the equalization of the voltage between the capacitor modules.

  A plurality of capacitor modules 10 configured as described above are electrically connected, and as a power storage device, a battery such as an automobile, a crane, an automatic guided vehicle (AGV), a wind power generator, an elevator, or a UPS (Uninterruptible Power). Supply: Uninterruptible power supply).

The operation flow of the equalization control circuit 12 when a plurality of capacitor modules 10 using the equalization control circuit 12 of the present embodiment are connected will be described below.
First, a signal is sent from the arithmetic processing unit 20 to the decoder 40 so that the relays R ₁ and R ₂ are turned on in order to charge and boost the capacitor cell C ₁ to a preset equalization voltage of the capacitor cell. .

In order to charge the capacitor cell C ₁ , a PWM (Pulse Width Modulation) signal is transmitted from the arithmetic processing unit 20 to the DC / DC converter 30, and the capacitor cell C ₁ is supplied to the capacitor cell C ₁ by a change in the duty ratio of the pulse wave. Control charging.

After the elapse of a predetermined time, confirmation of the charging voltage of the capacitor cells C _1, and, in order to monitor the voltage balance of all the capacitor cells C ₁ -C _12, measuring cell voltages of all the capacitor cells C ₁ -C _12.

In the measurement of the cell voltage, for example, for the capacitor cell C ₁ , the arithmetic processing unit 20 turns on the relays R ₁ and R ₂ and turns off the other relays R _{3 to} R ₁₂ .
By doing so, both ends _C1- voltage V _{C1 +} and V of the capacitor cell C1 is read by the operational amplifier A ₁ and A ₂ and A / D via the converter processor 20. The arithmetic processing unit 20 measures the voltage value of the capacitor cell C1 by calculating the difference between V _{C1 +} and V _C1− .

Note that, when reading of V _{C1 +} and V _C1− is completed by the arithmetic processing unit 20, the relays R ₁ and R ₂ are turned off. Thus, the current consumption of the capacitor cell C ₁ can be reduced by controlling.

At this time, the relay R ₁ is connected in series with the operational amplifier A _1, and the relay R ₂ is connected in series with the operational amplifier A ₂ .
Thus, among the connection points P ₁ to P ₁₃ of a plurality of capacitor cells C ₁ -C ₁₂ which are connected in series, the odd-numbered connection points _{P 1, P 3, ... P} 13 includes an operational amplifier A ₁ and the electrical The even-numbered connection points P ₂ , P ₄ ,... P ₁₃ are electrically connected to the operational amplifier A ₂ . By connecting in this way, the voltage of each capacitor cell can be obtained by calculating the difference between the voltage values at the connection points P _{1 to} P ₁₃ .

Next, measurement is repeated for the voltages of the capacitor cells C _{2 to} C _{12 in} the same manner as described above. The time required for voltage measurement of the capacitor cells C _{1 to} C ₁₂ depends on the operation speeds of the arithmetic processing unit 20, the decoder 40, and the relays R _{1 to} R ₁₂ , but the capacitor cells C _{1 to} C ₁₂ The time required to measure the voltage all over is preferably 30 ms or less, more preferably 1 ms to 20 ms, and further 1 to 10 ms. By setting the time required for voltage measurement in this way, current consumption can be reduced and power can be saved, and a measurement error due to the measurement time being too short does not occur.

After the cell voltages of the capacitor cells C _{1 to} C ₁₂ are measured in this way, the highest voltage value of the cell voltage is compared with the lowest voltage value of the cell voltage, and they are within a predetermined specified value. In this case, since the capacitor cell C ₁ is not sufficiently charged, the above operation is performed again.

On the other hand, when the capacitor cell C ₁ becomes equal to or greater than the equalization start voltage set in advance, equalization control of the cell voltage is performed.
First, in order to charge the capacitor cell having the lowest cell voltage, the arithmetic processing unit 20 controls the relays R _{1 to} R ₁₂ so that the DC / DC converter 30 performs charging.

Then, a PWM signal is transmitted from the arithmetic processing unit 20 to the DC / DC converter 30, and charging is started.
After charging for a certain time, the output of the PWM signal from the arithmetic processing unit 20 to the DC / DC converter 30 is stopped, and the charging to the capacitor cell having the lowest cell voltage is completed.

Then, a signal for turning off all the relays R _{1 to} R ₁₂ is transmitted from the arithmetic processing unit 20 to the decoder 40 so that the energy of the capacitor cells C _{1 to} C ₁₂ is not consumed.
Then, a voltage of the same manner as described above capacitor cell C ₁ -C ₁₂ measures, or by comparing the lowest voltage value of the highest voltage value and the cell voltage of the cell voltage, falls within the predetermined value determined in advance It is judged by the arithmetic processing unit 20 whether or not.

  At this time, if the highest voltage value of the cell voltage and the lowest voltage value of the cell voltage are not within a predetermined value, the same as the above for the capacitor cell having the lowest cell voltage. After charging again, the voltage balance of all capacitor cells is monitored.

  As described above, in the equalization control circuit 12 of the present embodiment, by boosting one capacitor cell in the capacitor module 10 to the equalization start voltage, the voltage balance between the capacitor cells is destroyed and equalization is performed again. Thus, equalization control of the module cell voltage is performed.

When the voltage balance is lost, only a specific capacitor cell is charged and the other capacitor cells are discharged.
At this time, regarding the discharged capacitor cell, the sum of the charge for charging the specific capacitor cell and the charge consumed by the loss inside the DC / DC converter 30 is consumed.

  For this reason, the electric charge consumed by the loss in the DC / DC converter 30 is consumed in the entire capacitor module 10, and the voltage across the entire capacitor module 10 can be stepped down by this amount. Equalization control can be performed as described below.

Hereinafter, the flow of equalization control between the capacitor modules will be described.
In this embodiment, the capacitor module 10 is set as a master (hereinafter also referred to as master module 10), and the capacitor modules 11a and 11b are set as slaves (hereinafter also referred to as slave modules 11a and 11b).

First, the voltage values of the capacitor cells C _{1 to} C ₁₂ , C _{13 to} C ₂₄ (not shown), and C _{25 to} C ₃₆ (not shown) of the capacitor modules 10, 11a, and 11b are measured as described above. and, also, the capacitor module 10, 11a, the equalization control of the capacitor cells _{C 1 ~C 12, C 13 ~C} 24, C 25 ~C 36 per 11b is performed.

At this time, for each of the capacitor modules 10, 11a, and 11b, when the highest voltage value of the cell voltage and the lowest voltage value of the cell voltage are within predetermined predetermined values, the capacitor module 10, For each of 11a and 11b, the voltage values of the capacitor cells C _{1 to} C ₁₂ , C _{13 to} C ₂₄ , and C _{25 to} C ₃₆ are added by the arithmetic processing unit 20 to calculate the module voltage of the entire capacitor module.

  Next, the data in the format shown in FIG. 4A is transmitted from the bidirectional communication isolation circuit 50 of the master module 10 to the bidirectional communication isolation circuit 50 of the slave modules 11a and 11b at regular time intervals. Requests that the module voltages 11a and 11b be transmitted to the master slave 10.

  In the present embodiment, the command command from the master module 10 to the slave modules 11a and 11b has a format as shown in FIG. 4A, but is not particularly limited. Command signals to the slave modules 11a and 11b can be transmitted.

  In the data format shown in FIG. 4A, first, an “STX” code indicating the start of data is sent. Next, the number of the module for which the instruction is to be executed is sent in ASCII code. For example, when it is desired to cause the slave module 11a to execute an instruction, “02” which is the module number of the slave module 11a is transmitted as “30h, 32h” as the ASCII code.

Next, a “CR” code is sent to separate the module number from the command. The “CR” code is a code meaning a carriage return (line feed).
The command command is then sent in ASCII code. In this embodiment, the command indicating “request for module voltage” is set as “01”, and “30h, 31h” is sent as the ASCII code.

Finally, an “ETX” code indicating the end of data is sent.
In this way, by clearly defining the start and end of the command with the “STX” code and the “ETX” code, even if a communication error occurs during the transmission of the command command, the error can be appropriately detected. It can be detected and the wrong operation is not performed.

When the slave modules 11 a and 11 b receive such a command from the master module 10, the slave modules 11 a and 11 b transmit their module voltages to the master module 10.
Similar to the data format of instruction commands from the master module 10 to the slave modules 11a and 11b, the data format of information data from the slave modules 11a and 11b to the master module 10 is not particularly limited.

  When the master module 10 receives the module voltages of all the slave modules 11a and 11b connected to the master module 10, the arithmetic processing unit 20 of the master module 10 obtains the highest voltage value and the module voltage. Calculate the difference between the lowest voltage values.

When this inter-module voltage difference is larger than a predetermined value set in advance, equalization control between modules is performed.
First, the master module 10 transmits data in the format shown in FIG. 4B to the capacitor module having the highest module voltage, and requests to lower the module voltage.

  The data format of FIG. 4B is basically the same as the data format of the instruction command shown in FIG. 4A, but the “target voltage value of the module voltage” is sent as a binary to the instruction command portion. .

By using binary as the “module voltage target voltage value” data without using the ASCII code, a detailed target voltage value can be specified with a short data length.
The capacitor module that has received the data of the “target voltage value of the module voltage” consumes the electric charge of the entire capacitor module by the DC / DC converter 30 by performing equalization control of each capacitor cell as described above. The module voltage is controlled so that the module voltage becomes the target voltage value.

  While the module voltage is stepped down by the equalization control, the master module 10 transmits the command command shown in FIG. 4A to the capacitor module and monitors the module voltage of the capacitor module. Yes.

  On the other hand, when the capacitor module on which equalization control is performed reaches the target voltage value by stepping down the module voltage, the module voltage is transferred from the capacitor module to the master module 10 according to the data format shown in FIG. Notify the completion of step-down. When the module voltage step-down is completed, FFFFh is set to be transmitted as “module voltage target voltage value” data.

  When the “capacitor module with the highest module voltage” is one of the slave modules 11a and 11b, the above-described communication with the master module 10 is performed via the bidirectional communication isolation circuit 50. However, when the “capacitor module with the highest module voltage” is the master module 10, communication via the bidirectional communication isolation circuit 50 is not performed, and the step-down control of the module voltage as described above is performed in the master module 10. Will be done.

  In addition, by configuring the bidirectional communication isolation circuit 50 so that it can be switched ON / OFF, the bidirectional communication of a slave module in a non-communication state, that is, a slave module other than the “capacitor module having the highest module voltage”. It is also possible to reduce the power consumption of the slave module in the non-communication state by turning off the insulation circuit 50.

  When the communication frequency between the master module 10 and the slave modules 11a and 11b increases, the bidirectional communication insulating circuit 50 requires power consumption equivalent to that of the DC / DC converter 30 due to the circuit configuration.

  For this reason, in order to reduce the communication frequency, the slave modules 11a and 11b may be configured to temporarily function as a master module in accordance with a command from the master module 10.

  Specifically, for example, when the module voltage of the slave module 11a is sufficiently higher than the voltages of other modules, the master module 10 temporarily stores the slave module 11a in FIG. The slave module 11a temporarily serves as a master module.

  Thus, by causing the slave module 11a to temporarily function as a master module, the frequency of communication with the master module 10 can be reduced, and the DC / DC converter 30 and the communication insulation circuit 50 can be operated. The target voltage to be equalized can be reached earlier.

  Note that the slave module 11a that has reached the target voltage notifies the master module 10 that the function as the master module is terminated by transmitting a command shown in FIG.

  Note that the communication format between modules in the present embodiment is merely an example, and can be appropriately changed depending on the type of the arithmetic processing unit 20 used in the circuit or a communication module (not shown).

  Also, the communication method is not particularly limited. For example, RS-422, RS-423, RS-485, and the like can be used. Especially when the number of connected modules is large, the RS It is preferable to use -485.

Further, the reliability of communication data can be improved by providing a circuit for detecting data collision (collision) in the communication line.
Further, in any of the slave modules 11a and 11b, when a module abnormality is detected, the slave module can be configured to notify the master module of the abnormality.

  In the present embodiment, the two slave modules 11a and 11b are connected to the master module 10. However, the number of slave modules is not particularly limited. The number can be changed as appropriate.

  In this embodiment, the electrical connection between the capacitor modules is not particularly limited, but the capacitor modules may be connected in series or may be connected in parallel. A plurality of capacitor modules connected in parallel may be connected in series. As described above, the connection method between the capacitor modules can be appropriately changed depending on the use as the power storage device.

  As described above, the capacitor module including the equalization control circuit of the present invention is used for automobiles, cranes, automated guided vehicles (AGVs), wind power generators, batteries for elevators, UPSs, and the like. Therefore, equalization control is performed not only in the unused state but also in the used state.

  FIG. 5 is a circuit configuration diagram of a capacitor module using an equalization control circuit according to another embodiment of the present invention, and FIG. 6 is a schematic circuit configuration diagram of a power storage device in which a plurality of capacitor modules of FIG. 5 are connected.

  The capacitor module 10 using the equalization control circuit of this embodiment has basically the same configuration as the capacitor module 10 using the equalization control circuit shown in FIGS. Are denoted by the same reference numerals, and detailed description thereof is omitted.

  As shown in FIG. 5, the equalization control circuit 12 of this embodiment is provided with a power supply 24 for sleep operation in addition to the power supply 22 for normal operation. The power supply 24 for sleep operation outputs a power output for sleep operation that is smaller than the power output for normal operation.

Normal operating power supply 22 and the sleep mode power supply 24 is connected to the processing unit 20 via the respective relay R _a and R _b, based on a signal from the processing unit 20, a relay R _a and R _b Selective control. That is, when the relay R _a is ON, the relay R _b is turned OFF, when the relay R _a is OFF is controlled to relay R _b are turned ON.

In the present embodiment, signals that control the relays R _a and R _b are called a wake-up signal and a sleep signal. If the processing unit 20 shifts to the sleep mode from the normal operation, the processing unit 20 transmits a sleep signal, turns OFF the relay R _a as well as the ON relay R _b. As a result, the power supply 24 for sleep operation is selected as the power supply for operating the arithmetic processing unit 20.

On the other hand, when the arithmetic processing unit 20 shifts from the sleep operation to the normal operation, the arithmetic processing unit 20 transmits a wake-up signal to turn on the relay _Ra and turn off the relay _Rb . As a result, the normal operation power supply 22 is selected as the power supply for operating the arithmetic processing unit 20.

The normal operation is an operation in which the arithmetic processing unit 20 measures the voltage of the capacitor cells C _{1 to} C ₁₂ or performs equalization control of the cell voltage of the capacitor cell via the DC / DC converter 30. means. On the other hand, the sleep operation means a state other than the normal operation, and is a state in which the arithmetic processing unit 20 is operating in a standby state.

  The power output for normal operation and the power output for sleep operation vary depending on the arithmetic processing unit 20, but in this embodiment, 20 mA is used as the power output for normal operation and 0.1 mA is used as the power output for sleep operation. Is output.

  Note that the power output for normal operation and the power output for sleep operation may be selectively output by switching the output of one power source. However, as in the present embodiment, the power output for normal operation 22 and the sleep operation power output By providing each of the operation power supplies 24 individually, current consumption in the power supply is reduced, and power saving can be achieved.

  In this embodiment, as shown in FIG. 6, the wakeup signal and sleep signal from the master module 10 can be transmitted to the slave modules 11a and 11b.

  In the power storage device configured as described above, when charging / discharging is not performed for a certain time in the master module 10, a sleep signal is transmitted to the slave modules 11a and 11b, and the master module 10 itself shifts to a sleep operation.

The arithmetic processing unit 20 of the slave modules 11a and 11b that has received the sleep signal from the master module 10 transmits the sleep signal to the relays _Ra and _Rb of the slave modules 11a and 11b itself, and shifts to the sleep operation.

  In addition, when a certain time has elapsed after the master module 10 shifts to the sleep operation, the arithmetic processing unit 20 shifts from the sleep operation to the normal operation and measures the total capacitor cell voltage of the master module 10 to charge the master module 10. It is determined whether or not the discharge is performed.

  When charging / discharging of the master module 10 is not performed, the master module 10 shifts to the sleep operation again, and determines whether charging / discharging is performed after a predetermined time.

  On the other hand, when charging / discharging of the master module 10 is performed, the master module 10 transmits a wake-up signal to the slave modules 11a and 11b, and shifts the slave modules 11a and 11b to normal operation.

  In this way, by controlling the operation state of the plurality of capacitor modules synchronously, the operation when the capacitor modules are not charged / discharged is not performed, thereby reducing the power consumption of the capacitor modules and extending the operation time. Can save power in the entire power storage device.

  Further, the wake-up signal and the sleep signal transmitted from the master module 10 to the slave modules 11a and 11b are not particularly limited, but can be transmitted as a pulse signal having a predetermined voltage. Although the pulse width of the pulse signal is not particularly limited, it is preferable to set it to the shortest time width that can be detected by the slave modules 11a and 11b in consideration of power saving.

  In addition, the transmission / reception circuit for the wakeup signal and the sleep signal is not particularly limited. However, by using a photocoupler, a photo MOSIC, or the like, reliability in transmission / reception is improved and power saving is achieved. Can do.

  The preferred embodiment of the present invention has been described above. However, the present invention is not limited to this. For example, in the above embodiment, the lithium ion capacitor is used as the capacitor. Various modifications can be made without departing from the object of the present invention, for example, a capacitor cell can be configured using other capacitors.

10 Master module (capacitor module)
11a, 11b Slave module (capacitor module)
12 Equalization Control Circuit 14 Power Storage Device 20 Arithmetic Processing Unit 22 Power Supply for Operation 24 Power Supply for Sleep Operation 26 Function Selection Dip Switch 30 Converter 40 Decoder 50 Bidirectional Communication Isolation Circuits A ₁ and A ₂ Operational Amplifiers C _{1 to} C ₃₆ Capacitors cell P ₁ to P ₁₃ connection points R ₁ to R ₁₂ relay R _a, R _b relay R _DC relay B ₁₁ .about.B ₁₅ block C ₁₁₀ -C ₁₅₉ unit cell Rdb block discharging resistor Rdc cell discharge resistor Sdb block discharging switch

Claims (21)

An equalization control circuit for equalizing a module voltage of a power storage device formed by connecting a plurality of capacitor modules including at least a plurality of capacitor cells,
The equalization control circuit includes a DC / DC converter,
A module voltage equalization control circuit configured to step down the module voltage using the internal loss of the DC / DC converter when equalizing the module voltages of the plurality of capacitor modules. . In the capacitor module, when reducing the module voltage,
Among the plurality of capacitor cells in the capacitor module, the module voltage is reduced by charging the capacitor cell whose cell voltage is lower than the cell voltage of other capacitor cells through the DC / DC converter. The equalization control circuit according to claim 1, wherein:   The equalization control circuit according to claim 2, wherein two or more capacitor cells among the plurality of capacitor cells are charged simultaneously. The equalization control circuit includes an arithmetic processing unit;
The module voltage is stepped down to a predetermined voltage value by controlling a DC / DC converter based on a signal from the arithmetic processing unit during equalization control of the module voltage. 4. The equalization control circuit according to any one of 3 above.   The equalization control circuit according to claim 1, wherein the equalization control circuit is incorporated in each capacitor module.   6. The equalization control circuit according to claim 5, wherein the equalization control circuit incorporated in each of the plurality of capacitor modules includes a communication device for transmitting and receiving signals between the capacitor modules. The equalization control circuit includes a communication device power source for driving the communication device,
When performing communication between capacitor modules, the communication device power is turned on and the communication device is driven,
7. The equalization control according to claim 6, wherein when communication between the capacitor modules is not performed, control is performed so that the communication device is stopped by turning off the power supply for the communication device. circuit. Among the plurality of capacitor modules, a specific capacitor module is set as a master module, and a capacitor module other than the master module is configured to be recognized as a slave module by the master module,
8. The equalization control circuit according to claim 6, wherein module voltages of a plurality of capacitor modules are equalized by controlling a module voltage of a slave module based on a signal from the master module. . In the master module, the module voltage of the master module and the module voltage of the slave module are compared,
9. The equalization control according to claim 8, wherein when the module voltage of the slave module is higher than the module voltage of the master module, the slave module is temporarily operated as a master module. circuit.   The equalization control circuit according to claim 1, wherein the capacitor modules are configured to equalize cell voltages of a plurality of capacitor cells for each capacitor module. The equalization control circuit includes an arithmetic processing device power source for operating the arithmetic processing device,
The power supply for the arithmetic processing unit is configured to be able to select a power output for normal operation of the arithmetic processing device and a power output for sleep operation whose output is smaller than the power output for normal operation. The equalization control circuit according to any one of claims 4 to 10.   The power supply for the arithmetic processing unit is composed of two types of power supplies: a power supply for normal operation power output and a power supply for sleep operation for power output for sleep operation. The equalization control circuit according to claim 11.   When at least one of the plurality of capacitor cells is equal to or lower than a predetermined cell voltage, the power output for normal operation is stopped and the power output for sleep operation is activated based on a signal from the arithmetic processing unit. The equalization control circuit according to claim 11 or 12. When the arithmetic processing unit shifts from the normal operation to the sleep operation, a sleep signal is transmitted to the arithmetic processing device power supply, and the normal operation power output is switched to the sleep operation power output.
When the arithmetic processing unit shifts from the sleep operation to the normal operation, a wake-up signal is transmitted to the arithmetic processing device power supply to switch from the power supply output for the sleep operation to the power output for the normal operation. The equalization control circuit according to claim 11.   When the arithmetic processing unit of the master module shifts from the normal operation to the sleep operation, a sleep signal is transmitted to the arithmetic processing unit of the slave module, and the power for the arithmetic processing unit of the slave module sleeps from the power output for normal operation. The equalization control circuit according to claim 14, wherein the equalization control circuit is switched to a power output for operation.   When the arithmetic processing unit of the master module shifts from the sleep operation to the normal operation, a wake-up signal is transmitted to the arithmetic processing unit of the slave module, and the power for the arithmetic processing unit of the slave module is switched from the power output for the sleep operation. The equalization control circuit according to claim 14, wherein the equalization control circuit is switched to a power supply output for normal operation.   The equalization control according to any one of claims 8 to 16, wherein when an abnormality occurs in the slave module, an abnormality occurrence notification is sent from the slave module to the master module via a communication device. circuit.   The equalization control circuit according to any one of claims 1 to 17, wherein the plurality of capacitor modules are connected in series connection, parallel connection, or a combination of series connection and parallel connection.   The equalization control circuit according to claim 1, wherein the capacitor cell is a lithium ion capacitor.   A capacitor module comprising the equalization control circuit according to claim 1.   A power storage device in which a plurality of capacitor modules according to claim 20 are connected.

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