JP2010212500A - Method of manufacturing semiconductor device and the semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device containing at least one partially-depleted SOI-MOSFET capable of suppressing short channel effects and also controlling a V<SB>th</SB>value in one chip, and to provide a method of manufacturing the semiconductor device. <P>SOLUTION: The method of manufacturing the semiconductor device including a source and a drain containing first conductivity type impurities 1 in a semiconductor layer 5 provided on an insulating layer 4 includes: a step of leading second conductivity type impurities 2 to a deep area of the semiconductor layer 5 to form a punch-through stopper region 7 and concurrently leading the impurities to a shallow area of the semiconductor layer 5 to form a first threshold value region 8; and a step of leading the first conductivity type impurities 1 to the shallow area of the semiconductor layer 5 where the second conductivity type impurities 2 are led, to form a second threshold value region 9 on at least part of the first threshold value region 8. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a method for manufacturing a semiconductor device and a semiconductor device capable of suppressing a short channel effect and improving controllability of a threshold voltage.

  A MOSFET (that is, SOI-MOSFET) formed on a semiconductor substrate (hereinafter also referred to as an SOI substrate) including an SOI (Silicon On Insulator) layer has a parasitic capacitance as compared with a MOSFET formed on a conventional bulk semiconductor substrate. It is a small device that is expected to operate at high speed and low voltage. There are roughly two types of SOI-MOSFETs. One type is a “fully depleted type” where the depletion layer reaches the BOX layer included in the SOI substrate during operation, and the other type is a “partial depletion type” where the depletion layer does not reach this BOX layer during operation and a neutral region remains. Is.

  Although fully depleted SOI-MOSFETs show the features of SOI-MOSFETs such as high-speed operation and low voltage, the thickness of the SOI layer is several tens of nanometers or less. high. On the other hand, in the partially depleted SOI-MOSFET, the thickness of the SOI layer is at the level of 100 nm, and the difficulty related to its manufacture is not so high as compared with the fully depleted type. In the partially depleted type, it is possible to obtain the same characteristics as the fully depleted type by setting the substrate potential (body potential) to an appropriate value. The structure of this partially depleted SOI-MOSFET is described in Patent Document 1, for example.

JP 2004-128254 A

In this way, processes that are indispensable for mass production of partially-depleted SOI-MOSFETs with relatively low manufacturing difficulty and excellent characteristics at a high product yield include suppression of the short channel effect and threshold voltage (hereinafter referred to as the threshold voltage). , _Vth ).
However, there has conventionally been a problem that it is difficult to realize these two processes simultaneously. This is because the above processes are in a mutually contradictory relationship (trade-off relationship). For example, in order to suppress the short channel effect, it is necessary to suppress the extension of the depletion layer from the source and drain ends included in the SOI-MOSFET. For this reason, it is necessary to introduce a conductive impurity into a deep part of the SOI layer (for example, near the boundary between the SOI layer and the BOX layer) to form a layer with a high impurity concentration (that is, a punch-through stopper region). However, since the introduction of such conductive impurities is performed through a shallow part of the SOI layer, the impurity concentration in the vicinity of the surface of the SOI layer is affected. For this reason, there may be a problem that a desired _Vth value cannot be obtained or the degree of variation of the _Vth value is large.

On the other hand, in order to set the _Vth value accurately, it is necessary to introduce conductive impurities for setting the _Vth value only in the vicinity of the surface of the SOI layer and to form a layer having a high impurity concentration there. For this reason, a punch-through stopper region is not formed in the vicinity of the boundary between the SOI layer and the BOX layer. Therefore, the depletion layer extends from the source and drain ends inevitably, and as a result, there may be a disadvantage that the short channel effect cannot be suppressed.
Accordingly, some aspects of the present invention have been made in view of such a problem, and are capable of suppressing the short channel effect and improving the controllability of the _Vth value. It is an object to provide a method and a semiconductor device.

  In order to achieve the above object, a method for manufacturing a semiconductor device according to one embodiment of the present invention includes manufacturing a semiconductor device in which a semiconductor layer provided over an insulating layer includes a source and a drain containing an impurity of a first conductivity type. In the method, a second conductivity type impurity is introduced into a deep portion of the semiconductor layer to form a punch-through stopper region, and simultaneously introduced into a shallow portion of the semiconductor layer to form a first threshold region. And a step of introducing the first conductivity type impurity into a shallow portion of the semiconductor layer into which the second conductivity type impurity is introduced to form a second threshold region in at least a part of the first threshold region. And a forming step.

According to the above method, the introduced second conductivity type impurity forms a punch-through stopper region that suppresses the extension of the depletion layer from the source and drain ends and suppresses the short channel effect. A first threshold region can be formed above the stopper region. Further, by introducing the first conductivity type impurity, a second threshold region having a _Vth value lower than that of the first threshold region can be formed. As a result, it is possible to provide a semiconductor device that suppresses the short channel effect and improves the controllability of the _Vth value (that is, has a small degree of variation).

Further, in the above manufacturing method, the first conductivity type impurity is introduced into a shallow portion of the semiconductor layer to at least a part of the first threshold region or at least a part of the second threshold region. The method may further include a step of forming a third threshold region.
According to the above method, the first threshold region or the third threshold region having a _Vth value lower than that of the second threshold region can be formed. Thereby, it is possible to form a plurality of types of threshold regions at a desired position in one chip while suppressing the short channel effect and improving the controllability of the _Vth value.

Furthermore, the manufacturing method may further include a step of performing a heat treatment on the semiconductor layer after the step of forming the second threshold region.
According to said method, the heat processing process implemented after the process of forming a 1st threshold value area | region can be skipped. By performing the heat treatment step only after forming the second threshold region, the number of manufacturing steps can be reduced by one step. As a result, it is possible to produce a semiconductor device in which the short channel effect is suppressed and the controllability of the _Vth value is improved while suppressing the manufacturing cost.

Further, the above manufacturing method may further include a step of performing a heat treatment on the semiconductor layer after the step of forming the third threshold region.
According to said method, the heat processing process implemented after the process of forming the 1st and 2nd threshold value area | region can be skipped. By performing the heat treatment step only after forming the third threshold region, the heat treatment step to be performed can be performed once regardless of the number of threshold regions to be formed. Thereby, a product can be manufactured without increasing a manufacturing process. Therefore, the short channel effect is suppressed, and it is possible to produce a semiconductor device in which the control of the V _th value is increased at a low manufacturing cost.

Furthermore, in the above manufacturing method, the step of forming the punch-through stopper region and the first threshold region is performed on the semiconductor layer in a state where the region where the source and drain are formed is covered with a mask. This may be a feature.
According to the above method, it is possible to prevent the second conductivity type impurity from being introduced below the region where the source and drain are formed. As a result, it is possible to prevent a substantial decrease in the concentration of impurities of the first conductivity type in the source and drain (that is, a decrease in concentration due to counterdoping), and it is possible to prevent the resistance of the source and drain from increasing. Thereby, not only the suppression of the short channel effect can be improved, but also the driving power of the semiconductor device can be lowered.

Furthermore, in the above manufacturing method, the step of forming the punch-through stopper region and the first threshold region may be performed on the semiconductor layer after the element isolation region is formed.
According to the above method, when forming the punch-through stopper region and the first threshold region, it is not necessary to consider the influence of thermal history and impurity diffusion when forming the element isolation region. Therefore, it becomes easy to accurately match the positions and densities of the punch-through stopper region and the first threshold region with preset values.

  A semiconductor device according to another aspect of the present invention includes a substrate having a semiconductor layer formed on an insulating layer, a gate insulating film provided on the semiconductor layer, and a gate provided on the gate insulating film. A semiconductor device including a transistor having an electrode and a source and a drain including an impurity of a first conductivity type provided in the semiconductor layer below both sides of the gate electrode, and below the gate electrode, A punch-through stopper region containing a second conductivity type impurity provided in a deep portion of the semiconductor layer, a first threshold region and a first threshold region provided in a shallow portion of the semiconductor layer below the gate electrode. 2 threshold regions, wherein the first threshold region includes only second conductivity type impurities, and the second threshold region includes first conductivity type impurities and second conductivity type impurities. Features It is intended.

According to the device having such a configuration, the extension of the depletion layer from the source and drain ends can be suppressed by the introduced second conductivity type impurity. As a result, the short channel effect can be effectively suppressed as compared with the semiconductor device in which the second conductivity type impurity is not implanted. Furthermore, the _Vth value can be accurately adjusted by introducing the first conductivity type impurity.

Sectional drawing which shows the manufacturing process of the semiconductor device which concerns on 1st embodiment of this invention. Sectional drawing which shows the manufacturing process of the semiconductor device which concerns on 1st embodiment of this invention. The top view which shows the manufacturing process of the semiconductor device which concerns on 1st embodiment of this invention. Sectional drawing which shows the manufacturing process of the semiconductor device which concerns on 2nd embodiment of this invention. Sectional drawing which shows the manufacturing process of the semiconductor device which concerns on 3rd embodiment of this invention. Experimental data showing the short channel effect in n-type and p-type transistors. Experimental data showing the _Vth value and the degree of variation in n-type transistors. Experimental data showing the _Vth value and the degree of variation in p-type transistors.

Hereinafter, an embodiment of the present invention will be described with reference to the accompanying drawings.
(1) First Embodiment FIGS. 1A to 1E and FIGS. 2A to 2F are cross-sectional views showing a manufacturing process of a semiconductor device according to a first embodiment of the present invention. . 3A to 3E are plan views showing the manufacturing process of the semiconductor device according to the first embodiment of the present invention. In the drawing, the X-axis direction and the Y-axis direction indicate the substrate horizontal direction, and the Z-axis direction indicates the substrate vertical direction.

Hereinafter, a case of forming a first conductivity type (for example, p-type) field effect transistor will be described.
First, in FIG. 1A, an SOI substrate in which an insulating layer 4 (BOX layer) is formed on a bulk silicon (Si) substrate 3 and a semiconductor layer 5 is formed thereon is prepared. Here, the insulating layer 4 is, for example, a Si oxide film, and the semiconductor layer 5 is, for example, a single crystal Si layer. This SOI substrate is formed by, for example, a SIMOX (Separation by Implanted Oxygen) method or a bonding method. Next, the element isolation region 6 is formed in the semiconductor layer 5 by using, for example, a LOCOS (Local Oxidation of Silicon) method. Here, as shown in FIG. 3A, a region surrounded by the element isolation region 6 (that is, a region where the element isolation region 6 is not formed) is an element region.

Next, in FIG. 1B, for example, phosphorus (P ⁺ ) is introduced into the semiconductor layer 5 as the second conductivity type (in this case, n-type) impurity 2. Thereby, as shown in FIG. 1C, the punch-through stopper region 7 is formed in the vicinity of the boundary between the semiconductor layer 5 and the insulating layer 4, and at the same time, the first threshold region 8 is formed in the vicinity of the surface of the semiconductor layer 5. To do. In this case, if the SOI layer is about 1400 mm, it is preferable that the incident energy of P ⁺ is about 150 keV and the introduction amount is about 2.1 × 10 ¹³ / cm ^2. However, the present invention is not limited to this. Absent. A plan view of the above process is as shown in FIG. 3B. For example, the first threshold region 8 is formed in the entire element region. In the present specification, the threshold value indicated by the formed first threshold value region 8 is represented as V _th 1.

Next, in FIG. 1D, a part or all of the first threshold region 8 formed by the process of FIG. 1B is used as the first conductivity type impurity 1 as, for example, boron fluoride (BF ₂ ⁺ ) To form the second threshold region 9. In this case, it is preferable that the incident energy of BF ₂ ⁺ is about 30 keV and the introduction amount is about 3.5 × 10 ¹² / cm ² , but the present invention is not limited to this. Here, as shown in FIG. 3C, for example, when a mask is applied only to a desired region in the first threshold region 8, the second threshold region 9 is formed in a region not covered with the mask. Is done. Then, after the second threshold region 9 is formed, the mask is removed. In the present specification, the threshold value indicated by the formed second threshold value region 9 is represented as V _th 2. Further, the mask applied in this manufacturing process corresponds to a region surrounded by a broken line in the drawing.

Next, in FIG. 1 (e), as in FIG. 1 (d), as a first conductivity type impurity 1 in part or all of the first threshold region 8 formed by the process of FIG. 1 (b). For example, BF ₂ ⁺ is introduced to form the third threshold region 10. The third when forming the threshold region 10 introduces a large amount of BF ₂ ⁺ than the formation of the second threshold region 9 some or all of the first threshold area 8. Note that when the second threshold region 9 or the third threshold region 10 is formed, it is desirable to make the incident energy of BF ₂ ^{+ to be} introduced equal to each other. This is because the depth that the impurity reaches depends on the incident energy of the impurity to be introduced.

Therefore, when the third threshold region 10 is formed, for example, it is preferable that the incident energy of BF ₂ ⁺ is about 30 keV and the introduction amount is about 1.0 × 10 ¹³ / cm ² . By doing so, the impurity concentration of the first conductivity type in the third threshold region 10 can be made higher than that in the second threshold region 9. That is, as shown in FIG. 3D, for example, when a mask is formed in all of the desired region in the first threshold region 8 and the second threshold region 9, the region that is not covered with the mask is used. A third threshold region 10 is formed. Then, the chip shown in FIG. 3E is manufactured by removing the mask after forming the third threshold region 10. In the present specification, the threshold value indicated by the formed third threshold region 10 is represented as V _th 3.

The first conductivity type impurity concentration in the first threshold region 8 thus formed is C1, the first conductivity type impurity concentration in the second threshold region 9 is C2, and the first conductivity type impurity concentration in the third threshold region 10 is C1. When the impurity concentration is expressed as C3, the magnitude relationship between them is C3>C2> C1. When a first conductivity type transistor is formed in each semiconductor layer 5 in FIGS. 1C to 1E (for example, corresponding to FIGS. 2D to 2F), the threshold voltage of these transistors is As the impurity concentration of the first conductivity type increases, it decreases as the _Vth value in each threshold value region becomes V _th 1> V _th 2> V _th 3.

The subsequent manufacturing process is in accordance with a general transistor manufacturing process. For example, first, as shown in FIGS. 2A to 2C, the semiconductor layer 5 in which the first threshold region 8, the second threshold region 9, and the third threshold region 10 are formed is thermally oxidized. Then, a gate insulating film 12 is formed on the surface. Next, the gate electrode 13 is formed on the semiconductor layer 5 in each threshold region via the gate insulating film 12. Then, using the gate electrode 13 as a mask, the first conductivity type impurity 1 (for example, BF ₂ ⁺ ) is introduced into each semiconductor layer 5. Thereafter, the SOI substrate is subjected to a heat treatment to thermally diffuse the first conductivity type impurity 1 introduced into each semiconductor layer 5, and a source is formed in each semiconductor layer 5 as shown in FIGS. 14 and drain 15 are formed. In this manner, a transistor having a threshold voltage of V _th 1, a transistor having a threshold voltage of V _th 2, and a transistor having a threshold voltage of V _th 3 can be formed in the semiconductor layer 5 in one chip. .

As described above, according to the first embodiment of the present invention, the low-energy counter ion implantation (FIG. 1 (d), FIG. 1) is applied to the high-energy body ion implantation (step of FIG. 1 (b)). Each step of (e) is added. As a result, it is possible to improve the controllability of the _Vth value while suppressing the short channel effect, and to realize a partially depleted transistor with a small degree of variation. A semiconductor device provided with a large number of such transistors in one chip can be provided.
Further, according to the above embodiment, after the element isolation region 6 is formed, the first threshold region 8, the second threshold region 9, and the third threshold region 10 are formed. Thereby, it is not necessary to consider the influence of thermal history and impurity diffusion when the element isolation region 6 is formed. Therefore, it is easy to accurately match the position of the punch-through stopper region 7 and the position of each threshold region, their density, and the like with preset values.

  In the above embodiment, after the third threshold region 10 is formed, the semiconductor layer 5 is subjected to heat treatment to thermally diffuse the impurities contained in each threshold region. In other words, the heat treatment step performed after the step of forming the first and second threshold regions is omitted, and the heat treatment step is performed after the third threshold region 10 is formed. First, the heat treatment step for forming the threshold region can be performed once. In this way, manufacturing costs can be reduced by minimizing the number of heat treatment steps.

(2) Second Embodiment In the above embodiment, the third threshold region 10 is formed by introducing the first conductivity type impurity 1 into a part or all of the first threshold region 8 (FIG. 1). (E)) has been described. However, the present invention is not limited to this.
4A to 4E are cross-sectional views illustrating the manufacturing steps of the semiconductor device according to the second embodiment of the present invention. For example, as shown in FIGS. 4A to 4E, the first conductivity type impurity 1 is introduced again into part or all of the second threshold value region 9 instead of the first threshold value region 8 to Four threshold regions 11 may be formed. In this case, the third threshold region 10 and the fourth threshold region 11 may be formed simultaneously, or only the fourth threshold region 11 may be formed without forming the third threshold region 10. . In the present specification, the threshold value indicated by the formed fourth threshold region 11 is expressed as V _th 4.
In the second embodiment, the four regions of the first threshold region 8, the second threshold region 9, the third threshold region 10, and the fourth threshold region 11 are exemplified. The number of areas is not limited. That is, more threshold regions can be formed by performing the step of introducing the first conductivity type impurity 1 a plurality of times.

(3) Third Embodiment In the above embodiment, as shown in FIG. 1B, for example, the second conductivity type impurity 2 is introduced without covering the semiconductor layer 5 in the element region with a mask. Explained the case. However, in the present invention, the impurity 2 may be introduced using a mask 16 made of, for example, a photoresist or an insulating film.
FIGS. 5A to 5F are cross-sectional views showing the manufacturing steps of the semiconductor device according to the third embodiment of the present invention. For example, as shown in FIGS. 5A and 5B, P ⁺ is introduced in a state where a part of the semiconductor layer 5 is covered with a mask 16, and the punch-through stopper region 7 and the first threshold region 8 are formed. It may be formed in the semiconductor layer 5. Here, when this mask 16 is applied to the portion where the source 14 and the drain 15 are formed, the punch-through stopper region 7 is formed below the source 14 and drain 15 regions as shown in FIGS. Is not formed. As a result, the resistance of the source 14 and the drain 15 can be prevented from being increased. The first threshold region 8, the second threshold region 9, the third threshold region 10, and the fourth threshold region 11 shown in FIGS. 5C to 5F are formed as shown in FIGS. According to the formation method shown in FIG.

(4) Other Embodiments The present invention is not limited to the formation of the p-type field effect transistor, and can exhibit the same operations and effects in the formation of the n-type field effect transistor. it can. When forming an n-type field effect transistor, the first conductivity type impurity 1 is n-type and the second conductivity type impurity 2 is p-type. In this case, when forming the punch-through stopper region 7 and the first threshold region 8, for example, body ions are introduced with B ⁺ as the second conductivity type impurity 2. At that time, it is preferable that the incident energy of B ⁺ is about 50 keV and the introduction amount is about 1.2 × 10 ¹³ / cm ² . When the second threshold region 9 is formed, for example, counter ions are introduced using P ⁺ as the first conductivity type impurity 1. At that time, it is preferable that the incident energy of P ⁺ is about 20 keV and the introduction amount is about 4.6 × 10 ¹² / cm ² .

  In the first, second, third, and other embodiments described above, the second conductivity type impurity 2 is introduced as the body ion, and then the first conductivity type impurity 1 is introduced as the counter ion. The invention is not limited to this order. That is, first, the first conductivity type impurity 1 is introduced into the semiconductor layer 5 to form a plurality of threshold regions, and then the second conductivity type impurity 2 is introduced to form the punch-through stopper region 7. good.

(5) About Experimental Data FIG. 6 is a diagram showing the difference in short channel effect depending on the presence or absence of a punch-through stopper region in n-type and p-type transistors. The vertical axis in FIG. 6 represents the measured _Vth value, and the horizontal axis represents the channel length. In the figure, a solid line connecting ◆ indicates a short channel effect in the case of an n-type transistor having a punch-through stopper region, and a solid line connecting n is an n-type transistor without a punch-through stopper region. The short channel effect in the case of. In addition, ◆ connected with a broken line indicates a short channel effect in the case of a p-type transistor provided with a punch-through stopper region, and ◇ connected with a broken line indicates a case of a p-type transistor provided with no punch-through stopper region. The short channel effect is shown.

What is commonly observed in the above four cases is that the _Vth value decreases as the channel length decreases. However, as can be seen from FIG. 6, when the punch-through stopper region is provided, the rate of decrease in each transistor is relatively small, and approximately 90% or more of V when the channel length is sufficiently long. It becomes _th value. On the other hand, when the punch-through stopper region is not provided, the reduction rate is large in each transistor, and the _Vth value is approximately 70 to 80% when the channel length is sufficiently long. That is, this result shows that by providing a punch-through stopper region in the transistor, the short channel effect can be effectively suppressed regardless of whether the transistor is an n-type transistor or a p-type transistor. .

FIG. 7 is experimental data showing the measured values of the _Vth values in the two threshold regions provided in the n-type transistor having the punch-through stopper region and the variation degree in each measured value for each lot number. The vertical axis in FIG. 7 indicates the measured value, and the horizontal axis indicates each lot number. In this experiment, when two threshold regions are provided in advance in the same lot and these threshold values are set to V _th 1 and V _th 2, respectively, V _th 1 = 0.55V and V _th 2 = 0.37V are set values. did. These set values are indicated by broken lines in the figure. The lot numbers were 1 to 6. In the figure, ◆ and ■ indicate the measured value of V _th 1 and the measured value of V _th 2, respectively.

  First, pay attention to the measured value and the degree of variation in the same lot. As shown in FIG. 7, the measured values substantially coincide with the respective set values. Further, each measurement value is provided with a bar (error bar; error range) indicating the degree of variation of the value. The value of this error bar is approximately ± 0.01V. This value is approximately 1/10 of the case where the conventional technique is used. That is, this result indicates that the present invention has improved threshold setting accuracy compared to the prior art.

Next, attention will be focused on the measurement value for each lot and the degree of variation thereof. There are no large fluctuations in the two measured values in each lot, and they almost coincide with the set values. Also, the error bar value is approximately ± 0.01 V in each lot, and there is no significant fluctuation. That is, this result indicates that a threshold region having a desired threshold can be formed repeatedly.
Similar results were obtained for a p-type transistor having a punch-through stopper region. Next, the obtained result is shown in FIG.

FIG. 8 is experimental data showing the measured values of the _Vth values in the three threshold regions provided in the p-type transistor having the punch-through stopper region and the variation degree in each measured value for each lot number. As in the case of FIG. 7, the vertical axis of FIG. 8 indicates the measured value, and the horizontal axis indicates the lot number. In this experiment, when three threshold regions are provided in the same lot in advance and these threshold values are V _th 1, V _th 2 and V _th 3, respectively, V _th 1 = 0.55V, V _th 2 = 0.45V V _th 3 = 0.25 V was set as a set value. These set values are indicated by broken lines in the figure. The lot numbers were 1 to 6. In the figure, ◆, ■, and ▲ indicate the measured value of V _th 1, the measured value of V _th 2, and the measured value of V _th 3, respectively.
First, pay attention to the measured value and the degree of variation in the same lot. As shown in FIG. 8, the measured values substantially coincide with the respective set values. Further, each measurement value is provided with an error bar indicating the degree of variation of the value. The value of this error bar is approximately ± 0.01V.

Next, attention will be focused on the measurement value for each lot and the degree of variation thereof. The three measured values in each lot do not vary greatly, and are almost in agreement with the respective set values. Also, the error bar value is approximately ± 0.01 V in each lot, and there is no significant fluctuation.
That is, FIG. 7 and FIG. 8 show that a transistor having a desired _Vth value and suppressing a short channel effect is repeated by manufacturing n-type and p-type transistors by the manufacturing method according to the present invention. Can be manufactured high (ie, with high product yield).

DESCRIPTION OF SYMBOLS 1 1st conductivity type impurity, 2 2nd conductivity type impurity, 3 Substrate, 4 Insulating layer, 5 Semiconductor layer, 6 Element isolation region, 7 Punch-through stopper region, 8 First threshold region, 9 Second threshold Region, 10 third threshold region, 11th threshold region, 12 gate insulating film, 13 gate electrode, 14 source, 15 drain, 16 mask, V _th 1 threshold in first threshold region, V _th 2 second Threshold in the threshold region, V _th 3 threshold in the third threshold region, V _th 4 threshold in the fourth threshold region

Claims (7)

A method of manufacturing a semiconductor device having a source and a drain containing a first conductivity type impurity in a semiconductor layer provided on an insulating layer,
Introducing a second conductivity type impurity into a deep portion of the semiconductor layer to form a punch-through stopper region and simultaneously introducing it into a shallow portion of the semiconductor layer to form a first threshold region;
Introducing the first conductivity type impurity into a shallow portion of the semiconductor layer into which the second conductivity type impurity is introduced to form a second threshold region in at least a part of the first threshold region; When,
A method for manufacturing a semiconductor device, comprising:   An impurity of the first conductivity type is introduced into a shallow portion of the semiconductor layer to form a third threshold region in at least part of the first threshold region or at least part of the second threshold region. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of:   The method of manufacturing a semiconductor device according to claim 1, further comprising a step of performing a heat treatment on the semiconductor layer after the step of forming the second threshold region.   The method for manufacturing a semiconductor device according to claim 2, further comprising a step of performing a heat treatment on the semiconductor layer after the step of forming the third threshold region.   2. The step of forming the punch-through stopper region and the first threshold region is performed on the semiconductor layer in a state where a region where the source and drain are formed is covered with a mask. A method for manufacturing a semiconductor device according to claim 4.   6. The step of forming the punch-through stopper region and the first threshold region is performed on the semiconductor layer after the element isolation region is formed. A method for manufacturing the semiconductor device according to the item. A substrate having a semiconductor layer formed on an insulating layer;
A gate insulating film provided on the semiconductor layer;
A gate electrode provided on the gate insulating film;
A semiconductor device including a transistor having a source and a drain including a first conductivity type impurity provided in the semiconductor layer below both sides of the gate electrode,
A punch-through stopper region including a second conductivity type impurity provided in a deep portion of the semiconductor layer below the gate electrode;
A first threshold region and a second threshold region provided below the gate electrode and in a shallow portion of the semiconductor layer;
The first threshold region includes only impurities of a second conductivity type;
The semiconductor device, wherein the second threshold region includes a first conductivity type impurity and a second conductivity type impurity.

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