JP2010211949A - Discharge lamp lighting circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the following problem: if a power supply voltage drops by short circuit of a discharge lamp, the high side transistor in a H bridge circuit is possibly hindered from switching on and off. <P>SOLUTION: In this discharge lamp lighting circuit 100, the H bridge circuit 30 includes two pairs of a high side transistor and a low side transistor placed in series between a ground potential and a dc power supply voltage Vo, and supplies a driving voltage VL to the discharge lamp 4. A control circuit 10 controls switching on and off of the transistors. Two high side transistors are switched on using the power supply voltage Vo. The control circuit 10 performs control to stop supplying the driving voltage VL, if the abnormal state of the discharge lamp 4 continues for a period longer than an abnormality detecting period, and switches off the two high side transistors included in the H bridge circuit 30 as the control to stop supplying the driving voltage VL, if a state in which the power supply voltage Vo is lower than a prescribed short circuit detection voltage, among various abnormal states, continues for a period longer than a short circuit detection period shorter than the abnormality detecting period. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a discharge lamp lighting circuit capable of detecting an abnormality of a discharge lamp.

  In recent years, metal halide lamps (hereinafter referred to as discharge lamps) have been used as vehicle lamps such as headlamps in place of conventional halogen lamps having a filament. Although a discharge lamp can achieve luminous efficiency and a long life compared to a halogen lamp, it requires several tens to several hundreds V as a driving voltage. An electric lighting circuit (also called ballast) is required.

  A discharge lamp lighting circuit includes a DC / DC converter that boosts a battery voltage, a switching circuit such as an H-bridge circuit that converts an output voltage of the DC / DC converter, a starter circuit, and a control circuit that controls these circuit blocks. (For example, refer to Patent Document 1).

  The abnormalities that can occur in a discharge lamp include a ground fault in which the terminal of the discharge lamp is unintentionally grounded, a short circuit in which the two terminals of the discharge lamp conduct with low resistance due to contact, etc., and wear of the electrode. There is an open circuit where the lamp current stops flowing. It is desirable that the discharge lamp lighting circuit has a function of detecting such an abnormality and stopping driving of the discharge lamp.

JP 11-329777 A

About the detection of abnormality of a discharge lamp, this inventor recognized the following subjects.
Consider a case where the output voltage of a DC / DC converter is used to turn on and off the high-side transistor of the H-bridge circuit. For example, the high-side transistor is turned on / off by bootstrap. Here, when the discharge lamp is short-circuited, the output voltage of the DC / DC converter decreases. In order to avoid erroneous detection, it takes some time after the discharge lamp short circuit occurs until the discharge lamp lighting circuit detects the short circuit and stops driving the discharge lamp. If the output voltage of the DC / DC converter becomes lower than the threshold voltage that determines on / off of the high side transistor during this period, there is a possibility that the on / off operation of the high side transistor may be hindered.

  The present invention has been made in view of such circumstances, and its purpose is to discharge a discharge lamp that can stably perform switching using the power supply voltage even if an abnormality of the discharge lamp that can lower the power supply voltage occurs. In providing the circuit.

  One embodiment of the present invention relates to a discharge lamp lighting circuit. This discharge lamp lighting circuit includes two sets of a high-side transistor and a low-side transistor placed in series between a fixed voltage and a DC power supply voltage, and supplies an AC drive voltage to a discharge lamp to be driven. And a control unit for controlling on / off of the two sets of the high-side transistor and the low-side transistor. Two high-side transistors included in the H-bridge circuit are turned on using a power supply voltage. When the abnormal state of the discharge lamp lasts longer than the predetermined abnormality detection period, the control unit performs control for stopping the supply of the drive voltage, and even in the abnormal state, the state where the power supply voltage is lower than the predetermined short-circuit detection voltage is abnormal. If it lasts longer than the short-circuit detection period shorter than the detection period, the two high-side transistors included in the H-bridge circuit are turned off as control for stopping the supply of the drive voltage.

The “abnormal state of the discharge lamp” may be a state in which the parameters of the discharge lamp lighting circuit satisfy a predetermined condition due to the abnormality of the discharge lamp.
According to this aspect, in order to turn on the high side transistor by turning off the two high side transistors included in the H bridge circuit when the power supply voltage is lower than the short circuit detection voltage for a longer period than the short circuit detection period. The power supply voltage used can be increased.

  When the power supply voltage is lower than the short-circuit detection period for a longer period than the short-circuit detection period, the control unit turns off the two high-side transistors included in the normal operation period in which the H-bridge circuit operates normally and the H-bridge circuit. The period may be repeated. In this case, when the discharge lamp continues to be short-circuited, the power supply voltage decreases during the normal operation period, so that the power supply voltage can be kept lower than the short-circuit detection voltage.

  The control unit may return the H-bridge circuit to the normal operation on condition that the power supply voltage in the normal operation period is higher than the short circuit detection voltage. In this case, when the short circuit of the discharge lamp is eliminated, the H bridge circuit can be returned to normal operation.

  The normal operation period may be set shorter than a half cycle of the AC drive voltage.

  Both off periods may be set longer than the normal operation period.

  ADVANTAGE OF THE INVENTION According to this invention, even if the abnormality of the discharge lamp which can reduce a power supply voltage generate | occur | produces, the switching using a power supply voltage can be performed stably.

It is a circuit diagram which shows the structure of the discharge lamp lighting circuit which concerns on embodiment, and the member connected to it. It is a circuit diagram which shows the structure of a bridge control part. It is a time chart which shows the waveform of the signal contained in the abnormality detection part of FIG. 2 when the short circuit of a discharge lamp arises in a steady lighting state. It is a time chart which shows the operation state of the discharge lamp lighting circuit of FIG. FIGS. 5A and 5B are time charts showing an operation state after the DC period of the discharge lamp lighting circuit. 2 is a time chart showing an operation state of a discharge lamp lighting circuit when a user turns on a power switch to start the discharge lamp lighting circuit of FIG. 1 in a state where a short circuit has occurred in the discharge lamp.

  The present invention will be described below based on preferred embodiments with reference to the drawings. The same or equivalent components, members, and processes shown in the drawings are denoted by the same reference numerals, and repeated descriptions are omitted as appropriate.

  In this specification, “the state in which the member A is connected to the member B” means that the member A and the member B are electrically connected in addition to the case where the member A and the member B are physically directly connected. It includes the case of being indirectly connected through another member that does not affect the connection state. Similarly, “the state in which the member C is provided between the member A and the member B” refers to the case where the member A and the member C or the member B and the member C are directly connected, as well as an electrical condition. It includes the case of being indirectly connected through another member that does not affect the connection state.

  In the discharge lamp lighting circuit according to the embodiment, the discharge lamp is AC-driven using an H bridge circuit. The discharge lamp lighting circuit includes a bootstrap circuit for driving a transistor on the high side of the H bridge circuit. When both terminals of the discharge lamp are short-circuited for some reason, the lamp current flows through the short-circuited portion, but the power supply voltage supplied to the H-bridge circuit is lowered. If the power supply voltage is lower than the voltage necessary for driving the high-side transistor, it may hinder the on-off of the high-side transistor. Therefore, in the discharge lamp lighting circuit according to the present embodiment, when the short-circuit state continues for a predetermined period, the control is switched to intermittently supplying the drive voltage to the discharge lamp. The power supply voltage rises during the period when the supply of the driving voltage to the discharge lamp is stopped. As a result, the driving capacitor connected to the bootstrap circuit can be charged, so that the high-side transistor can be turned on and off more reliably.

  FIG. 1 is a circuit diagram showing a configuration of a discharge lamp lighting circuit 100 and members connected thereto according to the embodiment. The discharge lamp lighting circuit 100 drives a vehicle-mounted discharge lamp 4 that is a metal halide lamp. The discharge lamp lighting circuit 100 is connected to an in-vehicle battery (hereinafter simply referred to as a battery) 6 and a power switch 8. The discharge lamp lighting circuit 100 and the discharge lamp 4 are unitized as a vehicular lamp.

  The battery 6 generates a DC battery voltage Vbat of 12V (or 24V). The power switch 8 is a relay switch provided for controlling on / off of the discharge lamp 4 and is provided in series with the battery 6. When the power switch 8 is turned on, the battery voltage Vbat is supplied from the battery 6 to the discharge lamp lighting circuit 100.

  The discharge lamp lighting circuit 100 boosts the smoothed battery voltage Vbat, converts it into an alternating current, and supplies it to the discharge lamp 4. Hereinafter, a detailed configuration of the discharge lamp lighting circuit 100 will be described.

  The discharge lamp lighting circuit 100 includes a DC / DC converter CONV, a control circuit 10, a starter circuit 20, an H bridge circuit 30, a first driving capacitor C1, a second driving capacitor C2, an input capacitor Cin, and a first bootstrap circuit B1. , A second bootstrap circuit B2 and a current detection resistor R1.

  Input capacitor Cin is provided in parallel with battery 6 and smoothes battery voltage Vbat. More specifically, the input capacitor Cin is provided in the vicinity of the transformer 14 and fulfills a voltage smoothing function for the switching operation of the DC / DC converter CONV.

  The discharge lamp lighting circuit 100 supplies an alternating drive voltage VL having a lighting frequency f1 between both ends of the discharge lamp 4 in a run-up period and a steady lighting period to be described later. The lighting frequency f1 is preferably 10 kHz or less, more preferably 250 Hz to 750 Hz, and here it is set to 310 Hz. The reciprocal of the lighting frequency f1 is referred to as a lighting cycle T1 (= 1 / f1 = 3.2 ms).

  The DC / DC converter CONV boosts the battery voltage Vbat. The DC / DC converter CONV is a non-insulated switching regulator, and includes a transformer 14, a rectifier diode D1, an output capacitor Co, and a switching element M1.

  One end of the primary coil L1 of the transformer 14 and one end of the secondary coil L2 are connected in common with the drain of the switching element M1. The primary coil L1 and switching element M1 of the transformer 14 are provided in series between the input terminal Pin of the DC / DC converter CONV and the ground terminal (GND) in parallel with the input capacitor Cin. For example, the switching element M1 is composed of an N-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The other end of the secondary coil L2 of the first transformer 14 is connected to the anode of the rectifier diode D1. The output capacitor Co is provided between the cathode of the rectifier diode D1 and the ground terminal.

A control pulse signal Sp having a PWM frequency f2 higher than the lighting frequency f1 is applied to the control terminal (gate) of the switching element M1. For example, the PWM frequency f2 is 400 kHz. The switching element M1 is turned on when the control pulse signal Sp is at a high level and turned off when it is at a low level. The control circuit 10 adjusts the high-level and low-level duty ratios of the control pulse signal Sp by feedback based on the electrical state of the discharge lamp 4.
The boosted DC power supply voltage Vo is supplied to the H bridge circuit 30 at the subsequent stage.

The H bridge circuit 30 is placed in series between the first high-side transistor MH1 and the first low-side transistor ML1 placed in series between the ground terminal and the power supply voltage Vo, and similarly between the ground terminal and the power supply voltage Vo. The second high-side transistor MH2 and the second low-side transistor ML2 are supplied to supply the AC driving voltage VL to the discharge lamp 4.
The first high side transistor MH1, the second high side transistor MH2, the first low side transistor ML1, and the second low side transistor ML2 are IGBTs (Insulated Gate Bipolar Transistors).

On / off of the first high-side transistor MH1 is controlled by a first high-side control signal SH1 supplied from the first bootstrap circuit B1. The first high side control signal SH1 is generated using the battery voltage Vbat or the power supply voltage Vo. The second high side transistor MH2 is controlled to be turned on / off by the second high side control signal SH2 supplied from the second bootstrap circuit B2. The second high side control signal SH2 is generated using the battery voltage Vbat or the power supply voltage Vo.
On / off of the first low-side transistor ML1 and the second low-side transistor ML2 is controlled by a first low-side control signal SL1 and a second low-side control signal SL2 supplied from the control circuit 10 to the gates of the transistors, respectively.

  The first output voltage Vo1 at the first connection point N1 between the first high-side transistor MH1 and the first low-side transistor ML1 is applied to one end P1 of the discharge lamp 4 via the starter circuit 20. The second output voltage Vo2 at the second connection point N2 between the second high-side transistor MH2 and the second low-side transistor ML2 is applied to the other end P2 of the discharge lamp 4.

  The control circuit 10 includes a first state φ1 that turns on a pair of the first high-side transistor MH1 and the second low-side transistor ML2, and a second state φ2 that turns on a pair of the second high-side transistor MH2 and the first low-side transistor ML1. Are alternately repeated at the lighting frequency f1 to supply the AC drive voltage VL to the discharge lamp 4.

  In the first state φ1, the first output voltage Vo1 (≈Vo) is applied to one end P1 of the discharge lamp 4, and the ground voltage (0V) is applied to the other end P2, and as a result, the drive voltage VL is applied to the discharge lamp 4. (≈Vo1) is applied with the first polarity. In the second state φ2, the second output voltage Vo2 (≈Vo) is applied to the other end P2 of the discharge lamp 4 and the ground voltage is applied to the one end P1, and as a result, the driving voltage VL (≈Vo2) is applied to the discharge lamp 4. ) Is applied with a second polarity opposite to the first polarity.

When the first base signal SH1 ′ becomes low level, the first bootstrap circuit B1 uses a voltage obtained by adding the first high-side control signal SH1 to the power supply voltage Vo and the gate-emitter voltage of the first high-side transistor MH1. Is a high voltage signal. As a result, a sufficient gate-emitter voltage is applied to the first high-side transistor MH1, and the first high-side transistor MH1 is turned on. For this purpose, the first bootstrap circuit B1 is connected to the other end of the first driving capacitor C1 whose one end is connected to the first connection point N1, and generates a first terminal voltage Vc1 generated in the first driving capacitor C1. Use.
Here, the gate-emitter voltage of the first high-side transistor MH1 is a voltage at which the first high-side transistor MH1 is turned on when a voltage higher than that voltage is applied between the gate and the emitter of the first high-side transistor MH1. It is.

The first bootstrap circuit B1 includes a first BS resistor 52, a first BS diode 54, a second BS resistor 56, and three Zener diodes (hereinafter referred to as first Zener diodes) 58 connected in series in the same direction. , A first npn-type bipolar transistor 60, a first pnp-type bipolar transistor 62, a third BS resistor 64, a fourth BS resistor 66, and a first switch transistor 68.
A power supply voltage Vo is applied to one end of the first BS resistor 52. The other end of the first BS resistor 52 is connected to the anode of the first BS diode 54. The cathode of the first BS diode 54 is connected to one end of the fourth BS resistor 66, the collector of the first npn bipolar transistor 60, the cathode of the first Zener diode 58, and the other end of the first driving capacitor C1. The emitter of the first npn-type bipolar transistor 60 is connected to the emitter of the first pnp-type bipolar transistor 62, and the signal at the connection node is passed through the second BS resistor 56 as the first high-side control signal SH1 and the gate of the first high-side transistor MH1. To be supplied. The first output voltage Vo1 of the first connection point N1 is applied to the collector of the first pnp bipolar transistor 62 and the anode of the first Zener diode 58. The base of the first npn-type bipolar transistor 60 and the base of the first pnp-type bipolar transistor 62 are both connected to one end of the third BS resistor 64. The other end of the fourth BS resistor 66 and the other end of the third BS resistor 64 are both connected to the collector of the first switch transistor 68. The emitter of the first switch transistor 68 is grounded, and the first base signal SH1 ′ is input to the base.

  The breakdown voltage (sum of the breakdown voltages of the three Zener diodes) Vz of the first Zener diode 58 is set to a value higher than the gate-emitter voltage of the first high-side transistor MH1, for example, 20V.

  According to the configuration of the first bootstrap circuit B1, when the first switch transistor 68 is turned on, the first high side control signal SH1 is at a low level, and the first high side transistor MH1 is turned off. During this time, the first driving capacitor C1 is charged until the first terminal voltage Vc1 reaches about the breakdown voltage Vz of the first Zener diode 58. When the first switch transistor 68 is turned off, a voltage higher than the emitter voltage by the first terminal voltage Vc1 is applied to the gate of the first high-side transistor MH1, and the first high-side transistor MH1 is turned on.

  The second bootstrap circuit B2 has a circuit topology similar to that of the first bootstrap circuit B1. That is, the first BS resistor 52, the first BS diode 54, the second BS resistor 56, the first Zener diode 58, the first npn type bipolar transistor 60, the first pnp type bipolar transistor 62, the third BS resistor 64, the fourth BS resistor 66, the first switch The transistor 68 includes a fifth BS resistor 70, a second BS diode 72, a sixth BS resistor 74, a second Zener diode 76, a second npn bipolar transistor 78, a second pnp bipolar transistor 80, a seventh BS resistor 82, an eighth BS resistor 84, respectively. This corresponds to the second switch transistor 86. Further, the second driving capacitor C2 and the first driving capacitor C1 also correspond.

The current detection resistor R1 is provided on the path of the lamp current IL flowing through the discharge lamp 4. In the circuit of FIG. 1, the current detection resistor R <b> 1 is provided on a ground wiring that connects the DC / DC converter CONV and the H bridge circuit 30. In the first state φ1, the lamp current IL flows to the discharge lamp 4 in the first polarity (rightward in FIG. 1), and in the second state φ2, the lamp current IL flows in the second polarity (leftward in FIG. 1). Flowing. The current detecting resistor R1, the first state .phi.1, in each of the second state .phi.2, a voltage drop proportional to the lamp current IL (referred to as a current detecting signal S _IL) is generated. The current detection signal S _IL is input to the control circuit 10.

  The starter circuit 20 is provided to break down the discharge lamp 4. The starter circuit 20 generates a high voltage pulse (for example, 20 kV) when starting the discharge lamp 4 and applies it to one end P <b> 1 of the discharge lamp 4. As a result, the discharge lamp 4 breaks down and discharge starts.

  The control circuit 10 includes a function IC (Integrated Circuit) that controls the entire discharge lamp lighting circuit 100, controls the operation sequence of the discharge lamp lighting circuit 100, and adjusts the electric power supplied to the discharge lamp 4. The on / off control of the first high-side transistor MH1, the second high-side transistor MH2, the first low-side transistor ML1, and the second low-side transistor ML2 is controlled. The control circuit 10 acquires information on the power supply voltage Vo from the output of the DC / DC converter CONV.

  The control circuit 10 performs control for stopping the supply of power to the discharge lamp 4 when an abnormality of the discharge lamp 4 is detected. Here, the abnormality of the discharge lamp 4 includes a ground fault, a short circuit, and an open circuit as described above. When the discharge lamp 4 is short-circuited, the power supply voltage Vo decreases. When the discharge lamp 4 is opened, the lamp current IL decreases. When the discharge lamp 4 is grounded, the power supply voltage Vo is lowered and the lamp current IL is also lowered.

The control circuit 10 includes a bridge control unit 40 described later with reference to FIG. Regarding the abnormality of the discharge lamp, the control circuit 10 realizes the following three functions by the bridge controller 40:
1. The bridge control unit 40 monitors the power supply voltage Vo and the lamp current IL, and detects an abnormality of the discharge lamp if the abnormal state of the discharge lamp continues longer than a predetermined abnormality detection period PT1. When the abnormality of the discharge lamp is detected, the bridge control unit 40 performs control for stopping the supply of the drive voltage VL to the discharge lamp 4.
The abnormal state of the discharge lamp is a state in which the parameters of the discharge lamp lighting circuit 100 satisfy a predetermined condition due to the abnormality of the discharge lamp, and it corresponds to each kind of abnormality of the discharge lamp. The conditions to do are determined. If the discharge lamp is short-circuited, a decrease in the lamp current IL is not observed, but if the state where the power supply voltage Vo is lower than the predetermined short-circuit detection voltage Vsh continues longer than the abnormality detection period PT1, it is determined that the short-circuit is occurring.
The short circuit detection voltage Vsh is a voltage that is low enough to determine that the discharge lamp 4 is in a shorted state.

2. When the state of the power supply voltage Vo being lower than the short circuit detection voltage Vsh continues longer than the short circuit detection period PT2 shorter than the abnormality detection period PT1, the bridge control unit 40 does not decrease the lamp current IL. As control for stopping the supply of the drive voltage VL, both the first high-side transistor MH1 and the second high-side transistor MH2 are turned off. Thereafter, as long as the power supply voltage Vo is lower than the short-circuit detection voltage Vsh, the bridge control unit 40 includes both off periods PT3 in which both the first high-side transistor MH1 and the second high-side transistor MH2 are turned off, and an H-bridge circuit. The normal operation period PT4 in which 30 is normally operated is alternately repeated.
The normal operation period PT4 is set shorter than half of the lighting cycle T1. Here, in particular, the length of the normal operation period PT4 is set to 0.8 ms, which is a value smaller than half of the lighting cycle T1 (3.2 ms).
Further, the length of both off periods PT3 is set longer than the length of the normal operation period PT4. Here, in particular, the length of both off periods PT3 is set to 6.4 ms (= 0.8 × 8) which is an integral multiple of the length (0.8 ms) of the normal operation period PT4.

The reason why the both off periods PT3 and the normal operation period PT4 are repeated in this way is as follows. The state where the power supply voltage Vo is lower than the short circuit detection voltage Vsh continues for a longer period than the short circuit detection period PT2, and after both the first high side transistor MH1 and the second high side transistor MH2 are turned off, the power supply voltage Vo is After a while, it becomes higher than the short circuit detection voltage Vsh. Then, the control circuit 10 determines that the abnormal state has been resolved and starts normal operation. However, actually, since the discharge lamp 4 remains short-circuited, the power supply voltage Vo becomes lower than the short-circuit detection voltage Vsh again, and both the first high-side transistor MH1 and the second high-side transistor MH2 are turned off. Depending on the settings of the abnormality detection period PT1 and the short circuit detection period PT2, the state where the power supply voltage Vo is lower than the short circuit detection voltage Vsh does not last longer than the abnormality detection period PT1 in this cycle. Therefore, there is a case where a short circuit of the discharge lamp 4 cannot be detected any time.
Therefore, in the discharge lamp lighting circuit 100 according to the present embodiment, both the off period PT3 and the normal operation period PT4 are repeated. Unless the short circuit of the discharge lamp 4 is eliminated, the power supply voltage Vo decreases due to the short circuit of the discharge lamp 4 in the normal operation period PT4. Therefore, the state where the power supply voltage Vo is lower than the short circuit detection voltage Vsh continues longer than the abnormality detection period PT1, and the short circuit of the discharge lamp 4 can be detected.

  3. The bridge control unit 40 restores the H bridge circuit 30 to a normal operation on condition that the power supply voltage Vo in the normal operation period PT4 is higher than the short circuit detection voltage Vsh.

  In both off periods PT3, both the first low side transistor ML1 and the second low side transistor ML2 are also turned off. That is, in both off periods PT3, the H bridge circuit 30 is placed in a reset state in which all the transistors related to the discharge lamp drive are turned off. Thereby, the discharge lamp 4 in which the short circuit has occurred and the other part of the discharge lamp lighting circuit 100 can be electrically separated.

FIG. 2 is a circuit diagram showing a configuration of the bridge control unit 40. The bridge control unit 40 includes a signal processing unit 42, a drive signal generation unit 44, an operation stop unit 46, and an abnormality detection unit 48.
The signal processing unit 42 receives the power information of the voltage Vo and the current detection signal S _IL, the power supply voltage Vo and the lamp current IL is determined whether or not the condition indicating an abnormal state of the discharge lamp 4. Bridge control unit 40, a result of the determination, the power supply voltage Vo in a steady lighting state is when asserted below a predetermined low tube voltage, for example 31V (e.g., a high level) generates a low tube voltage signals S _VL To do. As a result of the determination, the bridge control unit 40 generates a high tube voltage signal S _VH that is asserted (for example, becomes high level) when the power supply voltage Vo becomes higher than a predetermined high tube voltage, for example, 69 V, in a steady lighting state. To do. After the breakdown of the discharge lamp 4, the bridge controller 40 generates an open signal Sop that is asserted (for example, becomes high level) when the lamp current IL becomes smaller than a predetermined open threshold current, for example, 0.3A. To do. After the breakdown of the discharge lamp 4, the bridge control unit 40 generates a short circuit signal Ssh that is asserted (for example, becomes high level) when the power supply voltage Vo becomes lower than the short circuit detection voltage Vsh, for example, 18V.

  A known signal processing technique is used for signal processing for realizing the above-described signal generation in the signal processing unit 42. As an example, a configuration including a comparator that compares a voltage of an input signal with a reference voltage may be used.

  The drive signal generator 44 generates and outputs a first base signal SH1 ', a second base signal SH2', a first low side control signal SL1, and a second low side control signal SL2. The drive signal generator 44 receives the reset signal Srst from the abnormality detector 48. The drive signal generation unit 44 is reset when information indicating reset, for example, a rising edge appears in the reset signal Srst. When the drive signal generation unit 44 is reset, the drive signal generation unit 44 puts the H bridge circuit 30 in the reset state during both off periods PT3. During this time, the rising edge appearing in the reset signal Srst is ignored. When both off periods PT3 have elapsed after the drive signal generator 44 has been reset, the drive signal generator 44 drives the H-bridge circuit 30 again as usual.

The abnormality detection unit 48 receives the low tube voltage signal S _VL , the high tube voltage signal S _VH , the open signal Sop, and the short circuit signal Ssh, and detects an abnormality of the discharge lamp 4. The abnormality detection unit 48 is asserted when any one of the low tube voltage signal S _VL , the high tube voltage signal S _VH , and the open signal Sop becomes a high level longer than the predetermined first abnormality detection period PT5 (for example, A stop signal Sst (which becomes high level) is generated. The abnormality detection unit 48 asserts the stop signal Sst (for example, sets it to the high level) when the short circuit signal Ssh becomes a high level longer than the second abnormality detection period PT6 shorter than the first abnormality detection period PT5.

When the short circuit signal Ssh becomes a high level for a longer time than the short circuit detection period PT2, the abnormality detection unit 48 generates a reset signal Srst indicating a rising edge with a short circuit period T2 equal to the length of the normal operation period PT4. Further, when the short circuit is canceled and the short circuit signal Ssh becomes a low level longer than the short circuit detection period PT2, the level of the reset signal Srst is fixed.
In addition, when both the open signal Sop and the short circuit signal Ssh are at a high level, it can be interpreted that the discharge lamp 4 is in a ground fault state. Also in this case, the abnormality detector 48 generates a rising edge in the reset signal Srst with a short-circuit period T2 equal to the length of the normal operation period PT4.

The abnormality detecting unit 48 includes a first AND gate AND1, a second AND gate AND2, a first OR gate OR1, a second OR gate OR2, a third OR gate OR3, a first filter FIL1, a second filter FIL2, a D flip-flop FF, and a counter CNT. Including.
The first OR gate OR1 outputs a logical sum of the low tube voltage signal S _VL , the high tube voltage signal S _VH , the open signal Sop, and the short circuit signal Ssh to the first filter FIL1. That is, if any one of the low tube voltage signal S _VL , the high tube voltage signal S _VH , the open signal Sop, and the short circuit signal Ssh becomes high level, the first signal S1 that becomes high level is input to the first filter FIL1.

  The first filter FIL1 is provided to remove the influence on the abnormality detection of the discharge lamp due to instantaneous noise that may occur in the circuit. The first filter FIL1 keeps the first signal S1 at the high level for a predetermined first filter constant TF1, for example, a constant in the range of 1.6 ms to 3.2 ms after the first signal S1 becomes the high level. And the first filter signal Sf1 that is negated (for example, becomes low level) is generated. Thereby, even if the input signal of the first OR gate OR1 is disturbed by noise having a time width shorter than the first filter constant TF1, it can be prevented that it is erroneously detected as an abnormality of the discharge lamp 4.

  The second filter FIL2 is also provided for the same purpose as the first filter FIL1. The second filter FIL2 is asserted when the short circuit signal Ssh keeps the high level for a second filter constant TF2, which is equal to the length of the short circuit detection period PT2, for example, 1.6 ms after the short circuit signal Ssh becomes the high level. A second filter signal Sf2 (for example, at a high level) is generated. Thereby, even if the short circuit signal Ssh is disturbed by noise having a shorter time width than the second filter constant TF2, it can be prevented from being erroneously detected as a short circuit of the discharge lamp 4. The second filter FIL2 negates (sets to the low level) the second filter signal Sf2 if the short circuit signal Ssh continues to keep the low level for the second filter constant TF2 after the short circuit signal Ssh becomes the low level. .

The first AND gate AND1 outputs a second signal S2 that is a logical product of the open signal Sop and the short circuit signal Ssh in order to detect a ground fault.
The second OR gate OR2 outputs a third signal S3 that is a logical sum of the second filter signal Sf2 and the second signal S2 to the reset terminal of the D flip-flop FF.
The clock signal S _CLK generated in the abnormality detection unit 48 or supplied from the outside of the abnormality detection unit 48 is input to the clock terminal of the D flip-flop FF. The clock signal S _CLK is a rectangular wave having a period of 0.4 ms which is a half of a predetermined clock period T3, for example, the length of the normal operation period PT4 (= short circuit period T2 = 0.8 ms).

The reset signal Srst output from the inverting output terminal of the D flip-flop FF is input to the data terminal of the D flip-flop FF. When the third signal S3 is at a low level, the D flip-flop FF is reset and the reset signal Srst is maintained at a high level. Further, the count acceleration signal Sup output from the non-inverting output terminal of the D flip-flop FF is kept at a low level. When the third signal S3 is at the high level, reset is released the D flip-flop FF, both the count up speed signal Sup and a reset signal Srst, the edge is synchronized with the clock signal S _CLK, the period of the clock cycle T3 2 A rectangular wave having a double, that is, a short-circuit period T2. The phases of the count acceleration signal Sup and the reset signal Srst are shifted by 180 degrees.

  The counter CNT receives the first filter signal Sf1 and the count acceleration signal Sup. The counter CNT changes to a high level when the first filter signal Sf1 maintains a low level during a period in which the first filter constant TF1 is subtracted from the first abnormality detection period PT5 after the first filter signal Sf1 becomes a low level. The first abnormal signal Sab1 is generated. The length of the first abnormality detection period PT5 is set to 500 ms.

  When a rectangular wave having a short circuit period T2 appears in the count acceleration signal Sup, the counter CNT uses the rectangular wave to increase the count. A rectangular wave appears in the count acceleration signal Sup when the output of the second OR gate OR2 is at a high level, that is, in the case of a short circuit or a ground fault. Therefore, in the case of a short circuit or a ground fault, the count in the counter CNT is increased. In this case, the counter CNT is high when the first filter signal Sf1 is maintained at the low level during the period obtained by subtracting the first filter constant TF1 from the second abnormality detection period PT6 after the first filter signal Sf1 is at the low level. A second abnormal signal Sab2 that is level is generated. The length of the second abnormality detection period PT6 is set to 100 ms.

  The second AND gate AND2 outputs a signal that is a logical product of the second abnormal signal Sab2 and the reset signal Srst to the third OR gate OR3. The third OR gate OR3 outputs the logical sum of the output signal of the second AND gate AND2 and the first abnormality signal Sab1 to the operation stop unit 46 as the stop signal Sst. As a result, the stop signal Sst becomes a high level if any one of the low tube voltage state, the high tube voltage state, and the open state continues longer than the first abnormality detection period PT5. Further, the stop signal Sst becomes a high level when the short circuit state or the ground fault state continues longer than the second abnormality detection period PT6.

  The operation stop unit 46 receives the stop signal Sst and performs control for stopping the supply of the drive voltage VL to the discharge lamp 4 when the stop signal Sst becomes a high level. The control for stopping the supply of the drive voltage VL includes, for example, placing the H bridge circuit 30 in a reset state and turning off the switching element M1 of the DC / DC converter CONV.

FIG. 3 is a time chart showing a waveform of a signal included in the abnormality detection unit 48 of FIG. 2 when a short circuit of the discharge lamp 4 occurs in the steady lighting state. The vertical and horizontal axes in FIG. 3 are enlarged or reduced as appropriate for easy understanding, and each waveform shown is also simplified for easy understanding. FIG. 3 shows, in order from the top, the short circuit signal Ssh, the second filter signal Sf2, the clock signal S _CLK , the reset signal Srst, the first base signal SH1 ′, and the second base signal SH2 ′.

It is assumed that a short circuit occurs in the discharge lamp 4 and the power supply voltage Vo falls below the short circuit detection voltage Vsh at time t1. Then, the short circuit signal Ssh becomes a high level.
At time t2 after the second filter constant TF2 from time t1, the second filter signal Sf2 that is the output of the second filter FIL2 becomes high level. Then, the reset of the D flip-flop FF is released, and the D flip-flop FF generates a rectangular wave with a period of 0.8 ms in the reset signal Srst. This rectangular wave is synchronized with the clock signal _SCLK at the edge position.
At time t3 when a rising edge first appears in the reset signal Srst after time t2, the drive signal generation unit 44 that has been driving corresponding to the first state φ1 is reset. Then, both the first base signal SH1 ′ and the second base signal SH2 ′ are at a high level, and both the first high side transistor MH1 and the second high side transistor MH2 are turned off.

In both off periods PT3 starting from time t3, both the first base signal SH1 ′ and the second base signal SH2 ′ are maintained at a high level. At time t4 after 6.4 ms, which is the length of both off periods PT3 from time t3, the drive signal generation unit 44 starts normal driving. Here, it is assumed that driving corresponding to the first state φ1 is started. Therefore, at time t4, the first base signal SH1 ′ becomes a low level, and the first high-side transistor MH1 is turned on.
Here, when the short-circuit state of the discharge lamp 4 has not been eliminated, the power supply voltage Vo decreases and the short-circuit signal Ssh remains at the high level. Therefore, at time t5 when the rising edge first appears in the reset signal Srst after time t4, the drive signal generation unit 44 is reset again. The period between the time t4 and the time t5 is the normal operation period PT4, and the length is 0.8 ms.

  The above is the configuration of the discharge lamp lighting circuit 100. Next, the operation will be described according to the sequence. FIG. 4 is a time chart showing the operating state of the discharge lamp lighting circuit 100. The vertical and horizontal axes in FIG. 4 are enlarged or reduced as appropriate for easy understanding, and the waveforms shown are also simplified for easy understanding.

1. When the user turns on the power switch 8 at power-on time t1, the discharge lamp lighting circuit 100 is activated. The control circuit 10 activates the DC / DC converter CONV and puts the H bridge circuit 30 in the reset state. The discharge lamp lighting circuit 100 boosts and stabilizes the battery voltage Vbat to a predetermined high voltage (400V).

2. At the breakdown time t2, the starter circuit 20 receives the power supply voltage Vo of 400 V generated by the DC / DC converter CONV and generates a high voltage pulse of 20 kV or more. As a result, the driving voltage VL of the discharge lamp 4 rises to about 15 kV, breaks down, and glow discharge starts.

3. DC period φ _DC
After the breakdown, the control circuit 10 first controls the lamp current IL to flow in the direction of the first polarity for about 10 ms in the first state φ1. Next, the control circuit 10 switches to the second state φ2 and performs control to flow the lamp current IL in the direction of the second polarity for approximately 10 ms. It will be referred to this period as the DC period φ _DC. In this DC period φ _DC , the glow discharge is shifted to the arc discharge.

When the DC period phi _DC termination to the arc discharge is stabilized, the control circuit 10 controls the H-bridge circuit 30 repeats the first state φ1 alternately and the second state φ2 at the lighting cycle T1.

5A and 5B are time charts showing an operation state after the DC period φ _DC of the discharge lamp lighting circuit 100. FIG. The vertical and horizontal axes in FIGS. 5 (a) and 5 (b) are enlarged or reduced as appropriate for easy understanding, and each waveform shown is also simplified for easy understanding. Yes. FIGS. 5A and 5B show waveforms during the run-up process and steady lighting, respectively.

4). As the run-up arc discharge grows, the light output of the discharge lamp 4 increases. The rise of the optical output is determined by the standard, and the control circuit 10 monitors the power supply voltage Vo and the lamp current IL so as to obtain an optical output (electric power) that matches the standard, and by feedback, the control circuit 10 Adjust the on / off duty ratio. In order to rapidly increase the light output of the discharge lamp 4 during the run-up period, the discharge lamp lighting circuit 100 temporarily supplies overpower higher than the rated power, and then the lamp voltage is 45 V and the lamp current IL is 0.8 A. Stabilized to close to the rated power (35W). (Fig. 5 (a))

5). Steady lighting After the run-up process, when the light output of the discharge lamp 4 is stabilized, the power supplied to the discharge lamp 4 is stabilized at a rated value of 35 W (FIG. 5B). Note that the waveforms of the drive voltage VL and the lamp current IL shown in FIGS. 5A and 5B are simplified for easy viewing, and actually have a frequency of 250 Hz to 750 Hz. .

  Consider a case where the user turns on the power switch 8 to activate the discharge lamp lighting circuit 100 in a state where a short circuit has occurred in the discharge lamp 4. FIG. 6 is a time chart showing the operating state of the discharge lamp lighting circuit 100 in this case. The vertical axis and the horizontal axis in FIG. 6 are appropriately enlarged or reduced for easy understanding, and each waveform shown is also simplified for easy understanding. FIG. 6 shows, in order from the top, the power supply voltage Vo, the first terminal voltage Vc1, the second base signal SH2 ', the first base signal SH1', the first low side control signal SL1, and the second low side control signal SL2.

At time t1, the power switch 8 is turned on. Shortly thereafter, the power supply voltage Vo reaches 400V. Since the H-bridge circuit 30 is placed in the reset state, the first terminal voltage Vc1 of the first driving capacitor C1 is charged to about 20V that is the breakdown voltage Vz.
The first high-side transistor MH1 and the second low-side transistor ML2 are turned on to start the breakdown at time t2, but since the discharge lamp 4 is short-circuited, the power supply voltage Vo is immediately reduced to the short-circuit detection voltage Vsh. Is less than 18V. Then, the second filter constant TF2 elapses from time t2, and the H bridge circuit 30 is placed in the reset state at time t3 after elapse of the short circuit period T2. Then, the power supply voltage Vo recovers to 400V, and the first terminal voltage Vc1 also approaches 20V.
At time t4 after 6.4 ms, which is the length of both off periods PT3 from time t3, normal operation is started again, and the first high-side transistor MH1 and the second low-side transistor ML2 are turned on. If the short circuit has not been eliminated, the H bridge circuit 30 is placed in the reset state again at time t5 after the short circuit period T2 has elapsed from time t4.
Thereafter, both the off-period PT3 and the normal operation period PT4 continue until the second abnormality detection period PT6 elapses unless the short circuit is eliminated. While this repetition continues, the first terminal voltage Vc1 is maintained at about 20V, and the first high-side transistor MH1 is normally turned on / off.

  The above is the operation of the discharge lamp lighting circuit 100 according to the embodiment. The discharge lamp lighting circuit 100 has the following advantages over the conventional discharge lamp lighting circuit.

  (1) According to the discharge lamp lighting circuit 100 according to the present embodiment, the lamp current IL does not decrease, but the period in which the power supply voltage Vo is lower than the short circuit detection voltage Vsh is longer than the second abnormality detection period PT6. Control for detecting the short-circuit of the discharge lamp 4 and stopping the operation is performed. In addition, when the period during which the power supply voltage Vo falls below the short circuit detection voltage Vsh is longer than the short circuit detection period PT2, both the first high side transistor MH1 and the second high side transistor MH2 are turned off. When the discharge lamp 4 is short-circuited, the power supply voltage Vo is lowered, and accordingly, the voltage charged in the driving capacitor of the high side transistor is lowered. However, according to the discharge lamp lighting circuit 100, the power supply voltage Vo is recovered by turning off both the first high-side transistor MH1 and the second high-side transistor MH2, and the driving capacitor for the high-side transistor is sufficiently charged again. It becomes possible. Thereby, it is possible to avoid the on / off of the high side transistor from becoming unstable due to a decrease in the voltage across the driving capacitor until the second abnormality detection period PT6 elapses.

  In a conventional discharge lamp lighting circuit, when a high-side transistor, which is an IGBT, is used in an active region, heat generation in the high-side transistor becomes large, and a problem may occur in the transistor itself. Therefore, as described above, it is particularly beneficial to stably turn on and off the high-side transistor even when a short circuit is caused by the discharge lamp lighting circuit 100 according to the present embodiment.

  In the conventional discharge lamp lighting circuit, the power supply voltage Vo and the lamp current IL may be stabilized in a state where the high side transistor is used in the active region. In this case, if the power supply voltage Vo is stabilized at a value higher than the short circuit detection voltage Vsh, it is not preferable because a short circuit of the discharge lamp cannot be detected. Therefore, as described above, it is particularly beneficial to stably turn on and off the high-side transistor even when a short circuit is caused by the discharge lamp lighting circuit 100 according to the present embodiment.

(2) If the short circuit of the discharge lamp 4 is caused by a temporary factor and the short circuit is resolved before the second abnormality detection period PT6 has elapsed, in the normal operation period PT4 after the cancellation, The power supply voltage Vo increases. Since the power supply voltage Vo naturally increases in both off periods PT3, the power supply voltage Vo becomes higher than the short circuit detection voltage Vsh in a normal operation period PT4 after the short circuit is eliminated.
Here, in the discharge lamp lighting circuit 100 according to the present embodiment, the H bridge circuit 30 is returned to the normal operation under one condition that the power supply voltage Vo in the normal operation period PT4 is higher than the short circuit detection voltage Vsh. Therefore, when the short circuit of the discharge lamp 4 is resolved before the second abnormality detection period PT6 elapses, the discharge lamp 4 can be continuously driven as usual.

  In particular, when the discharge lamp 4 is short-circuited due to an external and temporary factor such as noise, the short-circuit is also eliminated when the factor is eliminated. In the discharge lamp lighting circuit 100 according to the present embodiment, such a case can be excluded from detection of a short circuit as not being a substantial short circuit that requires replacement of the discharge lamp 4.

  (3) When the short-circuited discharge lamp 4 is driven as usual, a large short-circuit current flows through the transistor in which the H-bridge circuit 30 is turned on. Therefore, in the discharge lamp lighting circuit 100 according to the present embodiment, the normal operation period PT4 is set to be shorter than half of the lighting cycle T1. This prevents the large short-circuit current from continuing to flow through one transistor for a long time.

  (4) In the discharge lamp lighting circuit 100 according to the present embodiment, both the off periods PT3 are set longer than the normal operation period PT4. As a result, the transistor that generates heat due to the short-circuit current is cooled during both longer off periods PT3. As a result, the heat generation of the entire H-bridge circuit 30 from when a short circuit is detected to when the operation stops can be reduced, and the possibility of a malfunction in the transistor can also be reduced.

  (5) Further, the second abnormality detection period PT6 related to the short circuit or the ground fault is set shorter than the first abnormality detection period PT5 related to other abnormalities. Thereby, in the case of a short circuit or a ground fault in which a large short circuit current, a ground fault current can flow in the transistor of the H bridge circuit 30, the operation of the discharge lamp lighting circuit 100 can be stopped more quickly. As a result, the possibility that the transistor is defective can be reduced.

  The present invention has been described above based on the embodiment. These embodiments are exemplifications, and it is understood by those skilled in the art that various modifications can be made to combinations of each component and each processing process, and such modifications are also within the scope of the present invention. .

In the embodiment, the case where the short-circuit detection voltage Vsh is a threshold voltage that is low enough to determine that the discharge lamp 4 is in a short-circuited state has been described, but is not limited thereto. For example, the short circuit detection voltage Vsh may be determined based on the threshold voltage of the high side transistor of the H bridge circuit 30, for example, the gate-emitter voltage. In this case, a sufficient gate-emitter voltage can be more reliably supplied to the high-side transistor.
Further, the short circuit detection voltage Vsh may be set higher than the gate-emitter voltage. In this case, the both-off period PT3 can be set by detecting a short circuit state before the power supply voltage Vo falls below the gate-emitter voltage. Thereby, the fall of the voltage of the drive capacitor can be prevented more suitably.

  In the embodiment, the case where the H bridge circuit 30 is placed in the reset state in both off periods PT3 has been described, but the present invention is not limited to this. For example, both the first low-side transistor ML1 and the second low-side transistor ML2 may be turned on in both off periods PT3. In this case, since both ends of the short-circuited discharge lamp 4 can be grounded in both off periods PT3, the influence of the short-circuit of the discharge lamp 4 on other parts of the discharge lamp lighting circuit 100 can be reduced.

  A microcomputer may be used for the control circuit of the discharge lamp lighting circuit according to the embodiment or a part thereof.

  In the embodiment, a discharge lamp lighting circuit for driving a vehicle discharge lamp has been described as an example. However, the application of the present invention is not limited to this, and the discharge lamp lighting circuit has a function of detecting an abnormality of the discharge lamp. Widely applicable.

  In the circuit described in the embodiment, the setting of the high level and low level logic values of the signal is an example, and can be freely changed by appropriately inverting it with an inverter or the like.

  In the embodiment, the case where the four transistors of the H-bridge circuit 30 are IGBTs has been described, but the present invention is not limited to this. These transistors may all be N-channel MOSFETs or may be bipolar transistors.

  In the embodiment, when the lamp current IL becomes smaller than the open-circuit threshold current and the power supply voltage Vo becomes lower than the short-circuit detection voltage Vsh, a ground fault occurs in the discharge lamp 4, and the lamp current IL is larger than the open-circuit threshold current. However, the case where the discharge lamp 4 is short-circuited when the power supply voltage Vo becomes lower than the short-circuit detection voltage Vsh has been described, but the present invention is not limited thereto. For example, when the power supply voltage Vo falls below a predetermined short-circuit ground fault detection voltage, for example, 18 V, it may be either a short circuit or a ground fault of the discharge lamp.

  In the embodiment, the case where the second abnormality detection period PT6 is shorter than the first abnormality detection period PT5 has been described. However, the present invention is not limited to this. For example, the length of the first abnormality detection period PT5 may be set equal to the length of the second abnormality detection period PT6.

  Although the present invention has been described using specific words and phrases based on the embodiments, the embodiments are merely illustrative of the principles and applications of the present invention, and the embodiments are defined in the claims. Many modifications and arrangements can be made without departing from the spirit of the present invention.

  4 discharge lamp, 6 onboard battery, 8 power switch, 10 control circuit, 20 starter circuit, 30 H bridge circuit, 40 bridge control unit, 42 signal processing unit, 44 drive signal generation unit, 46 operation stop unit, 48 abnormality detection unit 100 Discharge lamp lighting circuit, Vo power supply voltage.

Claims (5)

An H-bridge circuit including two sets of a high-side transistor and a low-side transistor placed in series between a fixed voltage and a DC power supply voltage, and supplying an AC driving voltage to a discharge lamp to be driven;
A control unit for controlling on / off of the two sets of high-side transistors and low-side transistors,
Two high-side transistors included in the H-bridge circuit are turned on using the power supply voltage,
The control unit performs control for stopping the supply of the drive voltage when the abnormal state of the discharge lamp continues longer than a predetermined abnormality detection period, and the power supply voltage is a predetermined short-circuit detection voltage in the abnormal state. When the lower state continues longer than the short-circuit detection period shorter than the abnormality detection period, the two high-side transistors included in the H-bridge circuit are turned off as control for stopping the supply of the drive voltage. A discharge lamp lighting circuit.   When the state where the power supply voltage is lower than the short-circuit detection voltage continues longer than the short-circuit detection period, the control unit performs a normal operation period in which the H-bridge circuit is normally operated and two high-sides included in the H-bridge circuit. The discharge lamp lighting circuit according to claim 1, wherein both off periods for turning off the transistor are repeated.   3. The control unit according to claim 2, wherein the control unit returns the H-bridge circuit to a normal operation on condition that the power supply voltage in the normal operation period is higher than the short-circuit detection voltage. Discharge lamp lighting circuit.   4. The discharge lamp lighting circuit according to claim 2, wherein the normal operation period is set to be shorter than a half cycle of the AC drive voltage.   The discharge lamp lighting circuit according to any one of claims 2 to 4, wherein the both off periods are set longer than the normal operation period.

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