JP2010204262A - Display processing device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display processing device that outputs videos in a plurality of display devices respectively with one display unit and reduces load in a bus band accompanying data copy on a frame memory without having restriction on data arrangement on the frame memory. <P>SOLUTION: The display processing device processing to display the same or different images in a plurality of displays of the same resolution includes a image acquisition section to acquire image data which is assigned to each of a plurality of layers; a plurality of superposing sections to superpose the image data of at least one layer among the image data acquired by the image acquisition section; a layer composing section to output the superposed result from at least one superposing section among the plurality of superposing sections, as superposed image data which is displayed in each of the plurality of displays by the layer composing section; and a selection instructing section to perform instruction related to selection of the superposed image data output by the layer composing section. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a display processing apparatus that performs image display control for each of a plurality of display devices.

  As shown in FIGS. 9 and 10, the display control device disclosed in Patent Literature 1 arranges frame data to be displayed on two different displays side by side on a frame memory. Further, the display control device other than the above recognizes the horizontal separation position on the frame memory by setting the display size in the built-in line buffer. According to the display control device, different images can be displayed on two displays having the same resolution.

  In the technology disclosed in Non-Patent Document 1, two images can be output to two displays by using two display processing devices.

JP-A-2005-292677 LCD / CRT 2D Graphic Subsystem Data Book, Version0.08, May26,2000 (nVIDIA)

  However, in the display processing apparatus disclosed in Patent Document 1 described above, it is necessary to arrange the display data on the frame memory side by side in the horizontal direction. For this reason, when the original data to be displayed is an external video such as a DVD, TV broadcast, camera video, etc., in order to display these videos simultaneously on two displays, a frame for displaying on one display is displayed. It is necessary to copy the data once taken into the memory to the corresponding area on the frame memory in order to take in the data to be displayed on the other display. Thus, in order to display different images on the two displays, there is a restriction on the data arrangement on the frame memory. Further, when data for display on one display captured in the frame memory is copied to a corresponding area on the frame memory in order to display another video on the other display, data transfer occurs. At this time, the transfer bandwidth of the memory and the internal bus is occupied.

  An object of the present invention is to provide a bus for data copying on a frame memory in a state in which video can be output to each of a plurality of display devices by one display unit and there is no restriction on data arrangement on the frame memory. It is an object of the present invention to provide a display processing device capable of reducing a load in a band.

  The present invention is a display processing device that performs processing to display the same or different images on a plurality of displays having the same resolution, the image acquisition unit acquiring image data assigned to each of a plurality of layers, and the image acquisition unit Includes a plurality of superimposing units that superimpose image data of at least one layer, and the layer synthesis unit displays the superimposing result of at least one superimposing unit among the plurality of superimposing units. There is provided a display processing apparatus including a layer synthesis unit that outputs as superimposed image data to be displayed on each of the displays, and a selection instruction unit that gives an instruction related to selection of superimposed image data output from the layer synthesis unit. As a result, in the state where there is no restriction on the data arrangement on the frame memory, the same or different from one display processing device to a plurality of display devices of the same resolution without reducing the load in the bus bandwidth accompanying the data copy on the frame memory Different images can be output.

  The display processing device generates different timing control signals and controls each display with the same vertical synchronization period and horizontal synchronization period for the plurality of displays having different specifications other than resolution. A display timing control unit for outputting is provided. As a result, the timing control signal can be output independently to a plurality of displays operating with different timing control signals with the same horizontal resolution period and vertical period and resolution.

  In the display processing device, the resolution of at least one of the plurality of displays is different from that of the other display, and the size of at least one image indicated by the superimposed image data output from the layer combining unit is reduced. Reducer for processing superimposed image data representing an image, and display timing control for generating different timing control signals and outputting the same to each display in order to control each display having different resolutions in the same vertical synchronization period and different horizontal synchronization periods A section. Thereby, the same or different images can be output to a plurality of displays having the same vertical synchronization period but different resolutions.

  In the display processing device, the display timing control unit includes a frequency dividing unit that generates the timing control signal including a dot clock set in a corresponding display and divides the dot clock having a predetermined frequency. As a result, two dot clocks can be generated from one dot clock source.

  In the display processing device, the dividing unit divides a dot clock set in a display that displays an image that is not reduced by the reducing unit, and displays the image that is reduced by the reducing unit. A set dot clock may be output.

  The present invention is an in-vehicle driving support system including the display processing device, wherein the first display is attached to a position such as a center console of an automobile that can be seen when the driver is facing forward. Attach the first display to a position that can be seen by the driver when visually checking the back, such as the center of the ceiling of the car, and while looking directly at the back when the driver moves the car backward, An in-vehicle driving support system that displays a camera image attached to the rear of a vehicle on a display is provided. As a result, it is possible to simultaneously confirm the blind spot photographed by the camera attached to the rear of the vehicle without changing the direction of the body at the same time as the rearward confirmation by visual observation, and it is possible to reduce the burden of driver safety confirmation It becomes.

  According to the display processing device of the present invention, video can be output to each of a plurality of display devices by one display unit, and there is no restriction on the data arrangement on the frame memory, and on the frame memory. It is possible to reduce the load on the bus band accompanying data copying. In addition, it is possible to reduce the load when confirming the driver's safety in an automobile.

  Embodiments of the present invention will be described below with reference to the drawings.

<Embodiment 1>
FIG. 1 is a block diagram showing an apparatus 111 with a display function including a display processing apparatus 100 according to Embodiment 1 of the present invention. As shown in the figure, a display processing apparatus 100 connected to two displays (displays A and B) 112 and 113 includes an internal bus interface 101, a buffer control unit 102, a line buffer 103, and an image quality adjustment unit 104. A layer synthesis unit 105, a display interface unit (display IF unit) 106, a display timing control unit 107, and a display timing generation unit 108.

  The line buffer 103 stores data on the same line of a plurality of images to be displayed. The internal bus interface 101 reads the required number of image data stored in the memory 114 by the image input unit 109 based on an instruction from the buffer control unit 102 and stores the image data in the line buffer 103. The image input unit 109 has a video input function for capturing camera images and television images input from the outside, and a drawing function for drawing graphics and characters. In addition to these functions, the image input unit 109 may include all functions for generating data that can be displayed on a display, such as still images and moving images.

  The image quality adjustment unit 104 acquires data of the same line of the image stored in the line buffer 103. The image quality adjustment unit 104 performs image scale change processing, color and brightness adjustment such as gamma correction and luminance correction, noise removal, and image edge processing. However, these image quality adjustment processes are not necessarily performed depending on the type of image.

  Each image output from the image quality adjustment unit 104 is input to the layer synthesis unit 105 in order to perform a superimposition process in a preset order. The layer synthesizing unit 105 performs layer superimposition processing on each image to generate the same or different image data to be output to the two displays 112 and 113. The image data for each display generated by the layer synthesis unit 105 is sent to the displays 112 and 113 via the display interface unit 106, and a timing control signal for controlling the display timing of each display output from the display timing generation unit 108. Is output together.

  Hereinafter, the layer synthesis unit 105 will be described with reference to FIG. FIG. 2 is a block diagram showing an internal configuration of the layer synthesis unit 105. As illustrated in FIG. 2, the layer synthesis unit 105 includes a tatami order control unit 200, superimposing units 201, 202, and 203, selectors 204 and 205, and a display data selector 206.

  The superimposition order control unit 200 assigns the input image data 1, 2, 3 to the layers L1, L2, L3 in a preset order. The superimposing units 201, 202, and 203 superimpose a preset background color on the layers L1, L2, and L3 output from the superimposition order control unit 200, respectively. In particular, the superimposing unit 202 is controlled by the superimposing control signal 1 output from the display timing control unit 107, and the superimposing unit 203 is controlled by the superimposing control signal 2 output from the display timing control unit 107.

  The selectors 204 and 205 select between which layers the background color is inserted when different images are output to the two displays 112 and 113. In particular, the selector 204 receives the output data of the superimposing unit 201 and data related to the background color, and is controlled by the background color insertion control signal 1 output from the display timing control unit 107. The selector 205 receives the output data of the superimposing unit 202 and data related to the background color, and is controlled by the background color insertion control signal 2 output from the display timing control unit 107.

  In response to the two-screen output mode control signal output from the display timing control unit 107, the display data selector 206 outputs which superimposition result from the superimposition results output from each superimposition unit as display data for each display. Select.

  Note that the number of image data and the number of layers are not limited to three as shown in FIG. Moreover, each superimposition part does not necessarily superimpose a background color under the applicable layer, and may not superimpose depending on a setting, or may perform translucent superimposition. Further, depending on the setting, image data that is not a superimposition target may not be transferred from the memory 114 shown in FIG.

  FIG. 3 is a diagram illustrating display examples of the two displays 112 and 113 by the display function-equipped device 111 including the display processing device 100 according to the first embodiment. In particular, FIG. 3A shows an example in which the same image is displayed on the two displays 112 and 113. FIG. 3B is an example in which completely different images are displayed on the two displays 112 and 113. FIG. 3C is an example in which only some of the image layers displayed on one of the two displays 112 and 113 are displayed.

  In the example shown in FIG. 3A, the display data selector 206 selects the output of the superimposing unit 203 in the layer synthesizing unit 105 as Ch1 image data, and outputs the same image based on the Ch1 image data to two displays. .

  In the example shown in FIG. 3B, the display data selector 206 selects the output of the superimposing unit 201 as display A image data, and the display data selector 206 selects the output of the superimposing unit 203 as display B image data. . At this time, since the selector 204 is controlled to select the background color, the image displayed on the display A does not include the image data of the layer L1. In this way, completely different images can be generated on the two displays by the layer composition unit 105. In the example shown in FIG. 3B, a boundary is set between the layer L1 and the layer L2, but this boundary may be set between any layers.

  In the example shown in FIG. 3C, the display data selector 206 selects the output of the superimposing unit 203 as display A image data, and the display data selector 206 selects the output of the superimposing unit 201 as display B image data. . By doing so, only a part of the layer of the superimposed image displayed on the display A is displayed on the display B. The display on the display B is not limited to the output of the superimposing unit 201 and may be the output of the superimposing unit 202.

  As described above, according to the present embodiment, one display processing apparatus 100 can display the same or different images on the two displays 112 and 113. Further, according to the present embodiment, the display can be realized without an increase in bandwidth load on the internal bus in a state where there is no restriction on data arrangement on the line buffer 103.

  It is conceivable that the device with display function 111 including the display processing device 100 of the present embodiment is applied to, for example, a car display system. In this case, if the display A is a rear seat display and the display B is a front seat display, the same image data is output as shown in FIG. For example, entertainment images such as TV images and DVDs are displayed, and while driving, the entertainment image continues to be displayed at the rear seat as shown in FIG. 3C, and the map image from the car navigation system and the vehicle-mounted camera are displayed at the front seat. It is possible to display a driving support image such as an image from a single display processing device 10.

<Embodiment 2>
FIG. 4 is a block diagram showing a device 412 with a display function including the display processing device 400 according to Embodiment 2 of the present invention. As shown in the figure, a display processing device 400 connected to two displays (displays A and B) 112 and 113 includes an internal bus interface 101 provided in the display processing device 100 of the first embodiment shown in FIG. A buffer control unit 102, a line buffer 103, an image quality adjustment unit 104, a layer synthesis unit 105, a display interface unit (display IF unit) 106, and a display timing control unit 107 are provided, and two display timing generations are further performed. Parts 408a and 408b. In FIG. 4, the same reference numerals are given to the components common to FIG. 1.

  In order for the two displays 112 and 113 to actually display, a timing control signal is required. However, the timing and polarity of the change in the display dot clock unit, horizontal line unit, frame unit, and the like differ depending on the display model. Therefore, in the second embodiment, a display timing generation unit corresponding to each display is provided, and the display timing generation unit 408a receives the dot clock, horizontal synchronization signal, and vertical synchronization signal, which are display basic timing signals, from the display timing control unit 407. Input to 408b.

  The display timing generation unit 408 a outputs a timing control signal requested from the display 112 based on the signal input from the display timing control unit 407. Further, the display timing generation unit 408b outputs a timing control signal requested from the display 113 based on the signal input from the display timing control unit 407.

  According to this embodiment, each display timing generation unit outputs a timing control signal requested by each display. Therefore, if the resolutions of the displays 112 and 13 are the same, an image can be displayed on each display even if different timing control signals are required.

  It is conceivable to apply the display function-equipped device 412 including the display processing device 400 of the present embodiment to, for example, a car display system. When a rear seat display is retrofitted to a car equipped with a car navigation system, the same display is not necessarily installed. Even in such a case, an image can be displayed on a retrofitted display if the device 412 with a display function includes the display processing device 400 of the present embodiment. Therefore, by changing the setting of the timing control signal, the degree of freedom in the specification of a display to be retrofitted can be increased, and the options for the display can be expanded.

<Embodiment 3>
FIG. 5 is a block diagram showing a device with display function 513 including a display processing device 500 according to Embodiment 3 of the present invention. As shown in the figure, the display processing device 500 connected to the two displays (displays A and B) 112 and 113 includes the internal bus interface 101 provided in the display processing device 400 of the second embodiment shown in FIG. A buffer control unit 102, a line buffer 103, an image quality adjustment unit 104, a layer synthesis unit 105, a display interface unit (display IF unit) 106, a display timing control unit 107, and display timing generation units 408a and 408b. And a reduction unit 506. In FIG. 5, the same reference numerals are given to components common to FIG. 4.

  The reduction unit 506 processes the image data displayed on the display 113 output from the layer synthesis unit 505, thereby reducing the image displayed on the display 113 than the image displayed on the display 112. Note that the vertical frequency for display on the display is substantially the same frequency (about 60 Hz) even when the resolutions are different. Therefore, even when the resolutions of the displays 112 and 113 are different, an image can be normally displayed on each display by matching the same vertical frequency and phase.

  According to the present embodiment, it is not necessary to read out image data from the memory 114 again for image display on each display, and two independent display processing devices are not required to display images of two different resolutions. .

<Embodiment 4>
FIG. 6 is a block diagram showing a device with display function 614 including a display processing device 600 according to Embodiment 4 of the present invention. As shown in the figure, the display processing device 600 connected to the two displays (displays A and B) 112 and 113 includes an internal bus interface 101 provided in the display processing device 500 of the third embodiment shown in FIG. A buffer control unit 102, a line buffer 103, an image quality adjustment unit 104, a layer synthesis unit 105, a display interface unit (display IF unit) 106, a display timing control unit 107, display timing generation units 408a and 408b, A reduction unit 506 and a frequency divider 611. In FIG. 6, the same reference numerals are assigned to components common to FIG. 5.

  The frequency divider 611 is provided in the display timing generation unit 408b and divides the dot clock for the display 112 output from the display timing generation unit 408a to generate a dot clock for the display 113. The display timing generation unit 408 b outputs a timing control signal based on the dot clock obtained by the frequency divider 611 to the display 113.

  Different display standards have different dot clocks (frequency at which a dot dot is displayed on the display). Generally, a clock of about 25 MHz is used for a resolution of 640 dots horizontally and 480 dots vertically called VGA, and about 33.2 MHz for a resolution of 800 dots horizontally and 480 dots vertically called WVGA. It is a clock. The vertical and horizontal numbers of dots indicate an effective display area that is actually displayed on the display, and actually there is a non-display period called a blanking period corresponding to the outside of the area. The vertical period corresponding to the blanking period and the dot clock is about 60 Hz.

  As described above, the frequency divider 611 divides the dot clock for the display 112 to generate the dot clock for the display 113. Therefore, when the resolution of the display 113 is 1/4 with respect to the display 112, the frequency divider 611 divides the dot clock for the display 112 by about 1/4. When the display 112 is progressive display and the display 113 is interlaced, an image can be displayed on the display 113 if the frequency divider 611 divides the dot clock of the display 112 by 1/2.

  The frequency divider 611 may not only simply divide 1/2 or 1/4 using a flip-flop or the like, but may use another method. For example, the clock that is the source of the display clock may be set to a very high frequency compared to the clock that is actually output to the display, and the frequency divider 611 may output the dot clock of either the display 112 or the display 113. In this case, the frequency increment of the dot clock can be finely controlled.

<Embodiment 5>
FIG. 7 is a block diagram showing an apparatus 715 with a display function including the display processing apparatus 700 according to the fifth embodiment of the present invention. As shown in the figure, the number of displays is not limited to two, and may be three or more as long as the number of layers can be increased. In addition, the display timing generation unit is provided to be equal to the number of provided displays, and a timing control signal is input to the corresponding display from each display timing generation unit. Further, the number of reduction units 506 described in the third embodiment is not limited to one, and may be two or more.

<Embodiment 6>
FIG. 8 is a schematic diagram of an automobile 800 equipped with an in-vehicle driving support system according to Embodiment 6 of the present invention. An automobile 800 shown in FIG. 8 collects images sent from a front seat display 801, a rear seat display 802, a rear confirmation camera 803, a camera 803, and the like, and outputs an image to be displayed on each display. A processing unit 804, a front seat display 801, a rear seat display 802, and cables 805, 806, and 807 that connect the rear confirmation camera 803 and the image processing unit 804, respectively.

  In the example shown in FIG. 8, the cables 805 to 807 for connection are connected to the image processing unit on a one-to-one basis. However, a configuration in which a network is configured and connected in a ring shape may be used.

  The image processing unit 804 incorporates the display processing device described in the first to fifth embodiments. The front seat display 801 is used for map information provided by car navigation, camera images mounted on automobiles, entertainment, and the like. The rear seat display 802 is mainly used for entertainment of a person wearing the rear seat. However, when the driver moves the vehicle backward, the head or upper body is directed rearward and visual confirmation is performed rearward, and the image from the rear confirmation camera 803 normally displayed on the front seat display 801 is used for the rear seat. By displaying on the display 802 and changing the display direction of the rear seat display 802 to the front seat direction instead of the rear seat direction, the driver can check the image of the rear confirmation camera 803 while viewing the rear.

  In order to change the display direction of the rear seat display 802, various methods are conceivable, such as rotating the direction of the display or making the image visible from both the rear seat and the front seat with a display using a transparent material. However, the method is not limited.

  According to the present embodiment, it is possible to realize driving support capable of suppressing the posture change and the line-of-sight change amount during reverse travel.

  The display processing apparatus according to the present invention is configured to be able to output a plurality of the same or different images from the layer synthesizing unit, so that there is no need to provide a plurality of display processing apparatuses, and data arrangement restrictions in the image memory and an internal bus It is possible to delete the load related to the data transfer. Therefore, the display processing device is effective for a technique for displaying the same or different images on a plurality of display devices such as an in-vehicle information display device including a plurality of displays. The display processing device can also be applied to an in-vehicle driving support system.

1 is a block diagram illustrating a configuration of a display processing device according to a first embodiment. It is a block diagram of the layer synthetic | combination part of Embodiment 1-4. It is a screen display image figure realizable with Embodiments 1-4 of the present invention. FIG. 6 is a block diagram illustrating a configuration of a display processing device according to a second embodiment. FIG. 10 is a block diagram illustrating a configuration of a display processing device according to a third embodiment. FIG. 10 is a block diagram illustrating a configuration of a display processing device according to a fourth embodiment. FIG. 10 is a block diagram illustrating a configuration of a display processing device according to a fifth embodiment. It is a schematic diagram of the motor vehicle 800 carrying the vehicle-mounted driving assistance system which concerns on Embodiment 6 of this invention. It is a structural example of the display processing apparatus to the conventional two displays. It is an example of data arrangement in a memory and a buffer in the case of the display processing apparatus to the conventional two displays.

100, 400, 500, 600, 700 Display processing device 101 Internal bus interface 102 Buffer control unit 103 Line buffer 104 Image quality adjustment unit 105 Layer composition unit 106 Display interface unit 107 Display timing control unit 108 Display timing generation unit 109 Image input unit 110 Memory interfaces 111, 412, 513, 614, 715 Devices with display function 112, 113 Display 114 Memory 200 Superimposition order control units 201, 202, 203 Superimposition units 204, 205 Selector 206 Display data selectors 408a, 408b Display timing generation unit 506 Reduction 611 Frequency divider 700 Display processing device 800 Automobile 801 Front seat display 802 Rear seat display 803 Rear confirmation camera 804 Image processing unit 805 pre-seat display - the image processing unit between the cable 806 after seat display - the image processing unit between the cable 807 Rearview camera - after image processing unit between the cable 808 handle 809 front seat 810 seat

Claims (6)

A display processing apparatus for processing to display the same or different images on a plurality of displays having the same resolution,
An image acquisition unit for acquiring image data assigned to each of the plurality of layers;
Among the image data acquired by the image acquisition unit, there are a plurality of superimposing units that superimpose image data of at least one layer, and the superposition result of at least one superimposing unit of the plurality of superimposing units is used as the layer synthesis. A layer synthesis unit that outputs as superimposed image data to be displayed on each of the plurality of displays by the unit;
A selection instruction unit for giving an instruction related to selection of superimposed image data output by the layer synthesis unit;
A display processing apparatus.   Display timing control unit that generates different timing control signals and outputs to each display in order to control each display in the same vertical synchronization period and horizontal synchronization period for the plurality of displays having different specifications other than resolution at least A display processing apparatus according to claim 1. Of the multiple displays, at least one display and the other display have different resolutions,
A reduction unit that processes the superimposed image data indicating the image so as to reduce the size of at least one image indicated by the superimposed image data output from the layer synthesis unit;
A display timing control unit that generates different timing control signals and outputs to each display in order to control each display having different resolutions in the same vertical synchronization period and different horizontal synchronization periods;
The display processing device according to claim 1, further comprising: The display timing controller is
Generating the timing control signal including a dot clock to be set in the corresponding display;
The display processing apparatus according to claim 3, further comprising a frequency divider that divides a dot clock having a predetermined frequency.   The frequency divider divides a dot clock set on a display that displays an image that is not reduced by the reduction unit, and generates a dot clock set on a display that displays an image reduced by the reduction unit. The display processing apparatus according to claim 4, wherein the display processing apparatus outputs. An in-vehicle driving support system comprising the display processing device according to claim 1, 2, 3, 4 or 5,
Attach the first display to a position that can be seen when the driver is facing forward, such as the center console. View the second display when the driver checks the back, such as in the center of the ceiling. A vehicle-mounted driving support system that displays a camera image attached to the rear of the vehicle with a second display while being attached to a position where the driver can move the vehicle backward while observing the rear.

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