JP2010199358A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To make it possible to efficiently manufacture a semiconductor device having high reliability. <P>SOLUTION: The method of manufacturing a semiconductor device includes the steps of: forming an insulating film 4 on a semiconductor substrate 1; etching a first region TC1 of the insulating film 4 so that the thickness of the first region becomes thinner than the thickness of a second region TB1 positioned in the vicinity of the first region TC1; etching the insulating film 4 in the first region TC1 and the second region TB1 after etching the first region TC1 of the insulating film 4 and patterning the insulating film 4; and etching the semiconductor substrate 1 using a mask 10 formed by patterning the insulating film 4 and forming a groove 11 for forming a region which separates an element in the semiconductor substrate 1. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device.

When a plurality of transistors for performing data processing are formed side by side in a semiconductor device, it is necessary to form an element isolation insulating layer that separates the active regions of the transistors on the surface of the silicon substrate.
Here, when STI (Shallow Trench Isolation) is used as the element isolation insulating layer, the transistor can be miniaturized, and the semiconductor device can be highly integrated and have high performance. When forming STI, dry etching is performed using a hard mask formed on a silicon substrate to form an isolation trench, and an isolation insulating film for embedding such as silicon oxide is embedded therein. Thereafter, the excess isolation insulating film is removed by a chemical mechanical polishing (CMP) method. As a result, the STI is formed by the isolation insulating film buried in the isolation trench.

  By the way, when polishing by the CMP method, since the hard mask polishing rate is small with respect to the isolation insulating film, there are a region where elements such as transistors are densely formed on a silicon substrate and a region where elements are not densely formed. The amount of polishing varies depending on the location. That is, since the area where the elements are densely occupied has a large area occupied by the hard mask used to form the trench, it is harder to polish than the area where the area occupied by the hard mask is relatively small, such as an area where the elements are not densely packed. Become. For this reason, if the polishing is performed until the isolation insulating film in the region where the elements are densely packed reaches the target value, the region where the elements are not crowded is excessively polished. On the other hand, when the polishing is finished when the isolation insulating film in the region where the elements are not densely reached the target value, the region where the elements are densely ground becomes insufficient.

  If the process proceeds to the next step after the CMP method is polished and the film thickness of the isolation insulating film becomes nonuniform, there is a possibility that the resist pattern may be defective or an etching failure may occur. For example, the isolation insulating film is excessively polished and etched in a region where the elements are not densely packed, so that the active region of the silicon substrate protrudes from the isolation insulating film. In the next process, when the conductive film is patterned to form the gate electrode of the transistor on the active region, the conductive film remains on the side of the protruding active region and leakage occurs between adjacent source / drain regions. In some cases, transistor characteristic defects may occur. This causes a decrease in the yield of the semiconductor device.

  If the process proceeds to the next step after the CMP method is polished and the film thickness of the isolation insulating film becomes nonuniform, there is a possibility that the resist pattern may be defective or an etching failure may occur. For example, the isolation insulating film is insufficiently polished and etched in the region where the elements are densely packed, and the isolation insulating film protrudes from the active region of the silicon substrate. Then, when the conductive film is patterned in the next step to form the gate electrode of the transistor on the active region, the conductive film remains on the side of the protruding isolation insulating film, and leakage occurs between adjacent gates. May cause a characteristic failure. This causes a decrease in the yield of the semiconductor device.

  Therefore, conventionally, a base insulating film and a first protective film are sequentially formed on a silicon substrate, and all of the first protective film in a region where elements are concentrated is removed by etching. Next, a second protective film is formed on the entire surface of the substrate. As a result, a two-layered film composed of the base insulating film and the second protective film is formed on the silicon substrate in the region where the elements are densely packed. On the other hand, in a region where elements are not densely formed, a three-layer laminated film including a base insulating film, a first protective film, and a second protective film is formed on a silicon substrate.

  Thereafter, the laminated film is etched by dry etching, and further etched to form a separation groove having a predetermined depth in the silicon substrate. At this time, in a region where the elements are not densely packed, a longer etching time is required until the surface of the silicon substrate is exposed by the amount of the first protective film. For this reason, the isolation trench in the region where the elements are not densely formed is shallower than the region where the elements are densely packed.

  As a result, when the isolation insulating film is embedded in the isolation trench, the height of the surface of the isolation insulating film in the region where the element is not densely becomes higher than the region where the element is densely increased by the shallowness of the isolation trench. Further, even after the surface is polished by the CMP method, the height of the isolation insulating film in the region where the elements are not concentrated is higher than the isolation insulating film in the region where the elements are concentrated due to the shallowness of the isolation trench. Thereafter, the height of the surface of the isolation insulating film in both regions is adjusted to a desired value by wet etching.

JP 2006-351747 A

However, in the above conventional manufacturing method, it is necessary to stack the first and second protective films on the base protective film, and the second protective film needs to be formed after the first protective film is etched. The process was complicated. Furthermore, after polishing by the CMP method, a step of adjusting the height of the isolation insulating film by wet etching is necessary. For this reason, it has been difficult to shorten the manufacturing time.
Further, the height of the element isolation insulating film may not be adjusted depending on the arrangement of the areas where the elements are densely arranged, the arrangement where the elements are densely arranged and the area where the elements are not densely arranged, or the size of the area where the elements are densely arranged.

  The present invention has been made in view of such circumstances, and a main object of the present invention is to enable efficient manufacture of a highly reliable semiconductor device.

  According to one aspect of the present application, a step of forming a first insulating film on a semiconductor substrate, a step of forming a second insulating film on the first insulating film, and the second insulating film Etching the first region so that the thickness of the first region is smaller than the thickness of the second region located around the first region; and After the etching, in the first region and the second region, the second insulating film is etched to pattern the second insulating film, and the second insulating film is patterned. A step of etching the first insulating film and the semiconductor substrate using the formed mask to form a groove for forming an element isolation region in the semiconductor substrate. A manufacturing method is provided.

The objects and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims.
It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not intended to limit the invention.

According to the present invention, since the hard mask is formed by previously reducing the thickness of a part of the hard mask in the dense region, a new film is formed after the part of the hard mask film is etched. The process can be simplified compared to the case of stacking. Further, since the time required for polishing is made substantially constant regardless of the location by changing the film thickness of the hard mask depending on the location, the surface of the polished semiconductor substrate or insulating film can be flattened.

FIG. 1 is a sectional view (No. 1) showing a manufacturing process of a semiconductor device according to an embodiment of the present invention. FIG. 2 is a sectional view (No. 2) showing the manufacturing process of the semiconductor device according to the embodiment of the invention. FIG. 3 is a sectional view (No. 3) showing the manufacturing process of the semiconductor device according to the embodiment of the invention. FIG. 4 is a sectional view (No. 4) showing the manufacturing process of the semiconductor device according to the embodiment of the invention. FIG. 5 is a flowchart showing processing for determining conditions for adjusting the film thickness of the hard mask layer. FIG. 6 is a plan view of the semiconductor device, and is a diagram for explaining a portion where film thickness measurement is performed. FIG. 7 is a diagram illustrating an example of a film thickness measurement result. FIG. 8 is a cross-sectional view showing a semiconductor substrate on which an STI formed for determining the film thickness adjustment condition of the hard mask layer is formed. FIG. 9 is a cross-sectional view showing a manufacturing process when the process of adjusting the thickness of the hard mask layer is performed twice. FIG. 10 is a plan view showing an example of a case where regions where active regions are concentrated are arranged close to each other.

Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings. In the drawings, similar components are given the same reference numerals.
First, a process of forming STI on a silicon substrate that is a semiconductor substrate will be described.
As shown in FIG. 1A, a base protective film 3 (first insulating film) and a protective insulating film 4 used as a hard mask film 2 are formed on the surface of an n-type or p-type silicon substrate 1 (semiconductor substrate). (Second insulating film) is formed in order.

For example, a SiO ₂ film having a thickness of 10 nm, for example, formed by a thermal oxidation method is used for the base protective film 3, and for example, Si ₃ having a thickness of 150 nm, for example, formed by a CVD (chemical vapor deposition) method, for the protective insulating film 4. N ₄ membrane is used. Further, a photoresist film 5 is applied on the hard mask film 2. In the present embodiment, an example in which the positive photoresist film 5 is used will be described, but a negative type may be used.

  Then, as shown in FIG. 1B, the photoresist film 5 is exposed, developed and baked to be patterned to form a resist pattern 5A. The pattern of the reticle (thickness adjusting reticle) used for exposure at this time is formed in accordance with a dense region TA1 in which elements such as transistors are densely formed. More specifically, in the reticle for adjusting the film thickness, the center of the opening that transmits light coincides with the center of the dense region TA1, and the size of the image on the silicon substrate 1 is narrower than that of the dense region TA1. It has an opening corresponding to one region TC1.

Here, as shown in FIG. 1A, the first region TC1 is narrower than the dense region TA1, for example, a region narrower to the inside by about two elements than the dense region TA1. Further, the second area SA1 includes the peripheral area TB1 around the outside of the first area TC1 in the dense area TA1, and the dense area TA1.
1 is a region including a sparsely populated region CA1 that is outside of 1 and does not concentrate elements.

  Further, as shown in FIG. 1C, dry etching is performed using the resist pattern 5A to reduce a part of the protective insulating film 4 to a predetermined thickness, for example, about 120 nm. The etching amount when performing dry etching is set to a preset value. In this way, by partially adjusting the film thickness of the hard mask layer 2, the film thickness d1 of the hard mask layer 2 in the first region TC1 is changed to the film thickness d2 in the second region SA1 which is the surrounding region. Thinner. Therefore, in the hard mask layer 2 in the dense region TA1, a step is formed in the protective insulating film 4 at the boundary between the first region TA1 and the second region SA1.

  After removing the resist pattern 5A, an antireflection film is formed on the protective insulating film 4 and then a new photoresist film is formed. Further, the photoresist film is exposed and developed. Thereby, as shown in FIG. 1D, a resist pattern 6 </ b> A having an opening in a region corresponding to the arrangement of the separation groove is formed on the antireflection film 15 on the protective insulating film 4.

  Next, as shown in FIG. 2A, using the resist pattern 6A formed in the previous step as a mask, at least the protective insulating film 4 of the hard mask film 2 is dried by the RIE method using a fluorine-based gas. The hard mask 10 is formed by etching. The hard mask 10 formed at this time has a configuration in which the film thicknesses are partially different. Specifically, a hard mask 10A having a high-density pattern is formed in the first region TC1 corresponding to the central portion of the dense region TA1, and the thickness d1 of the hard mask 10A in this region is larger than that of other regions. thin. In the second region SA1 including the peripheral region TB1 and the depopulated region CA1, a hard mask 10B having a pattern with a film thickness d2 thicker than the film thickness d1 is formed.

  In FIG. 2A, a hard mask 10A having a relatively thin film thickness in the first region TC1 is formed in a pattern that individually covers a large number of active regions, and a hard film having a relatively large film thickness in the peripheral region TB1. A mask 10B is formed so as to cover each of the two active regions. Furthermore, a cross-sectional view in which one hard mask 10B is formed in the depopulated area CA1 is illustrated.

  Here, in the dense area TA1 and the depopulated area CA1, the hard mask 10 has a pattern corresponding to the number of active areas. One or more patterns of the hard mask 10B are formed in the peripheral area TB1 of the dense area TA1.

  In the depopulated area CA1, only one pattern covering the active area of the hard mask 10B having a film thickness of d2 is shown. However, a plurality of patterns covering the active area of the hard mask 10B may be formed. The mask 10B may not be formed at all.

Thereafter, as shown in FIG. 2B, the silicon substrate 1 is predetermined using the resist pattern 6A and the hard mask 10 by the RIE method using a reactive gas containing at least one of a chlorine-based gas and a fluorine-based gas. The isolation trench 11 is formed in the element isolation region by etching to a depth of 1 mm.
The depth of the separation groove 11 formed in the silicon substrate 1 is substantially the same in the first region TC1 and the second region SA1, and is, for example, 360 nm to 420 nm. When the base protective film 3 is left on the surface of the silicon substrate 1, the protective insulating film 4 is also etched when the isolation trench 11 is formed.

After the separation groove 11 is formed, the resist pattern 6A is removed by ashing. After that, a thin oxide film may be formed on the inner surface of the separation groove 11 by a thermal oxidation method.
Furthermore, as shown in FIG. 2 (c), as an element isolation insulating film 12 on the silicon substrate 1 (the third insulating film), for example, it is deposited by a SiO ₂ film HDP (high Density Plasma) -CVD method. The element isolation insulating film 12 is deposited to a thickness that completely fills the isolation trench 11 and covers the hard mask 10.

  Next, the element isolation insulating film 12 is polished by CMP. For CMP, for example, a slurry containing silica as abrasive grains is used. In the initial stage of polishing, since the entire surface is covered with the element isolation insulating film 12, the polishing rate becomes uniform regardless of the location. Further, as the polishing proceeds, the hard mask 10B is exposed on the respective surfaces of the peripheral area TB1 of the dense area TA1 and the depopulated area CA1, as shown in FIG. This is because the thickness of the hard mask 10B in the regions TB1 and CA1 is thicker than the hard mask 10A in the first region TC1.

At this stage, only the element isolation insulating film 12 is polished in the first region TC1 in the dense region TA1, that is, the region of the thin hard mask 10A, since the hard mask 10A is not yet exposed.
In contrast, in the second region SA1, that is, the peripheral region TB1 and the depopulated region CA1 of the dense region TA1, both the element isolation insulating film 12 and the hard mask 10B are polished. Since the hard mask 10B is harder than the element isolation insulating film 12, the polishing rate is low, and the first region TC1 is more easily polished than the peripheral region TB1 and the depopulated region CA1.

  Further, as the polishing proceeds, the surface of the hard mask 10A is exposed also in the first region TC1. In the first region TC1, since the hard masks 10A are arranged at a high density, the polishing rate is smaller than that in the second region SA1. That is, the polishing rate of the hard mask 10A in the first region TC1 is relatively small, and the polishing rate of the hard mask 10B in the second region SA1 is relatively high. Therefore, if the polishing is further advanced, the film thickness of the hard mask 10A in the first region TC1 and the film thickness of the hard mask 10B in the second region SA1 can be made substantially the same as a result.

As a result, as shown in FIG. 3A, the surfaces of the hard masks 10A and 10B and the element isolation insulating film 12 become flat regardless of the density of the active region. When the polishing is completed, the protective insulating film 4 constituting the hard masks 10A and 10B is removed by wet etching using, for example, hot phosphoric acid.
Through the above steps, as shown in FIG. 3B, the element isolation insulating film 12 is buried in the isolation trench 11, and an STI surrounding the active region is formed.

Next, a process for forming a transistor in the active region will be described.
First, as shown in FIG. 3B, a p-type impurity such as boron is introduced into the transistor active region of the silicon substrate 1 surrounded by the STI element isolation insulating film 12 to form a p-well 21. Note that when an n-well is formed, an n-type impurity such as phosphorus is introduced into the transistor active region. Then, the surface of the transistor active region is thermally oxidized to form the gate insulating film 22. In this case, the gate insulating film 22 is a silicon oxide film formed by thermal oxidation and has a thickness of about 6 to 7 nm.

  Further, an amorphous or polycrystalline silicon film 23 is formed on the surface of the silicon substrate 1. After that, the gate electrode 24 shown in FIG. 3C is formed by patterning the silicon film 23 using a photolithography technique.

Subsequently, as shown in FIG. 4, ion implantation is performed using the gate electrode 24 as a mask, an n-type impurity such as phosphorus is introduced into the surface layer of the silicon substrate 1 on both sides of the gate electrode 24, and source / drain extensions 25 are formed. Form.
Thereafter, an insulating film is formed on the entire upper surface of the silicon substrate 1 including the gate electrode 24, and the insulating film is etched back to leave only the both side portions of the gate electrode 24.
Form. For the insulating film, for example, a silicon oxide film formed by a CVD method is used.

Subsequently, n-type impurities such as arsenic are ion-implanted again into the surface layer of the silicon substrate 1 using the insulating sidewall 28 and the gate electrode 24 as a mask, and high-concentration impurity diffusion is performed on the silicon substrate 1 on both sides of each gate electrode 24. A source / drain region 29 of the region is formed.
Further, a metal film is formed on the entire upper surface of the silicon substrate 1 including the gate electrode 24 by sputtering. Here, the metal film is preferably a high melting point metal such as a cobalt film, but may be a metal having a relatively low melting point.

  Then, a metal silicide layer 30 such as a cobalt silicide layer is formed on the upper surface of the gate electrode 24 and the source / drain region 29 by heating and reacting the metal film and silicon. Each heat source / drain region 29 may be activated by this heat treatment. After that, the unreacted refractory metal film on the element isolation insulating film 12 and the like is removed by wet etching.

  As a result, a plurality of transistors T constituted by the gate insulating film 22, the gate electrode 24, the source / drain regions 29, etc. are formed for each active region of the silicon substrate 1, and an interlayer insulating film, vias, wirings, etc. are formed thereon. By forming the semiconductor device, a semiconductor device is completed.

Next, in order to determine the number of times a part of the hard mask layer 2 is etched in the steps shown in FIGS. 1A to 1C, the range in which the film thickness is adjusted by one etching, and the etching depth. This flow will be described with reference to FIG.
In the following, each process of STI formation is performed without adjusting the film thickness of the hard mask layer 2 in the first process in the flow, and the film thickness of the hard mask layer 2 is adjusted in the second and subsequent processes. The case where the STI is formed so as to obtain the film thickness distribution is described as an example.

First, design data of the semiconductor device is acquired (step S101). The design data is data related to the dimensions and layout of the circuit of the semiconductor device, and includes STI arrangement and shape data.
Thereafter, a reticle is produced based on the design data (step S102). The reticle produced at this time has the shape of a resist pattern 6A for forming the hard mask 10 (10A, 10B) shown in FIGS. 1 (d) and 2 (a).

Furthermore, pattern density data is extracted from the design data (step S103). Here, the design data is processed, and an area where the density of the active areas exceeds a preset value is extracted as a density area TA1 as shown in FIG.
Note that the order of reticle production shown in step S102 and extraction of coarse / dense data shown in step S103 may be reversed.

  Next, as illustrated in FIG. 1D, a resist pattern 6 </ b> A is formed on the hard mask layer 2 using the reticle manufactured in step S <b> 102 with the hard mask layer 2 formed on the silicon substrate 1. To do. Next, the hard mask 10 is formed by dry etching the hard mask layer 2 using the resist pattern 6A as a mask (step S104).

  Since the process here is performed for the purpose of investigating the film thickness error of the hard mask 10 caused by polishing by the CMP method, the hard mask layer described with reference to FIGS. 1 (a) to 1 (c). The step of partially adjusting the film thickness of 2 is not performed.

Thereafter, the silicon substrate 1 is dry-etched using the hard mask 10 to separate the separation grooves 11.
Form. Further, an element isolation insulating film 12 is formed so as to fill the hard mask 10 and the isolation trench 11.

  Then, the element isolation insulating film 12 on the hard mask 10 is polished and removed by the CMP method (step S105). For example, the polishing time is set so that the film thickness of the element isolation insulating film 12 in the first region TC1 becomes a predetermined target value.

Thereafter, the film thickness of the hard mask 10 on the silicon substrate 1 is measured (step S106). The film thickness measurement is performed on a region extracted from the pattern density data where the density of the active region exceeds a preset value, that is, the dense region TA1. Specifically, as shown in FIG. 6, the measurement is performed at multiple points including the dense area TA1 and the peripheral area TB1 at the end thereof, and the measurement direction is, for example, the arrangement direction of the active areas.
The film thickness is measured in a non-contact manner using a laser beam or the like, and the measurement result is input to a data processing device (not shown).

In the data processing apparatus, the difference between the designed film thickness and the measured film thickness is calculated. Here, since the process of adjusting a part of the film thickness of the hard mask 10 is not performed, the film thickness distribution of the element isolation insulating film 12 and the hard masks 10A and 10B is not constant.
For example, in the dense region TA1 shown in FIGS. 6 and 7, the film thickness of the peripheral region TB1 is thinner than the central portion. As described above, since the pattern density of the hard mask 10 is lower in the second area CA1 including the peripheral area TB1 than in the first area TC1, the polishing rate of the second area CA1 is increased. Because.

Specifically, as shown in FIG. 8, the hard mask 10A in the first area TC1 in the dense area TA1 is the thickest, and the hard mask 10B gradually becomes thinner in the order of the peripheral area TB1 and the depopulated area CA1. .
If such a difference in film thickness is within a preset allowable range (Yes in step S107), the semiconductor device is manufactured using the reticle and etching conditions used in the steps so far.

  On the other hand, when the difference in film thickness exceeds a preset allowable range (No in step S107), the opening area of the reticle for etching a part of the hard mask layer 2 by obtaining the distribution of the film thickness And adjustment data for updating the opening position and the etching conditions are created (step S108), and the process returns to step S101. The adjustment data is correction data that increases or decreases at least one of the etching position, the etching area, and the etching amount.

  For example, when the etching rate of the peripheral region TB1 of the first region TC1 is high, data for making the central portion TC1 of the dense region TA1 thinner than the peripheral region TB1 for the hard mask layer 2 is created. If there are a plurality of dense regions in the semiconductor device formation region for the hard mask layer 2, adjustment data for each region is created, and adjustment data for varying the film thickness according to the pattern density is created.

  After the adjustment data is created, a reticle for adjusting the film thickness and a reticle for forming the hard mask are prepared using the design data and the adjustment data (steps S101 and S102). In the case of using a positive resist, the reticle for adjusting the film thickness is a first region TC1 in which the center position of the opening that transmits light coincides with the center position of the dense region TA1, and the opening area is narrower than the dense region TA1. It has a shape corresponding to.

  Then, pattern density data is extracted (step S103), and the hard mask layer 2 is patterned using the reticle for adjusting the film thickness and the reticle for forming the hard mask to form the hard mask 10 (step S104).

  More specifically, first, as shown in FIG. 1B, a resist pattern 5A is formed by a reticle for adjusting the film thickness. Further, dry etching is performed using the resist pattern 5A as a mask, and a part of the film thickness of the hard mask layer 2 is adjusted as shown in FIG. The etching amount is based on the adjustment data. Thereby, the first region TC1 of the hard mask layer 2 is adjusted to be thin.

  Then, as shown in FIGS. 1D and 2A, a resist pattern 6A is formed using a reticle for forming a hard mask pattern. Further, when the hard mask film 2 is etched using the resist pattern 6A, the hard mask 10 is obtained in which the film thickness of the first region TC1 is relatively thinner than that of the second region SA1.

After the silicon substrate 1 is etched using such a hard mask 10 to form an isolation groove 11, an element isolation insulating film 12 is deposited, and then polished by a CMP method. Further, after polishing, the film thickness is measured in the same manner as before.
If the difference in film thickness is within an allowable range (step S107), the semiconductor device is manufactured using a correction reticle and corrected etching conditions. On the other hand, if the difference in film thickness exceeds the allowable range, adjustment data is created again and the above process is repeated.

  As the adjustment data here, for example, the size of the first region TC1 is increased by 5% and the etching amount is increased by 3%. Then, based on such adjustment data, a reticle for film thickness adjustment for the second time is produced, and etching is performed on the hard mask layer 2 newly produced using this reticle. The area of the first region TC1 of the reticle thus formed is, for example, 5% larger than that formed by the first film thickness adjusting reticle manufactured. Further, the film thickness d1 of the hard mask layer 2 in the first region TC1 formed here is, for example, 3% thinner than that formed by the film thickness adjusting reticle manufactured first.

  If only the area of the first region TC1 is increased in the adjustment data, the number of active region patterns of the hard mask 10A having a small thickness when the hard mask layer 2 is etched increases. Further, even if the size of the first region TC1 is the same, if the etching amount is increased, the number of active region patterns of the thin hard mask 10A is not changed, but the thickness of the hard masks 10A and 10B between the regions is not changed. The difference increases.

Further, when the first region TC1 of the adjustment data is widened and the etching amount is increased, the number of patterns of the active region of the thin hard mask 10A is increased, and the film thickness of the second region SA1 with the hard mass 10B is increased. The difference also increases.
The adjustment data is data that causes one of these three methods to be performed. In the flow shown in FIG. 5, when the etching range for adjusting the film thickness is too wide or the etching amount is too large, the set values may be decreased.

  After forming the isolation trench 11 using the hard mask 10 thus formed, the element isolation insulating film 12 is formed by the HDP-CVD method, and then polished by the CMP method. The film thickness of the hard mask 10 is also measured (Steps S105 and S106). Thereafter, the above process is repeated until the difference in film thickness falls within the allowable range.

Here, when the number of repetitions n (n: positive integer) of the flow in FIG. 5 is increased to produce a reticle for adjusting the hard mask thickness after the third time or the etching amount is adjusted, an STI is formed. The uniformity of the film thickness of the element isolation insulating film 12 and the hard mask 10 on the surface of the silicon substrate 1 can be further improved. This is because the shape of the hard mask layer 2 can be optimized gradually by increasing the number of repetitions n. In this case, in order to adjust the etching range and etching amount of the hard mask layer 2 with high accuracy, the allowable range value may be reduced every time the adjustment data is updated.

Although the increase / decrease in the etching area and the increase / decrease in the etching amount in the adjustment data shown in step S108 vary depending on the material of the hard mask layer 2 and the isolation insulating film 12 and the polishing conditions by the CMP method, it is −10% to A range of 10% is preferred.
This is because if a value larger than this range is set as the adjustment amount, the hard mask 10 is made too thin by one adjustment, which may make adjustment difficult. On the other hand, if a value smaller than that range is set as the adjustment amount, the process in FIG. 5 must be repeated many times.

  By the way, in the above, each process was implemented without adjusting the film thickness of the hard mask layer 2 in the first process, but the film thickness of the hard mask layer 2 was adjusted from the beginning to obtain a desired film thickness distribution. You may make it obtain. That is, a first adjustment amount such as an etching amount for adjusting the film thickness of the hard mask layer 2 in the first region TA1 is predicted according to the density of the active region for element formation in the concentration region TA1, You may adjust it.

  For example, since the polishing rate is expected to be small in a region where the density of the active region is high, a large value is indicated as an initial value of the etching amount of the hard mask layer 2 in the first region TA1. Adjustment data may be created in the initial state. On the other hand, since the polishing rate is expected to be small in the region where the density of the active region is low, zero or a small value is indicated as the initial value of the etching of the hard mask layer 2 in the second region CA1. Such adjustment data may be created.

  Even in this case, before actually manufacturing the semiconductor device, the process is performed according to the flowchart of FIG. 5 to determine the process conditions for adjusting the film thickness and the range of the hard mask layer 2. And at the time of manufacture of a semiconductor device, the process of adjusting the film thickness of the hard mask layer 2 is implemented on the conditions.

  The initial values and adjustment data values described above may be determined based on data obtained by forming an STI exclusively for data adjustment, but are determined based on data actually obtained in the manufacturing process of the semiconductor device. You may do it.

Next, the case where the process of adjusting the film thickness of the hard mask layer 2 is performed a plurality of times during the manufacture of the semiconductor device will be described.
In one semiconductor device formation region, the density in a predetermined area of the active region is not necessarily divided into two areas, the dense area and the sparsely populated area as described above, and there are a plurality of areas having different densities.

  Therefore, the step of etching a part of the hard mask film 2 is executed once and only two regions due to the difference in film thickness are formed, and the element isolation insulating film 12 in the entire semiconductor device formation region is flattened by CMP. It can be difficult to polish. In such a case, the substrate surface can be planarized by etching a part of the hard mask film 2 in a plurality of times.

For example, it is possible to process a hard mask using two or more reticles for adjusting the film thickness. That is, the first dry etching is performed on the hard mask layer 2 in the first region TC1 with the resist pattern 5A formed using the first film thickness adjusting reticle. Thereafter, a part of the first dry-etched region is further dry-etched with a resist pattern formed using a second film thickness adjusting reticle, for example, as shown in FIG. Mask layer 2 is formed.

  In the hard mask layer 2 shown in FIG. 9A, the intermediate region TC3 is arranged inside the peripheral region TB1 in the dense region TA1, and the film thickness d11 of the central region TC2 of the first region TC1 is the smallest. The film thickness d12 of the surrounding intermediate region TC3 is the second smallest. The film thickness d2 of the hard mask layer 2 in the second region SA1 is the largest.

  In order to obtain such a film thickness distribution, when the hard mask layer 2 is etched, the hard mask layer 2 in the central region TC2 and the intermediate region TC3 is first formed using the first film thickness adjusting reticle. Etch until d12. Next, using a second reticle for adjusting the film thickness, a resist pattern having an opening only in the central region TC2 is formed, and only the hard mask layer 2 in the central region TC2 is etched until the film thickness reaches d11.

When the hard mask layer 2 whose thickness is adjusted stepwise by a plurality of etchings as described above is etched with the resist pattern 6A shown in FIG. 1D, the active region is covered as shown in FIG. 9B. A hard mask 40 having an isolated pattern is obtained. The hard mask 40 includes a first hard mask 40A formed in the central region TC2 of the first region TC1, a second hard mask 40B formed in the intermediate region TC3, and a third hard mask 40 in the second region SA1. A hard mask 40C, and the film thickness increases in that order.
In the second region SA1, a hard mask 40C that covers at least one active region is formed in each of the peripheral region TB1 and the depopulated region CA1.

  When the isolation trench 11 and the isolation insulating film 12 are formed in the silicon substrate 1 using the hard mask 40 and then polished by CMP, the third hard mask 40C in the second region SA1 is first exposed on the surface. . Next, the second hard mask 40B of the intermediate region TC3 of the first region TC1 is exposed on the surface. Finally, the first hard mask 40A in the central region TC2 is exposed.

  Thereby, the arrangement density of the active regions of the hard mask 40 is the highest in the central region TC2, and the polishing rate is the lowest. Correspondingly, since the film thickness of the hard mask 40 is gradually reduced according to the arrangement density of the active regions, the film thickness of the hard mask 40 in each region can be made substantially the same after polishing by CMP. . As a result, the surface of the element isolation insulating film 12 after polishing in the semiconductor device formation region becomes flat.

Thus, when a plurality of reticles for adjusting the film thickness are used, the uniformity of the film thickness of the element isolation insulating film 12 after polishing can be improved.
Incidentally, as shown in FIG. 10, when there are two dense regions TA1 and these regions are arranged close to each other, the polishing rate of the portion TB2 closest to each other in the two dense regions TA1 is high. May fall. This is because if the unit area for obtaining the density of the active region, that is, the element formation region is narrowed, the density of the approaching portions of the two density regions TA1 is high.

This is because the density of the active region of the peripheral portion TB2 closest to each other in the two dense regions TA1 is increased. In this case, the film thickness of the hard mask in the closest peripheral portion TB2 is preferably made thinner than the thickness of the hard mask in other peripheral portions TB1.
Therefore, even in the peripheral areas TB1 and TB2 of one dense area TA1, the hard mask 40 having a different film thickness is formed, and the peripheral area of the dense area TA1 is the active area density of the adjacent area. Therefore, the thickness is not always the same.

In the case where the film thickness of the hard mask layer 2 is varied at a plurality of stages, a plurality of types of reticles for film thickness adjustment are prepared, and the adjustment is performed according to the flow of FIG.
If a program for performing the processing shown in the flowchart of FIG. 5 is installed in a computer and executed, high-speed and accurate processing is possible. The manufacturing apparatus used for this process has a configuration in which reticle data and etching condition data are changed and output by inputting design data and adjustment data.

  In the above embodiment, a reticle is used to form a resist pattern used for adjusting the film thickness of the hard masks 10 and 40 and patterning them. However, the exposure for forming the resist pattern is not limited to the exposure method using a reticle, and electron beam exposure may be employed. This eliminates the need for reticle fabrication, and eliminates the need for reticle replacement when the film thickness adjustment of the hard mask layer 2 by etching is performed in multiple steps, thereby simplifying the process.

  According to the semiconductor device manufacturing method described above, the thickness of the hard mask layer 2 is adjusted by etching, and then the hard masks 10 and 40 for forming the STI are patterned. This eliminates the need for a plurality of film forming steps for adjusting the film thickness of the protective insulating film 4 constituting the hard masks 10 and 40, thereby simplifying the manufacturing process.

Further, after forming hard masks 10 and 40 in which regions having high density of active regions are made thinner than regions having low density, silicon substrate 1 is etched using hard masks 10 and 40 to form isolation grooves 11. Yes.
As a result, the isolation trench 11 having substantially the same depth can be formed without being affected by the difference in the density of the active regions, and the film thickness distribution of the element isolation insulating film 12 embedded in the isolation layer 11 is made uniform. So that the wet process is not necessary.

  Further, when the hard masks 10 and 40 formed thicker than the regions having a high thickness in the regions where the active regions are low in density are used, the density of the active regions is increased when the element isolation insulating film 12 is polished by the CMP method. In the region where the density is low, the polishing rate is higher than in the region where the density is high. Thereby, the thickness of the hard masks 10 and 40 in those regions can be made uniform by polishing to flatten the surface, and the thickness of the element isolation insulating film 12 constituting the STI can be made uniform.

  Furthermore, by adjusting the film thickness of the hard masks 10 and 40 under the conditions determined according to the flowchart shown in FIG. 5, the film thickness of the hard masks 10 and 40 after polishing the element isolation insulating film 12 is optimized with high accuracy. It becomes possible to adjust. As a result, it is possible to prevent the occurrence of unevenness in the height difference between the STI and the active region, thereby preventing the conductive film from remaining on the level difference.

  All examples and conditional expressions given here are intended to help the reader understand the inventions and concepts that have contributed to the promotion of technology, such examples and It should be construed without being limited to the conditions, and the organization of such examples in the specification is not related to showing the superiority or inferiority of the present invention. Although embodiments of the present invention have been described in detail, it should be understood that various changes, substitutions and variations can be made thereto without departing from the spirit and scope of the present invention.

The features of this embodiment will be added below.
(Supplementary Note 1) Of the second insulating film, a step of forming a first insulating film on the semiconductor substrate, a step of forming a second insulating film on the first insulating film, and the first insulating film. Etching the region so that the thickness of the region is thinner than the thickness of the second region located around the first region, and after etching the first region of the second insulating film, In the first region and the second region, a step of etching the second insulating film and patterning the second insulating film, and a mask formed by patterning the second insulating film Etching the first insulating film and the semiconductor substrate to form a groove for forming an element isolation region in the semiconductor substrate. A method for manufacturing a semiconductor device, comprising:
(Appendix 2) The method includes forming the element isolation regions in the plurality of grooves by polishing the third insulating film and the mask after the third insulating film is embedded in the plurality of grooves. The method for manufacturing a semiconductor substrate according to appendix 1, wherein:
(Supplementary note 3) After the step of polishing the second insulating film, the thickness of the second insulating film is measured, and the shape of the first region is changed according to the measured result. The manufacturing method of a semiconductor device according to Supplementary Note 2, wherein
(Supplementary Note 4) After the step of polishing the second insulating film, the thickness of the second insulating film is measured, and the second insulating film in the first region is measured according to the measurement result. The method for manufacturing a semiconductor device according to appendix 2, wherein the etching amount is changed.
(Appendix 5) Obtaining design data of a semiconductor device, extracting the density of an active region, setting the first area having the high density and the second area having the low density, and Creating adjustment data for updating the change data of the first region and the second region and the etching condition for thinning the second insulating film based on the result. 5. The method of manufacturing a semiconductor device according to claim 3, wherein the method is a semiconductor device.
(Supplementary note 6) The method of manufacturing a semiconductor device according to supplementary note 5, wherein the film thickness is adjusted by etching the hard mask layer a plurality of times according to the adjustment data.
(Supplementary Note 7) The first region is a central portion of a dense region where the active region surrounded by the groove is formed relatively densely on the semiconductor substrate as compared with other regions. The method for manufacturing a semiconductor device according to appendix 1, wherein the region includes at least a peripheral region of the dense region.
(Supplementary note 8) The method for manufacturing a semiconductor device according to supplementary note 1 or supplementary note 5, wherein the second region includes at least one active region.
(Additional remark 9) The process of forming the area | region where the film thickness of the said 2nd insulating film is thicker than the said 1st area | region, and becomes thinner than the said 2nd area | region in the boundary of the said 1st area | region and the said 2nd area | region. The method for manufacturing a semiconductor device according to appendix 1, further comprising:

1 Silicon substrate (semiconductor substrate)
2 Hard mask layer 3 Base protective film (first insulating film)
4 Insulating protective film (second insulating film)
10, 10A, 10B, 40, 40A, 40B, 40C Hard mask 12 Element isolation insulating film (third insulating film)
CA1 Depopulated area (area where elements are not concentrated)
SA1 Second area TA1 Dense area (area where elements are concentrated)
TB1 peripheral area TC1 first area TC2 central area TC3 intermediate area

Claims (4)

Forming a first insulating film on the semiconductor substrate;
Forming a second insulating film on the first insulating film;
Etching so that the thickness of the first region of the second insulating film is thinner than the thickness of the second region located around the first region;
Etching the first region of the second insulating film, etching the second insulating film in the first region and the second region, and patterning the second insulating film When,
Etching the first insulating film and the semiconductor substrate using a mask formed by patterning the second insulating film, and forming a groove for forming an element isolation region in the semiconductor substrate; ,
A method for manufacturing a semiconductor device, comprising:   And a step of forming the element isolation regions in the plurality of grooves by polishing the third insulating film and the mask after the third insulating film is embedded in the plurality of grooves. A method for manufacturing a semiconductor substrate according to claim 1.   The thickness of the second insulating film is measured after the step of polishing the second insulating film, and the shape of the first region is changed according to the measurement result. Item 3. A method for manufacturing a semiconductor device according to Item 2.   After the step of polishing the second insulating film, the thickness of the second insulating film is measured, and the etching amount of the second insulating film in the first region is determined according to the measured result. The method of manufacturing a semiconductor device according to claim 2, wherein the method is changed.

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