JP2010198730A - Semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory device which sets the latency in the inside with an appropriate timing. <P>SOLUTION: A trigger producing circuit 104 outputs a trigger signal. A delay circuit 110 receives the trigger signal and outputs a delay signal by which the trigger signal is delayed. A clock counter 106 receives the clock and counts the number of received clocks, during the period from the time when the trigger signal is received, to the time the delay signal is received, then the counted result is output. A determination circuit 107 stores the correspondence relation between the number of clocks and the latency, and the latency corresponding to the counted result output from the clock counter is determined. A register 108 for latency holds the determined latency. A WAIT control circuit 109 outputs a WAIT signal to the outside, based on the latency held by the register 108 for latency. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device suitable for mounting on a portable terminal.

  A semiconductor memory device used in a portable terminal such as a cellular phone uses a pseudo SRAM in order to realize a large capacity and easy control. In a pseudo SRAM (Static Random Access Memory), a DRAM (Dynamic Random Access Memory) cell is used as an internal memory cell, and a clock similar to that of an SRAM is used as an external interface for defining input control signals and address signals. An asynchronous interface is used that is not synchronized with The refresh operation is not automatically controlled by an external signal, but is automatically performed internally (see, for example, Patent Document 1).

  Furthermore, in order to realize higher speed, for example, a synchronous pseudo SRAM in which a synchronous interface is added to a pseudo SRAM such as CellularRAM (R) described in Non-Patent Document 1 has been put into practical use. Yes. This synchronous pseudo SRAM includes a synchronous interface synchronized with a clock in addition to an asynchronous interface that does not synchronize with an SRAM-like clock.

  By the way, in the synchronous pseudo-SRAM, from the time when a command latency CL, which is the number of clocks from when a read or write request is received until the time when data is output, until the command latency CL elapses, from the outside It is notified by the WAIT signal that it cannot be accessed. Conventionally, the command latency CL is given from the outside, but it can be said that the synchronous pseudo SRAM can be notified from the inside by the WAIT signal that it cannot be accessed, so it is not necessary to give it from outside. Rather, it can be said that setting the command latency CL in the synchronous pseudo SRAM according to the state at that time can be set to a more appropriate value than setting from the outside.

  On the other hand, Patent Document 2 discloses a latency determination circuit capable of adjusting latency according to a clock frequency. The latency determination circuit includes a latency determination instruction input unit that issues an internal start signal in response to activation of a latency determination start signal that starts latency determination in synchronization with the clock signal, and a clock signal in response to the latency determination start signal. Latency interval definition circuit that generates a predetermined latency determination interval signal for each edge, a delay unit that generates a delay signal so as to adjust the latency by delaying the internal start signal for a predetermined time, and latency determination start when the delay signal is activated There is provided a latency instruction circuit that determines the number of latencies in response to the signal and the latency determination section signal. With such a latency determining circuit, the latency can be determined internally without depending on an external instruction.

For example, Patent Document 3 discloses a method of simultaneously executing self-refresh and reading or writing when the pseudo SRAM has a plurality of banks. That is, in paragraph [0020] of Patent Document 3, in the first to fourth row address latch circuits and buffers 80 to 83, one of the first to fourth cell banks 10 to 13 is in the refresh mode. However, the second row address signals A ₀ -A _n-2 latched by the row address latch circuit 70 can be transmitted to the remaining three cell banks to enable data access even during the refresh mode. .

JP 2002-352577 A JP 2001-155484 A JP 7-226077 A

CellularRAMTM Memory, Internet <URL: http://www.micron.com/products/psram/cellularram/>

  However, the methods described in the above-mentioned patent documents and non-patent documents have the following problems.

  First, Patent Document 2 describes a method for setting latency internally, but does not describe timing for setting latency.

  Patent Document 3 describes a method of performing refresh and read or write at the same time when a bank to be refreshed is different from a bank to be read or written, but does not overlap with a bank to be read or written. However, it does not describe how to determine the bank to be refreshed.

  In addition, when a plurality of pseudo SRAMs are accommodated in one package, refresh is performed at different timings, so that there is a problem that WAIT signals output from each other compete.

  There is also a problem that data cannot be output at a timing earlier than the timing defined by the command latency CL.

  In addition, when there are multiple modes such as synchronous mode and asynchronous mode, and one mode is selected to operate, even a preamplifier that operates properly in one mode is appropriate in other modes. In some cases, amplification does not work normally.

  In addition, when shifting to the next row during continuous reading or writing, processing for shifting to the next row by the WAIT signal from the outside (deactivation of the word line before transition, after transition) There is a problem that a byte mask signal must be given after knowing that word line activation and amplification by a sense amplifier have been completed.

  Further, in order to precharge the bit line pair, the chip enable signal must be deactivated from the outside, and there is a problem that external control is required.

  In addition, a semiconductor memory device such as CellularRAM (R) has a problem that it cannot be operated synchronously with a low-frequency clock.

  In addition, there is a problem that the input / output buffer continues to operate in a standby state or in an inactive chip that is accessing another chip and consumes current wastefully.

  SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a semiconductor memory device that internally sets latency at an appropriate timing.

  Another object of the present invention is to provide a semiconductor memory device that appropriately determines a bank to be refreshed so as not to overlap with a bank to be read or written.

  Still another object of the present invention is to provide a semiconductor memory device capable of performing refresh at the same timing when a plurality of pseudo SRAMs are accommodated in one package.

  Still another object of the present invention is to provide a semiconductor memory device that can output data at a timing earlier than the timing defined by the command latency CL.

  Still another object of the present invention is to provide a semiconductor memory device that has a plurality of modes, and when a single mode is selected to operate, the preamplifier operates properly in all modes. It is.

  Still another object of the present invention is to provide a byte mask signal from the outside in the same way as in the case of not shifting to the next row even when shifting to the next row during continuous reading or writing. It is an object to provide a semiconductor memory device capable of performing

  Still another object of the present invention is to provide a semiconductor memory device capable of precharging a bit line pair only by internal control without requiring external control.

  Still another object of the present invention is to provide a semiconductor memory device that can be operated in a synchronous manner with a low-frequency clock.

  Still another object of the present invention is to provide a semiconductor memory device in which an input / output buffer keeps operating in an inactive chip and prevents current from being consumed unnecessarily.

  In order to solve the above-described problems, a semiconductor memory device according to an aspect of the present invention is a semiconductor memory device that operates in synchronization with a clock, and includes a memory array having a plurality of memory cells arranged in a matrix, a trigger, A trigger generation circuit that outputs a signal, a delay circuit that receives a trigger signal and outputs a delay signal obtained by delaying the trigger signal, and a clock received and received the trigger signal until the delay signal is received A clock counter that counts the number of clocks and outputs a count result; a determination circuit that stores a correspondence relationship between the number of clocks and latency and determines a latency corresponding to the count result output from the clock counter; A wait signal is output to the outside based on the register holding the latency and the latency held in the register. And a wait control circuit.

  A semiconductor memory device according to another aspect of the present invention includes a memory array having a plurality of dynamic random access memory memory cells arranged in a matrix, a plurality of banks serving as a unit of one refresh, When receiving a refresh trigger and a circuit that outputs a trigger, when an externally designated operation is being executed, a bank different from the bank that is executing the operation is selected and the address of the selected bank is output A bank selection circuit and a refresh control circuit for performing a refresh of the bank of the received address. The bank selection circuit holds the addresses of the banks that have been refreshed, and when the addresses of all the banks are held, A register that erases all stored addresses and when a refresh trigger is received Compares the specific circuit that identifies the address of the bank that has not been refreshed with reference to the register, the bank address that has not been refreshed, and the bank address that is executing the operation, and if not, outputs the bank address that has not been refreshed And a comparison circuit.

  According to still another aspect of the present invention, a semiconductor memory device includes a memory array having a plurality of dynamic random access memory memory cells arranged in a matrix, and a first signal for generating a first signal defining refresh timing. A circuit, an output terminal for outputting a first signal, an input terminal for receiving a second signal for defining refresh timing from the outside, and receiving either the first signal or the second signal, And a second circuit that receives a signal output from the switch and performs refresh control based on the signal.

  A semiconductor memory device according to yet another aspect of the present invention operates in synchronization with a clock, performs access in a burst mode, and obtains a row address and a column address before a read signal or a write signal is generated. A semiconductor memory device having a plurality of memory cells arranged in a matrix and a selection in synchronization with a first clock in which a read signal or a write signal is generated by a control signal received from the outside The row access processing of the generated row and the column access processing of the first number of columns that are one or more from the head and less than the burst length are performed, and in synchronization with the clocks after the second clock specified by the latency, Control to control column access processing of remaining second number of columns of burst mode access And a road.

  A semiconductor memory device according to still another aspect of the present invention is a semiconductor memory device set to one of a plurality of operation modes by a combination of external signals, and includes a plurality of memory cells arranged on a matrix. A memory array, a bit line pair connected to each of the memory cells, a first amplifier circuit for amplifying the potential of the bit line pair, an IO line pair connected to the plurality of bit line pairs, and each mode And two or more second amplification circuits that amplify the potential of the IO line pair.

  A semiconductor memory device according to still another aspect of the present invention is a semiconductor memory device that operates in synchronization with a clock and receives a memory array having a plurality of memory cells arranged in a matrix and a byte mask signal from the outside. The byte mask control circuit for controlling the byte mask processing based on the byte mask signal and the data output from the memory cell are received, and the byte mask signal of the data output from the memory cell is received according to the instruction from the byte mask control circuit. An output circuit that does not output the corresponding byte, and the byte mask control circuit includes a first row and a second row in the middle when continuous reading or writing is performed over two rows of the first row and the second row. Since the last column has been reached, the row mask signal is received from the outside while row access processing is being performed to shift to the second row. When subjected to the mask processing of bytes corresponding to the byte mask signal, row access is completed, extended to timing data of the next bit is output.

  A semiconductor memory device according to still another aspect of the present invention is a semiconductor memory device that operates in synchronization with a clock, and includes a memory array having a plurality of memory cells arranged in a matrix, and bits connected to the memory cells. A burst length counter that outputs a burst length reset signal at the next clock after receiving a line pair, a column selection signal, and a selection signal for selecting the last column of burst access is activated, and a burst length reset signal And a control circuit for precharging the bit line pair.

  A semiconductor memory device according to still another aspect of the present invention is a semiconductor memory device having a synchronous mode that operates in synchronization with a clock and an asynchronous mode that operates asynchronously, and a plurality of memory cells arranged in a matrix Having a memory array, a synchronous fixed mode, an asynchronous fixed mode, a setting circuit that can be set to either synchronous or asynchronous mixed mode, and an external chip enable signal in Investigate whether the time to rise is greater than or equal to a predetermined value, and when it is greater than or equal to the predetermined value, the asynchronous transition circuit that shifts to the asynchronous fixed mode and the synchronization that controls the synchronous operation when set to the synchronous fixed mode or mixed mode When the control circuit and asynchronous fixed mode or mixed loading mode are set, or when the asynchronous fixed mode is entered And a asynchronous control circuit for controlling an asynchronous operation, an asynchronous shifting circuit is deactivated in response to the output of the setting circuit.

  A semiconductor memory device according to still another aspect of the present invention is a semiconductor memory device that operates in synchronization with a clock, and receives a memory array having a plurality of memory cells arranged in a matrix and an external chip enable signal. A chip enable buffer for generating an internal chip enable signal; a clock buffer for receiving an external clock to generate an internal clock; an address buffer for receiving an external address signal to generate an internal address signal; and an external control other than the external chip enable signal A control buffer that receives the signal and generates an internal control signal. The clock buffer, the address buffer, and the control buffer receive the internal chip enable signal, and when the internal chip enable signal indicates that the chip is inactive, Stop operation, clock buffer, address The buffer and the control buffer execute an operation when the internal chip enable signal indicates activation, the control buffer receives the external address capture signal and generates an internal address capture signal, and the semiconductor memory device Furthermore, a delay circuit that delays the internal address fetch signal by a predetermined delay amount, a clocked inverter that receives the output of the delay circuit and the internal clock, and a logical product signal of the output of the clocked inverter and the internal clock are output. And a circuit that activates the row address strobe signal based on the first pulse of the logical product signal, and the first pulse of the logical product signal rises while the external address fetch signal is activated A predetermined delay amount of the delay circuit is determined to be an internal clock pulse generated from the external clock pulse.

  According to the semiconductor memory device according to an aspect of the present invention, the latency can be set internally at an appropriate timing.

  Further, according to the semiconductor memory device according to another aspect of the present invention, it is possible to appropriately determine the bank to be refreshed so as not to overlap with the bank to be read or written.

  Also, according to the semiconductor memory device according to still another aspect of the present invention, refreshing can be performed at the same timing when a plurality of pseudo SRAMs are accommodated in one package.

  In addition, according to the semiconductor memory device according to still another aspect of the present invention, data can be output at a timing earlier than the timing defined by the command latency.

  According to another aspect of the semiconductor memory device of the present invention, when there are a plurality of modes and one mode is selected to operate, the preamplifier operates properly in all modes. be able to.

  In addition, according to the semiconductor memory device according to still another aspect of the present invention, even when shifting to the next row in the middle of continuous reading or writing, from the outside, as in the case of not shifting to the next row. A byte mask signal can be provided.

  Further, according to the semiconductor memory device according to still another aspect of the present invention, the bit line pair can be precharged only by internal control without requiring external control.

  Further, according to the semiconductor memory device according to still another aspect of the present invention, the semiconductor memory device can be operated in a synchronous manner with a low-frequency clock.

  In addition, according to the semiconductor memory device according to still another aspect of the present invention, it is possible to prevent the input / output buffer from continuously operating in the inactive chip and consuming unnecessary current.

1 is a diagram showing a configuration of a synchronous pseudo SRAM 100 according to a first embodiment. 3 is a diagram illustrating a detailed configuration of a trigger generation circuit 104. FIG. 4 is a timing chart of signals generated by a trigger generation circuit 104. It is a figure which shows the structure of the synchronous pseudo SRAM 200 which concerns on 2nd Embodiment. 5 is a diagram showing a detailed configuration of a refresh bank address designating circuit 213. FIG. It is a figure for demonstrating operation | movement of the conventional synchronous pseudo SRAM. It is a figure for demonstrating the operation example of the synchronous pseudo SRAM200 which concerns on 2nd Embodiment. It is a figure for demonstrating another operation example of the synchronous pseudo SRAM 200 which concerns on 2nd Embodiment. It is a figure which shows the structure of each synchronous pseudo SRAM300 accommodated in one package which concerns on 3rd Embodiment. 3 is a diagram showing a detailed configuration of a refresh control circuit 305. FIG. It is a figure which shows the structure of the package which accommodated two synchronous pseudo | simulation SRAMs concerning 3rd Embodiment. It is a figure which shows the structure of the synchronous pseudo SRAM400 which concerns on 4th Embodiment. 2 is a diagram illustrating a configuration of a row control circuit 409. FIG. 2 is a diagram showing a configuration of a column control circuit 407. FIG. 3 is a diagram showing a detailed configuration of a CDETRG generator 421. FIG. 3 is a diagram illustrating a configuration of a WAIT control circuit 412. FIG. It is a figure showing the timing of the WAIT signal of the conventional synchronous pseudo SRAM. It is a figure showing the timing of the WAIT_ASYN signal and the WAIT signal of the synchronous pseudo SRAM 400 according to the fourth embodiment. 5 is a diagram showing a configuration of a column decoder 417. FIG. 14 is a timing chart illustrating an operation of the synchronous pseudo SRAM 400 according to the fourth embodiment. 2 is a diagram illustrating a configuration of a row control circuit 499. FIG. 6 is a diagram illustrating input / output signals of a command shift circuit 480. FIG. 5 is a diagram showing a detailed configuration of a command shift circuit 480. FIG. (A) is a diagram showing a modified read signal READF when the read signal READ is input when the refresh operation is not performed, and (b) is when the read signal READ is input during the refresh operation. FIG. 6 is a diagram illustrating a modified read signal READF. It is a figure which shows the structure of the synchronous pseudo SRAM 500 which concerns on 5th Embodiment. 5 is a diagram illustrating a configuration of a common signal generation circuit 507. FIG. (A) is a timing chart in which the synchronization instruction signal SYNC is generated when the external clock CLK is input. (B) is a timing chart in which the synchronization instruction signal SYNC is generated when the external clock CLK is not input. It is a figure which shows a timing chart. 5 is a diagram showing a configuration of a synchronization-compatible preamplifier control circuit 508. FIG. 3 is a diagram illustrating a configuration of a reference signal generator 521. FIG. It is a figure which shows an example of the High side Delay. 5 is a diagram showing a configuration of a synchronization-compatible preamplifier control signal generator 522. FIG. It is a figure which shows the timing at which the signal relevant to the synchronization corresponding preamplifier 512 is produced | generated. 5 is a diagram illustrating a configuration of an asynchronous preamplifier control circuit 509. FIG. It is a figure which shows the timing which the signal relevant to the asynchronous preamplifier 513 is produced | generated. 2 is a diagram showing a configuration of a synchronization-compatible preamplifier 512. FIG. It is a figure for demonstrating that the synchronous corresponding | compatible preamplifier 512 is not suitable for asynchronous reading. 5 is a diagram showing a configuration of an asynchronous preamplifier 513. FIG. FIG. 6 is a diagram showing a time change in potential of each node of an asynchronous preamplifier 513. 5 is a diagram illustrating a configuration of a synchronization-compatible DB driver 514. FIG. 3 is a diagram illustrating a configuration of an asynchronous DB driver 516. FIG. It is a figure which shows the structure of the shared DB driver 590 which serves as the synchronous corresponding | compatible DB driver 514 and the asynchronous corresponding | compatible DB driver 515. FIG. FIG. 5 is a diagram showing the arrangement of synchronous preamplifiers 512 and asynchronous preamplifiers 513. FIG. 10 is a diagram illustrating another arrangement of a synchronous preamplifier 512 and an asynchronous preamplifier 513. It is a figure which shows the structure of the synchronous pseudo SRAM600 which concerns on 6th Embodiment. 3 is a diagram illustrating a detailed configuration of a CE buffer 609. FIG. It is a figure which shows the detailed structure of the UB buffer 605. It is a figure which shows the detailed structure of the ZUB0 production | generation circuit 613. FIG. 3 is a diagram illustrating a detailed configuration of a ZLB0 generation circuit 614. FIG. 5 is a diagram illustrating a detailed configuration of an ADV0 generation circuit 615. FIG. 3 is a diagram illustrating a detailed configuration of a ZWE0 generation circuit 616. FIG. 3 is a diagram illustrating a detailed configuration of a ZRST generation circuit 612. FIG. It is a figure showing the timing at which ZRST is produced | generated. 5 is a diagram showing a detailed configuration of a mask control circuit 617. FIG. It is a timing chart showing a change of a signal when not accompanied with the shift to the next row at the time of burst reading in the synchronous pseudo SRAM 600 according to the sixth embodiment. 16 is a timing chart showing a signal change when accompanied by a transition to the next row during burst reading when the no-wrap mode is set in the synchronous pseudo SRAM 600 according to the sixth embodiment. It is a figure which shows the structure of RAM700 which concerns on 7th Embodiment. 6 is a diagram illustrating a configuration of a common unit 702. FIG. It is a figure which shows the structure of the cellular RAM exclusive part 704. FIG. It is a figure which shows the structure of the mobile RAM exclusive part 703. FIG. It is a figure which shows the structure of the synchronous pseudo SRAM 800 which concerns on 8th Embodiment. A detailed configuration of the burst length counter 805 is shown. It is a figure which shows the timing chart in which a word line is deactivated. It is a figure showing the setting method of the conventional synchronous / asynchronous mode. (A) is a figure for demonstrating the mode setting when tCSP is 7.5 ns, (b) is a figure for demonstrating the mode setting when tCSP is 22.5 ns. It is a figure showing the setting method of the synchronous / asynchronous mode of 9th Embodiment. It is a figure which shows the structure of the synchronous pseudo SRAM 900 which concerns on 9th Embodiment. It is a figure which shows the structure of the synchronous pseudo SRAM1000 which concerns on 10th Embodiment. FIG. 11 is a diagram showing a configuration of a conventional ADV0 generation circuit 1050. It is a figure showing the change timing of each signal when the conventional ADV0 generation circuit 1050 is used. It is a figure which shows the structure of the ADV0 generation circuit 1010 of this Embodiment. It is a figure showing the timing of the change of each signal when ADV0 generation circuit 1010 of this Embodiment is used. FIG. 12 is a diagram showing that the precharge timing is delayed when the external chip enable signal CE # is deactivated asynchronously.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[First Embodiment]
The present embodiment relates to a synchronous pseudo SRAM that automatically sets latency to an appropriate value internally at an appropriate timing.
(Constitution)
FIG. 1 shows a configuration of a synchronous pseudo SRAM 100 according to the present embodiment. Referring to FIG. 1, this synchronous pseudo SRAM 100 includes a DRAM cell array + peripheral circuit group 101, an address buffer 103, and a control circuit 102.

  The DRAM cell array of the DRAM cell array + peripheral circuit group 101 is a memory array made up of dynamic random access memory (DRAM) cells. The peripheral circuit group 101 includes a global input / output line pair GIOP (GIO and / GIO), a column selection line provided corresponding to each column, a column selection gate, a sense amplifier, a preamplifier, a write driver, Includes a row decoder, column decoder, and the like.

  The address buffer 103 receives the external address signal ADD [21: 0] and generates an internal address signal.

  The control circuit 102 includes a trigger generation circuit 104, a counter enable circuit 105, a clock counter 106, a determination circuit 107, a latency register 108, a WAIT control circuit 109, a delay circuit 110, and a refresh control circuit 111. Including.

  The refresh control circuit 111 controls the self-refresh operation of the DRAM cell array based on an internal refresh timer (not shown).

  The trigger generation circuit 104 outputs a trigger signal Trigger that serves as a latency setting trigger.

  The delay circuit 110 includes a plurality of stages of inverters, receives a trigger signal Trigger, and outputs a delay trigger signal dTrigger.

  The counter enable circuit 105 sets the counter enable signal CE to “H” from when the trigger signal Trigger is input until the delayed trigger signal dTrigger is input.

  The clock counter 106 counts the number of external clocks CLK input while the counter enable signal CE is “H”. The count number depends on the number of input external CLKs and the period when the counter enable signal CE is “H”, that is, the delay amount of the trigger signal Trigger in the delay circuit 110. The amount of delay in the delay circuit 110 depends on the surrounding environment such as temperature.

  The determination circuit 107 stores a correspondence relationship between the count number of the clock and the minimum latency operable with the count number. The correspondence relationship is determined so that the minimum latency increases as the clock count number increases. Based on this correspondence, the determination circuit 107 determines the minimum latency according to the count number output from the clock counter 106, and outputs it to the latency register 108.

  The latency register 108 stores the minimum latency sent from the determination circuit 107.

  The WAIT control circuit 109 sets the WAIT signal to “L” only for a period corresponding to the minimum latency stored in the latency register 108.

  FIG. 2 shows a detailed configuration of the trigger generation circuit 104. As shown in the figure, the trigger generation circuit 104 includes a latch circuit 121, inverters IV1, IV2, IV3, and an AND circuit AND1.

  FIG. 3 is a timing chart of signals generated by the trigger generation circuit 104. Referring to FIG. 9, latch circuit 121 latches external address take-in signal ADV # and outputs address take-in latch signal ADV # L. The latch circuit 121 latches the external chip enable signal CE # and outputs a chip enable latch signal CE # L. The latch circuit 121 latches the external write enable signal WE # and outputs a write enable latch signal WE # L. The latch circuit 121 latches the external configuration register enable signal CRE # and outputs a configuration register enable latch signal CREL. In the AND circuit 1, the address fetch latch signal ADV # L is “L”, the chip enable latch signal CE # L is “L”, the write latch signal WE # L is “H”, and the configuration register enable latch signal CREL is “ When “L” and the external clock CLK is “H”, the read signal READ is activated to “H” and the trigger signal Trigger is set to “H”.

  When such a trigger signal generation circuit 104 generates a read signal READ by a combination of logical values of external signals and performs reading, the trigger signal Trigger is also generated at the same time and the latency is set.

  As described above, according to the synchronous pseudo SRAM according to the present embodiment, the read signal READ is generated, and the external clock CLK input at the timing when the command latency is actually required for the read process. The latency can be set to the minimum value that can operate under ambient conditions such as frequency and temperature.

  In the present embodiment, the delay circuit 101 is composed of a plurality of inverters. However, the present invention is not limited to this. For example, a replica circuit that simulates a specific circuit is used. May be. The clock counter 106 may receive an internal clock instead of receiving the external clock CLK.

  Further, the present embodiment is not limited to the synchronous pseudo SRAM, and can be applied to any semiconductor memory device that operates in synchronization with a clock.

[Modification of First Embodiment]
In the first embodiment, the trigger generation circuit 104 detects the generation of the read signal READ and generates the trigger signal Trigger. However, the present invention is not limited to this. For example, the trigger signal Trigger may be generated in the following cases.

  (1) Detecting that another operation instruction signal such as the write signal WRITE is input, and generating a trigger signal Trigger.

  (2) When the power-on detection circuit detects that the power is turned on, the trigger signal Trigger is generated.

  (3) When the operation mode setting command determination circuit determines that mode setting such as latency and burst length has been performed by an external signal, a trigger signal is generated.

  (4) When a temperature change is detected by the temperature change detection circuit, a trigger signal Trigger is generated.

(5) The trigger signal Trigger is generated at a constant cycle by the internal transmission circuit.
[Second Embodiment]
The present embodiment relates to a synchronous pseudo SRAM in which a WAIT period is shortened by appropriately switching a bank to be self-refreshed.

(Constitution)
FIG. 4 shows a configuration of the synchronous pseudo SRAM 200 according to the present embodiment. Referring to FIG. 2, this synchronous pseudo SRAM 200 includes a DRAM cell array + peripheral circuit group 201 and a control circuit 202.

  The DRAM cell array of the DRAM cell array + peripheral circuit group 201 is a memory array composed of dynamic random access memory (DRAM) cells, and has four banks. A bank is a group of memory cells obtained by dividing a DRAM cell array and serves as a unit for one refresh operation. That is, in one refresh, one bank is refreshed.

  The peripheral circuit group includes a global input / output line pair GIOP (GIO and / GIO), a column selection line provided corresponding to each column, a column selection gate, a sense amplifier, a preamplifier, a write driver, Includes decoders, column decoders, etc.

  The control circuit 202 includes a command decoder 214, a refresh bank address designating circuit 213, a refresh timer 212, a refresh control circuit 211, and a WAIT control circuit 215.

  The command decoder 214 generates a row activation signal ACT, a read signal READ, and a write signal WRITE according to the combination of the logic levels of the internal control signals generated from the external control signal.

  Refresh timer 212 is formed of a ring oscillator and outputs a periodically activated refresh cycle signal / Refcyc.

  Refresh bank address designating circuit 213 receives refresh cycle signal / Refcyc, read signal READ or write signal WRITE, and bank address, and designates the address of the bank to be refreshed and its refresh timing.

  When the refresh control circuit 211 receives only the bank address from the refresh bank address designating circuit 213, it immediately controls the refresh operation of the bank at that address. When the refresh control circuit 211 receives a command to refresh after completion of the reading operation of the bank at the bank address together with the bank address from the refresh bank address designating circuit 213, the refresh control circuit 211 refreshes the bank after a predetermined time elapses. Control the behavior.

  The WAIT control circuit 215 sets the level of the WAIT signal to “L” while the refresh control circuit 211 controls the refresh operation.

  FIG. 5 shows a detailed configuration of the refresh bank address designating circuit 213. Referring to the figure, refresh bank address designating circuit 213 includes OR circuit 221, bank address counter 222, refreshed / unexecuted determination circuit 223, refreshed bank holding circuit 224, and first comparison circuit. 225, a second comparison circuit 227, and a read / write operation bank detection circuit 226.

  The OR circuit 221 receives the refresh cycle signal / Refcyc from the refresh timer 212, the signal NEXT indicating the next bank from the refreshed / unexecuted determination circuit 223, or the signal NEXT indicating the next bank from the first comparison circuit 225. And a count-up signal is output.

  When the bank address counter 222 receives the count up signal, the bank address counter 222 increases the count in the range of “1” to “4”. However. The initial value of the count value is “0”, and the count “4” is followed by the count “1”.

  The refreshed bank holding circuit 224 holds the bank address that has been refreshed. When all the bank addresses “1” to “4” are held, the refreshed bank holding circuit 224 erases all the held bank addresses and sets the count value of the bank address counter 222 to “0”. Reset it. Therefore, all the refreshes of bank 1 to bank 4 are completed in four refreshes.

  The refresh execution / non-execution determination circuit 223 checks whether or not the bank address of the counter value of the bank address counter 222 is held in the refreshed bank holding circuit 224. When the bank address of the counter value is not held, the refresh execution / non-execution determination circuit 223 determines that the refresh has not been performed, and sets the bank address to either the first comparison circuit 225 or the second comparison circuit 227. Output. Here, when the bank address to be output is the last bank address that is not held in the refreshed bank holding circuit 224, the refreshed / unexecuted judging circuit 223 sends the bank address to the second comparing circuit 227. Is output. The refresh execution / non-execution determination circuit 223 outputs the bank address to the first comparison circuit 225 in cases other than the above.

  When the bank address of the counter value is held, the refresh execution / non-execution determination circuit 223 determines that the refresh has been performed and outputs a signal NEXT indicating the next bank address.

  When the read / write operation bank detection circuit 226 receives the read signal READ or the write signal WRITE, the bank address (the address of the bank that is reading or writing) is input to the first comparison circuit 225 and the second comparison circuit. Output to the circuit 227.

  First comparison circuit 225 checks whether or not the two bank addresses received from read / write operation bank detection circuit 226 and refresh execution / non-execution determination circuit 223 are the same. When the two bank addresses are different, the first comparison circuit 225 sends the bank address received from the refresh execution / non-execution determination circuit 223 to the refresh control circuit 211, and sends the bank address to the refreshed bank holding circuit 224. Output and hold. When the two bank addresses are the same, first comparison circuit 225 outputs signal NEXT indicating the next bank address.

  Second comparison circuit 227 checks whether the two bank addresses received from read / write operation bank detection circuit 226 and refresh execution / non-execution determination circuit 223 are the same. When the two bank addresses are different, the second comparison circuit 227 sends the bank address received from the refresh execution / non-execution determination circuit 223 to the refresh control circuit 211, and sends the bank address to the refreshed bank holding circuit 224. Output and hold. When the two bank addresses are the same, second comparison circuit 227 issues a bank address received from refresh execution / non-execution determination circuit 223 and a command to perform refresh after the bank reading operation of the bank address is completed. The data is sent to the refresh control circuit 211.

(Example of operation of a conventional synchronous pseudo SRAM)
First, the operation of a conventional synchronous pseudo SRAM will be described for comparison of the operation of the synchronous pseudo SRAM 200 according to the present embodiment.

  FIG. 6 is a diagram for explaining the operation of a conventional synchronous pseudo SRAM. As shown in the figure, when the refresh timer outputs the refresh cycle signal / Refcyc while the read operation is being performed based on the read signal READ according to the external instruction, the refresh control circuit performs the read operation being executed. After the end of, the control of the refresh operation is started. The WAIT control circuit outputs a WAIT signal to the outside during the refresh operation.

  Therefore, in the conventional synchronous pseudo SRAM, when the timing of the read operation and the timing of the self-refresh overlap, the self-refresh timing is delayed, and a read instruction is issued from the outside until the self-refresh is completed. Can not.

(Operation example 1 of the synchronous pseudo SRAM 200 of the present embodiment)
FIG. 7 is a diagram for explaining an operation example of the synchronous pseudo SRAM 200 according to the present embodiment.

  First, a read operation of bank 2 is performed based on a read signal READ designating bank 2 from the outside.

  Next, a read operation of bank 3 is performed based on a read signal READ designating bank 3 from the outside. During the read operation of bank 3, refresh timer 212 outputs refresh cycle signal / Refcyc. When receiving the refresh cycle signal / Refcyc, the OR circuit 221 in the refresh bank address designating circuit 213 outputs a count up signal. The bank address counter 222 sets the count value of the bank address to “1”. The refresh execution / non-execution determination circuit 223 determines that it has not been executed yet because the refresh execution bank holding circuit 224 has not yet held anything, and outputs the bank address “1” to the first comparison circuit 225. The read / write operation bank detection circuit 226 receives the read signal READ and the bank address “3”, and outputs the bank address “3” to the first comparison circuit 225 and the second comparison circuit 227. Since the received two bank addresses are different, the first comparison circuit 225 sends the bank address “1” received from the refresh execution / non-execution determination circuit 223 to the refresh control circuit 211 and at the same time the refreshed bank holding circuit 224. Output and hold the bank address “1”. Upon receiving the bank address “1”, the refresh control circuit 211 controls the refresh operation of the bank 1.

  Next, the read operation of bank 1 is performed based on the read signal READ designating bank 1 from the outside.

  Next, the read operation of bank 2 is performed based on read signal READ designating bank 2 from the outside. During the read operation of bank 2, refresh timer 212 outputs refresh cycle signal / Refcyc. When receiving the refresh cycle signal / Refcyc, the OR circuit 221 in the refresh bank address designating circuit 213 outputs a count-up signal. The bank address counter 222 sets the count value of the bank address to “2”. Since the refreshed bank holding circuit 224 holds only the bank address “1” and does not hold the bank address “2”, the refreshed / unexecuted determination circuit 223 determines that the bank has not been executed, The address “2” is output to the first comparison circuit 225. The read / write operation bank detection circuit 226 receives the read signal READ and the bank address “2”, and outputs the bank address “2” to the first comparison circuit 225 and the second comparison circuit 227. Since the received two bank addresses are the same, the first comparison circuit 225 outputs a signal NEXT indicating the next bank.

  The OR circuit 221 outputs a count-up signal when it receives a signal NEXT indicating the next bank. The bank address counter 222 sets the count value of the bank address to “3”. Since the refreshed bank holding circuit 224 holds only the bank address “1” and does not hold the bank address “3”, the refreshed / unexecuted determination circuit 223 determines that the bank has not been executed, The address “3” is output to the first comparison circuit 225. The read / write operation bank detection circuit 226 receives the read signal READ and the bank address “2”, and outputs the bank address “2” to the first comparison circuit 225 and the second comparison circuit 227. Since the received two bank addresses are different, the first comparison circuit 225 sends the bank address “3” received from the refreshed / unexecuted determination circuit 223 to the refresh control circuit 211 and also performs the refreshed bank holding circuit 224. Output and hold the bank address “3”. Upon receiving the bank address “3”, the refresh control circuit 211 controls the refresh operation of the bank 3.

  Next, the read operation of bank 4 is performed based on read signal READ designating bank 4 from the outside.

  Next, the read operation of bank 1 is performed based on the read signal READ designating bank 1 from the outside. During the read operation of bank 1, refresh timer 212 outputs refresh cycle signal / Refcyc. When receiving the refresh cycle signal / Refcyc, the OR circuit 221 in the refresh bank address designating circuit 213 outputs a count up signal. The bank address counter 222 sets the count value of the bank address to “4”. The refreshed bank holding circuit 224 holds only the bank addresses “1” and “3”, and does not hold the bank address “4”. The bank address “4” is output to the first comparison circuit 225. The read / write operation bank detection circuit 226 receives the read signal READ and the bank address “1” and outputs the bank address “1” to the first comparison circuit 225 and the second comparison circuit 227. Since the received two bank addresses are different, the first comparison circuit 225 sends the bank address “4” received from the refreshed / unexecuted determination circuit 223 to the refresh control circuit 211 and also performs the refreshed bank holding circuit 224. Output and hold the bank address “4”. Upon receiving the bank address “4”, the refresh control circuit 211 controls the refresh operation of the bank 4.

  Next, a read operation of bank 3 is performed based on a read signal READ designating bank 3 from the outside.

  Next, the read operation of bank 4 is performed based on read signal READ designating bank 4 from the outside. During the read operation of bank 4, refresh timer 212 outputs refresh cycle signal / Refcyc. When receiving the refresh cycle signal / Refcyc, the OR circuit 221 in the refresh bank address designating circuit 213 outputs a count up signal. The bank address counter 222 sets the count value of the bank address to “1” (cyclically updated). Since the bank addresses “1”, “3”, and “4” are held in the refreshed bank holding circuit 224, the refreshed / unexecuted determination circuit 223 determines that the bank has been executed and sets the next bank. An instructing signal NEXT is output.

  The OR circuit 221 outputs a count-up signal when it receives a signal NEXT indicating the next bank. The bank address counter 222 sets the count value of the bank address to “2”. Since the bank address “1”, “3”, “4” is held in the refreshed bank holding circuit 224 and the bank address “2” is not held, the refreshed / unexecuted determination circuit 223 The bank address “2” is output to the second comparison circuit 227 by determining that it has not been executed. Here, the bank address “2” is output to the second comparison circuit 227 instead of the first comparison circuit 225 because the bank address “2” among the bank addresses “1” to “4” is not yet implemented. Because it is the last bank. The read / write operation bank detection circuit 226 receives the read signal READ and the bank address “4”, and outputs the bank address “4” to the first comparison circuit 225 and the second comparison circuit 227. Since the received two bank addresses are different, the second comparison circuit 227 sends the bank address “2” received from the refreshed / unexecuted determination circuit 223 to the refresh control circuit 211 and also performs the refreshed bank holding circuit 224. Output and hold the bank address “2”. Upon receiving the bank address “2”, the refresh control circuit 211 controls the refresh operation of the bank 2.

  When the refreshed bank holding circuit 224 holds all the bank addresses “1” to “4”, it erases the held bank address and sets the count value of the bank address to “0” in the bank address counter 222. To reset.

(Operation example 2 of refresh bank address command circuit)
FIG. 8 is a diagram for explaining another example of operation of the synchronous pseudo SRAM 200 according to the present embodiment.

  A process when the read signal READ designating the bank 2 is inputted instead of the read signal READ designating the bank 4 from the outside at the last stage of the operation example 1 will be described.

  Based on the read signal READ designating the bank 2 from the outside, the read operation of the bank 2 is performed. During the read operation of bank 2, refresh timer 212 outputs refresh cycle signal / Refcyc. When receiving the refresh cycle signal / Refcyc, the OR circuit 221 in the refresh bank address designating circuit 213 outputs a count up signal. The bank address counter 222 sets the count value of the bank address to “1” (cyclically updated). Since the bank addresses “1”, “3”, and “4” are held in the refreshed bank holding circuit 224, the refreshed / unexecuted determination circuit 223 determines that the bank has been executed and sets the next bank. An instructing signal NEXT is output.

  The OR circuit 221 outputs a count-up signal when it receives a signal NEXT indicating the next bank. The bank address counter 222 sets the count value of the bank address to “2”. Since the bank address “1”, “3”, “4” is held in the refreshed bank holding circuit 224 and the bank address “2” is not held, the refreshed / unexecuted determination circuit 223 The bank address “2” is output to the second comparison circuit 227 by determining that it has not been executed.

  Here, the bank address “2” is output to the second comparison circuit 227 instead of the first comparison circuit 225 because the bank address “2” among the bank addresses “1” to “4” is not yet implemented. Because it is the last bank. The read / write operation bank detection circuit 226 receives the read signal READ and the bank address “2”, and outputs the bank address “2” to the first comparison circuit 225 and the second comparison circuit 227. Since the received two bank addresses are the same, second comparison circuit 227 receives bank address “2” received from refresh execution / non-execution determination circuit 223 and a command to perform refresh after the read operation of bank 2 is completed. Is sent to the refresh control circuit 211, and the bank address “2” is output and held in the refreshed bank holding circuit 224. When the refresh control circuit 211 receives the bank address “2” and a command to perform refresh after the read operation of the bank 2, the refresh control circuit 211 controls the refresh operation of the bank 2 after a predetermined time has elapsed.

  When the refreshed bank holding circuit 224 holds all the bank addresses “1” to “4”, it erases the held bank address and sets the count value of the bank address to “0” in the bank address counter 222. To reset.

  As described above, according to the synchronous pseudo SRAM according to the present embodiment, a bank that does not overlap with a bank that performs reading or writing and that is not refreshed is determined to be refreshed. Can be refreshed without delay and at a fair frequency.

  In the present embodiment, the refresh of all four banks is completed in four self refreshes such as 1 to 4 times and 5 to 8 times. However, the present invention is limited to this. is not. For example, all four refreshes may be completed every eight self-refreshes. In this case, in the operation example 2, it is possible not to delay the self refresh timing of the fourth bank 2. Further, the external system side may be able to designate a bank address schedule to be read prior to the read signal READ. In this case, the bank address schedule to be refreshed can be set so as not to overlap with the reading of the bank address designated by the schedule and so that the number of refreshes is equal in all banks.

  In the operation example of the present embodiment, the case where the refresh request is generated during the read operation has been described. However, the case where the refresh request is generated during the write operation is similarly processed.

  Further, the present embodiment is not limited to the synchronous pseudo SRAM, and can be applied to a pseudo SRAM that does not operate in synchronization with the clock.

[Third Embodiment]
The present embodiment relates to a configuration in which a plurality of synchronous pseudo SRAMs are accommodated in one package, and the refresh timings of the plurality of synchronous pseudo SRAMs are made the same.

(Constitution)
FIG. 9 shows a configuration of each synchronous pseudo SRAM 300 accommodated in one package according to the present embodiment. This synchronous pseudo SRAM 300 includes a refresh timer 301, a control circuit 302, a DRAM cell array + peripheral circuit group 303, and a switch 304.

  The DRAM cell array of the DRAM cell array + peripheral circuit group 303 is a memory array composed of dynamic random access memory (DRAM) cells. The peripheral circuit group includes a global input / output line pair GIOP (GIO and / GIO), a column selection line provided corresponding to each column, a column selection gate, a sense amplifier, a preamplifier, a write driver, Includes decoders, column decoders, etc.

  The control circuit 302 receives an external control signal via the control signal terminal 315 and receives write data to the DRAM cell array via the data input / output terminal 316, and based on these, processes of the entire synchronous pseudo SRAM 300 are performed. And reading data read from the DRAM cell array via the data input / output terminal 316. The control circuit 302 includes a refresh control circuit 305 and a WAIT control circuit 306.

  Refresh timer 301 outputs a refresh cycle signal / Refcyc composed of a ring oscillator and periodically activated to switch 304 and refresh timer output PAD 311. The refresh cycle signal / Refcyc supplied to the refresh timer output PAD 311 is sent to another synchronous pseudo SRAM.

  Refresh timer input PAD 312 receives refresh cycle signal / Refcyc from the refresh timer of another synchronous pseudo SRAM.

  The bonding option PAD 313 controls the switch 304 in accordance with the applied potential.

  Switch 304 receives refresh cycle signal / Refcyc from refresh timer 301 and refresh cycle signal / Refcyc from refresh timer input PAD 312. The two refresh cycle signals / Refcyc have the same period but different timings.

  The switch 304 outputs one of the received refresh cycle signals / Refcyc to the refresh control circuit 305 in accordance with the applied potential of the bonding option PAD313. That is, the switch 304 outputs the refresh cycle signal / Refcyc from the refresh timer input PAD 312 when a ground potential is applied to the bonding option PAD 313, and from the refresh timer 301 when a potential other than the ground potential is applied. The refresh cycle signal / Refcyc is output.

The refresh control circuit 305 controls self refresh.
FIG. 10 shows a detailed configuration of the refresh control circuit 305. Referring to the figure, refresh control circuit 305 includes command signal activation circuit 50, determination circuit 60, NAND gates 41 and 44, inverter 42, buffer 48, delay circuits 43 and 49, and flip-flops. 45.

  The command signal activation circuit 50 outputs a refresh flag signal Refflag in order to activate the refresh command signal / REFE. The determination circuit 60 outputs a determination signal Refwin to determine whether or not to output a refresh command signal / REFE activated by the refresh flag signal Reffflag.

  The NAND gate 41 receives the refresh flag signal Refflag and the determination signal Refwin, calculates a logical product of the refresh flag signal Refflag and the determination signal Refwin, and outputs a signal obtained by inverting the calculation result as an inverted logical product signal / REFSF. .

  Inverter 42 receives signal / REFSF output from NAND gate 41 and outputs inverted signal φA1. The delay circuit 43 receives the inverted AND signal / REFSF and delays it for a predetermined time.

  NAND gate 44 receives output signal .phi.A1 of inverter 42 and the output signal of delay circuit 43, calculates the logical product of signal .phi.A1 and the output signal of delay circuit 43, and outputs a signal / REFS obtained by inverting the calculation result. .

  The flip-flop 45 is composed of NAND gates 46 and 47. NAND gate 46 receives signal / REFS and output signal φA3 output from NAND gate 47, calculates a logical product of signal / REFS and signal φA3, and outputs signal φA2 obtained by inverting the calculation result. NAND gate 47 receives signal φA2 output from NAND gate 46 and signal φA4 output from delay circuit 49, calculates the theoretical product of signal A2 and signal A4, and refreshes the signal obtained by inverting the calculation result. Output as signal / REFE. A refresh operation is performed in response to activation of refresh command signal / REFE.

  Delay circuit 49 receives refresh command signal / REFE output from flip-flop 45 and outputs signal φA4 delayed for a predetermined time.

Buffer 48 receives signal φA3 and outputs refresh command signal / REFE.
Command signal activation circuit 50 includes a flip-flop 52, a NAND gate 55, inverters 56 and 57, and a delay circuit 58.

  The flip-flop 52 is composed of NAND gates 53 and 54. NAND gate 53 receives refresh cycle signal / Refcyc and output signal φA11 of NAND gate 54, calculates a logical product of refresh cycle signal / Refcyc and signal φA11, and outputs signal φA10 obtained by inverting the calculation result. The NAND gate 54 receives the output signal φA10 output from the NAND gate 53 and the output signal φA12 output from the NAND gate 55, calculates the logical product of the signal φA10 and the signal φA12, and outputs the calculation result. An inverted signal φA11 is output.

  The inverter 56 receives and inverts the signal φA11 output from the flip-flop 52, and outputs the inverted signal as the refresh flag signal Refflag.

  Inverter 57 receives refresh command signal / REFE and inverts it. Delay circuit 58 receives refresh command signal / REFE inverted by inverter 57, and outputs signal φA13 obtained by delaying the inverted refresh command signal / REFE for a predetermined time.

  NAND gate 55 receives refresh command signal / REFE and signal φA13 output from delay circuit 58, calculates a logical product of refresh command signal / REFE and signal φA13, and outputs signal φA12 obtained by inverting the calculation result. To do.

  The determination circuit 60 includes a buffer circuit 61. The buffer circuit 61 receives the internal chip enable signal ZINTCE and outputs a determination signal Refwin.

  Referring again to FIG. 9, WAIT control circuit 306 sets the level of the WAIT signal output via WAIT terminal 314 to “L” while refresh control is performed under the control of refresh control circuit 305.

(package)
FIG. 11 shows a configuration of a package containing two synchronous pseudo SRAMs according to the present embodiment. Referring to FIG. 9, the first synchronous pseudo SRAM 300a and the second synchronous pseudo SRAM 300b have the same configuration as the synchronous pseudo SRAM of FIG. The bonding option PAD313a of the first synchronous pseudo SRAM 300a is opened, and the switch 304a sends the refresh cycle signal / Refcyc output from the refresh timer 301a to the refresh control circuit 305a.

On the other hand, the bonding option PAD313b of the second synchronous pseudo SRAM 300b is given a ground potential, and the switch 304b receives the refresh cycle signal output from the refresh timer 301a of the first synchronous pseudo SRAM 300a received through the refresh timer input PAD 312b. / Refcyc is sent to the refresh control circuit 305b. As a result, the refresh control circuits 305a and 305b are both operated by the refresh cycle signal / Refcyc of the refresh timer 301a, so that the refresh timing of the first synchronous pseudo SRAMs 300a and 300b is the same. The WAIT control circuit 306a The WAIT signal is output through the WAIT terminals 314a and 314, and the WAIT control circuit 306b outputs the WAIT signal through the WAIT terminals 314b and 314. Since the refresh timings of the refresh control circuits 305a and 305b are the same, the timing when each WAIT signal changes to “L” is also the same.

  As described above, in the plurality of synchronous pseudo SRAMs, it is possible to make the timing of the WAIT level change for notifying that the operation instructed from the outside cannot be accepted during the refresh.

  Although the present embodiment has been described by taking as an example a package in which two synchronous pseudo SRAMs are mounted, any number of two or more synchronous pseudo SRAMs may be mounted.

  In the present embodiment, a plurality of synchronous pseudo SRAMs share the refresh cycle signal / Refcyc, output their own refresh cycle signal / Refcyc through the refresh timer output PAD, and others through the refresh timer input PAD. The refresh cycle signal / Refcyc of the synchronous pseudo SRAM is received, but the present invention is not limited to this. For example, a plurality of synchronous pseudo SRAMs share the refresh flag signal Refflag, the inverted AND signal / REFSF, or the refresh command signal / REFE, and transfer these signals through the refresh timer output PAD and the refresh timer input PAD. It may be done.

  Furthermore, in this embodiment, a plurality of synchronous pseudo SRAMs output their WAIT signals, but the present invention is not limited to this. For example, a switch that can be controlled by the bonding option PAD is provided between the WAIT control circuit 306a and the WAIT terminal 314a, and between the WAIT control circuit 306b and the WAIT terminal 314b, and only one switch has the WAIT terminal and the WAIT control circuit. WAIT signal may be output only from one synchronous pseudo SRAM.

  Further, when a plurality of synchronous pseudo SRAMs do not output the WAIT signal, that is, when the self-refresh timing overlaps with the external read signal READ or write signal WRITE timing, the read signal READ or the write signal When WRITE is held and a read operation or a write operation is performed after completion of self-refresh, only the refresh cycle signal / Refcyc may be shared. That is, WAIT control is not performed. Even in this case, since a plurality of synchronous pseudo SRAMs perform refresh simultaneously, there is a certain effect that signal interference hardly occurs.

  Further, the present embodiment is not limited to the synchronous pseudo SRAM, and can be applied to a pseudo SRAM that does not operate in synchronization with the clock.

[Fourth Embodiment]
In the present embodiment, in burst read / write, several bits are read / written from the top in accordance with the first clock in which a read or write signal is generated, and the second and subsequent clocks defined by the command latency CL The present invention relates to a synchronous pseudo SRAM that reads / writes the remaining bits in accordance with the clock.

(Constitution)
FIG. 12 shows a configuration of the synchronous pseudo SRAM 400 according to the present embodiment. Referring to this figure, this synchronous pseudo SRAM 400 includes a DRAM cell array 401, a control circuit 402, an address buffer 403, an RCR (Refresh Configuration Register) 404, a BCR 405 (Bus Configuration Register), an input / output circuit, and And a buffer 406.

  The DRAM cell array 401 is a memory array composed of dynamic random access memory (DRAM) cells.

  Input / output circuit and buffer 406 inputs / outputs data to / from the external system side through data input / output terminal DQ. Input / output circuit and buffer 406 outputs data output from the DRAM cell in synchronization with clock signal CLKQ applied from input / output control circuit 411.

The RCR 404 defines a self refresh method.
The BCR 405 stores an interface with an external system, such as a burst length BL and a command latency CL.

  The address buffer 403 receives the external address signal ADD [21: 0] and generates an internal address signal. In the synchronous pseudo SRAM, the address buffer 403 takes in the external address signal ADD [21: 0] when the external address take-in signal ADV # is “L”. The timing at which the external address fetch signal ADV # becomes “L” is earlier than the timing at which the read signal READ or the write signal WRITE is generated. The external address signal ADD [21: 0] applied at this time includes not only a row address but also a column address. Therefore, the row address and the column address are acquired prior to the generation of the read signal READ or the write signal WEITE.

  In this way, not only the row address but also the column address can be acquired prior to the generation of the read signal READ or the write signal. Therefore, after the row access, the process waits until the clock specified by the command latency CL is input. Without having to start column access. In the present embodiment, using such a feature, the data in the first column of burst access is read according to the clock (referred to as the first clock) when the read signal READ or the write signal is generated. Perform column access processing. Then, in accordance with a clock (referred to as a second clock) defined by the command latency CL, a column access process for reading data in the remaining columns for burst access is performed.

  The control circuit 402 includes a command decoder 410, an input / output control circuit 411, a row control circuit 409, a column control circuit 407, a WAIT control circuit 412, and a refresh control circuit 420.

  Command decoder 410 generates a row activation signal ACT, a read signal READ, and a write signal WRITE according to the combination of the logic levels of the internal control signals generated from the external control signals.

  The row control circuit 409 activates a column enable signal COLE, a sense amplifier activation signal SENSE for activating a sense amplifier connected to the bit line pair BL, ZBL provided between the memory cell and the global bit line pair GIO, ZGIO. Is generated. FIG. 13 shows the configuration of the row control circuit 409. Referring to the figure, delay circuit (Delay) DL101 receives row activation signal ACT that is activated in response to rising of first clock CLK0, which is a clock in which read signal READ or write signal WRITE is generated. The delay circuit (Delay) DL101 outputs a sense amplifier activation signal SENSE obtained by delaying the row activation signal ACT. The delay circuit (Delay) DL102 receives the sense amplifier activation signal SENSE and generates a column enable signal COLE obtained by delaying the sense amplifier activation signal SENSE.

  The column control circuit 407 generates a preamplifier activation signal PARM for activating a preamplifier connected to the global bit line pair GIO, ZGIO, and a column decoder activation trigger signal CDETRG. FIG. 14 shows a part of the configuration of the column control circuit 407. Referring to FIG. 8, column control circuit 407 includes a COLP_SHFT generator 422 and a CDETRG generator 421.

  The COLP_SHFT generator 422 reads with the first clock CLK0 which is the clock when the external clock CLK, the read signal READ (or write signal WRITE), the command latency CL, and the read signal READ (or write signal WRITE) are generated. A column shift signal COLP_SHFT is generated based on the number of bits N1 (in this embodiment, “1”) and the burst length BL. That is, the COLP_SHFT generator 422 generates the column shift signal COLP_SHFT in response to the falling of the (CL-N1) -th clock CLK after the clock when the read signal READ (or write signal WRITE) is generated. When activated, the column shift signal COLP_SHFT is deactivated in response to the counter value of the burst length counter becoming the burst length BL.

  The CDETRG generator 421 generates a column decoder activation trigger signal CDETRG based on the column shift signal COLP_SHFT, the external clock CLK, and the column enable signal COLE.

  FIG. 15 shows a detailed configuration of the CDETRG generator 421. Referring to FIG. 9, CDETRG generator 421 includes a one-shot pulse generator 431, an AND circuit AND41, and an OR circuit OR42. The one-shot pulse generator 431 generates a one-shot pulse whose level is “H” at the rising edge of the column enable signal COLE. This one-shot pulse is a signal for activating the first column accessed in synchronization with the first clock CLK0.

  The AND circuit AND41 outputs a clock pulse whose level is “H” when the column enable signal COE is “H” and COLP_SHFT is “H”. This clock pulse becomes a signal for activating the second to fourth columns accessed in synchronization with the clocks after the second clock CLK2.

  The OR circuit OR42 combines the one-shot pulse output from the one-shot pulse generator 431 and the clock pulse output from the AND circuit AND41. The synthesized pulse becomes the pulse of the column decoder activation trigger signal CDETRG.

  FIG. 16 shows the configuration of the WAIT control circuit 412. Referring to FIG. 6, WAIT control circuit 412 includes WAIT_ASYN generation circuit 432 and WAIT generation circuit 433.

  The WAIT_ASYN generation circuit 432 sets the WAIT_ASYN signal to “L” in response to the read signal READ or the write signal WRITE input from the command decoder 410 and the external chip enable signal CE # being activated to “L”. To do. Thereafter, after receiving the preamplifier activation signal PAE, the WAIT_ASYN generation circuit 432 sets the WAIT_ASYN signal to “H” after a predetermined time required for the data D0 of the first bit to be output from the data output terminal DQ. . Thereafter, the WAIT_ASYN generation circuit 432 sets the WAIT_ASYN signal to Hi-Z in response to the external chip enable signal CE # being deactivated to “H”.

  The WAIT generation circuit 433 receives the read signal READ or the write signal WRITE from the command decoder 410 and sets the WAIT signal to “L” in response to the external chip enable signal CE # being activated to “L”. To. After that, the WAIT generation circuit 433 receives the number of clocks of (CL-1) + (the number of bits N1 read by the first clock CLK0 which is the clock when the read signal READ or the write signal WRITE is generated). Thereafter, the WAIT signal is activated to “H”. Thereafter, the WAIT generation circuit 433 sets the WAIT signal to Hi-Z in response to the external chip enable signal CE # being deactivated to “H”.

(Timing of WAIT signal of conventional synchronous pseudo SRAM)
FIG. 17 is a diagram illustrating the timing of the WAIT signal of the conventional synchronous pseudo SRAM. As shown in the figure, the WAIT signal becomes “L” in response to the read signal READ being inputted and the external chip enable signal CE # being activated to “L”. Thereafter, after receiving the number of clocks of (CL-1) (CL = 3), the WAIT signal becomes “H”. Thereafter, in response to the external chip enable signal CE # being deactivated to “H”, the WAIT signal becomes Hi-Z.

(Timing of WAIT_ASYN signal and WAIT signal of synchronous pseudo SRAM 400 of the present embodiment)
FIG. 18 is a diagram illustrating the timing of the WAIT_ASYN signal and the WAIT signal of the synchronous pseudo SRAM 400 according to the present embodiment. As shown in the figure, the WAIT_ASYN signal becomes “L” in response to the read signal READ being input and the external chip enable signal CE # being activated to “L”. After receiving the preamplifier activation signal PAE, the WAIT_ASYN signal becomes “H” after a lapse of a predetermined time required for the leading bit data D0 to be output from the data output terminal DQ. Thereby, it is possible to notify the external system side of the timing at which the data D0 of the first bit for which column access is performed according to the clock CLK0. Thereafter, the WAIT_ASYN signal becomes Hi-Z in response to the external chip enable signal CE # being deactivated to “H”.

  Further, as shown in the figure, the WAIT signal becomes “L” in response to the read signal READ being input and the external chip enable signal CE # being activated to “L”. After that, after receiving the number of clocks of (CL-1 + N1) (CL = 3, N1 = 1), the WAIT signal becomes “H”. As a result, the external system side can be notified of the output timing of the leading bit data D1 for which column access is performed in synchronization with the clock determined based on the command latency CL. Thereafter, in response to the external chip enable signal CE # being deactivated to “H”, the WAIT signal becomes Hi-Z.

  Referring again to FIG. 12, peripheral circuit group 408 includes a row decoder 418, a column decoder 417, a sense amplifier (not shown), and a preamplifier (not shown).

The row decoder 418 activates the selected word line.
FIG. 19 shows the configuration of the column decoder 417. As shown in the figure, when the column decoder activation trigger signal CDETRG is activated, the column selection signal CSL corresponding to the input column address is activated.

  A sense amplifier (not shown) is a first amplifier circuit, and amplifies a potential difference between the bit line pair BL and ZBL.

  A preamplifier (not shown) is a second amplifier circuit, and expands the potential difference between the global bit line pairs GIO and ZGIO connected to the plurality of bit line pairs BL and ZBL.

  A refresh control circuit 420 in FIG. 12 controls a self-refresh operation of the DRAM cell array based on an internal refresh timer (not shown).

(Operation of Synchronous Pseudo SRAM of this Embodiment)
FIG. 20 is a timing chart showing the operation of the synchronous pseudo SRAM 400 of the present embodiment. Referring to the figure, first, row access processing is performed as follows in synchronization with the rise of clock CLK0 (first clock) from which read signal READ is generated.

  Command decoder 410 outputs a row activation signal activated in synchronization with clock CLK0.

  The row decoder 418 selects a word line based on the row address sent from the address buffer 403 and activates the selected word line.

  The row control circuit 409 delays the row activation signal ACT and activates the sense amplifier enable signal SENSE. Thereby, a sense amplifier (not shown) in peripheral circuit group 408 amplifies the bit line pair.

  The row control circuit 409 activates the column enable signal COLE by delaying the sense amplifier enable signal SENSE.

  Next, column access processing for the first column is performed in synchronization with the rising edge of the first clock CLK0.

  The CDETRG generator 421 generates a one-shot pulse from the rising edge of the column enable signal COLE. This is the first pulse of the column decoder activation trigger signal CDETRG.

  The column decoder 417 activates the column selection signal CSL corresponding to the input column address of the first column in response to the first pulse of the column decoder activation trigger signal CDETRG.

  The potential of the bit line pair of the first column selected by the column selection signal CSL is sent to a preamplifier (not shown) in the peripheral circuit group 408 to be amplified.

  The data in the first column amplified by the preamplifier is sent to the input / output circuit and buffer 406. On the other hand, input / output control circuit 411 receives external clock CLK and outputs internal clock signal CLKQ. Here, the pulse of the leading clock signal CLKQ is generated in response to the rising edge of the first clock CLK0.

  The input / output circuit and buffer 406 outputs the data D0 output from the first column to the outside through the data output terminal DQ in synchronization with the clock signal CLKQ.

  Next, the column access processing of the second to fourth columns is performed in synchronization with the clock after the first clock CLK0 to (CL-N1) = 2nd clock CLK2 (second clock). It is.

  The COLP_SHFT generator 422 activates the column shift signal COLP_SHFT in response to the fall of the clock CLK2 (second clock), and the column shift signal in response to the counter value of the burst length counter becoming the burst length BL. Deactivate COLP_SHFT.

  The CDETRG generator 421 extracts three clock pulses included in a period in which the column shift signal COLP_SHFT is “H”. These are the second to fourth pulses of the column decoder activation trigger signal CDETRG.

  The column decoder 417 activates the column selection signal CSL corresponding to the input column addresses of the second to fourth columns in response to the second to fourth pulses of the column decoder activation trigger signal CDETRG. Turn into.

  The potentials of the bit line pairs in the second to fourth columns selected by the column selection signal CSL are sent to a preamplifier (not shown) in the peripheral circuit group 408 to be amplified.

  The data of the second to fourth columns amplified by the preamplifier is sent to the input / output circuit and the buffer 406. On the other hand, the input / output control circuit 411 receives an external clock signal CLK and outputs an internal clock signal CLKQ. The timings of the second to fourth pulses of the clock signal CLKQ are normal timings.

  The input / output circuit and buffer 406 externally outputs data D1 to D3 output from the second to fourth columns in synchronization with the second to fourth pulses of the clock signal CLKQ through the data output terminal DQ. Output to.

  As described above, according to the synchronous pseudo SRAM according to the present embodiment, the data is output earlier than the timing defined by the command latency CL, so that the system side can receive the data earlier, The process can be started early. In addition, the time when the bus is uncertain can be shortened.

  In the present embodiment, one piece of data is output in synchronization with the first clock CLK0. However, the present invention is not limited to this, and two or three pieces of data may be output. The number of data to be output in synchronization with the first clock CLK0 may be determined by the convenience of the system side.

  In the present embodiment, the WAIT_ASYN signal becomes Hi-Z in response to the external chip enable signal CE # being deactivated to “H”, but the present invention is not limited to this. . For example, the WAIT_ASYN signal may be Hi-Z in response to the WAIT signal becoming “H”.

  The number of bits N1 read by the first clock CLK0 may be a fixed value or a value set in a register by an external signal.

  In this embodiment, since the number of bits N1 read by the first clock CLK0 is “1”, one bit accessed in synchronization with the first clock CLK0 using the one-shot pulse generator 431. A signal for activating the column is generated. When N1 is 2 or more, a circuit that outputs N1 pulses obtained by shifting the generated one-shot pulse every cycle may be added.

  Further, the row control circuit is not limited to that shown in FIG. 13, and may be as shown in FIG. 21, for example. Referring to FIG. 21, delay circuit (Delay) DL191 and delay circuit (Delay) DL192 are activated in response to the rise of first clock CLK0, which is a clock in which read signal READ or write signal WRITE is generated. An activation signal ACT is received. The delay circuit (Delay) DL191 outputs a sense amplifier activation signal SENSE obtained by delaying the row activation signal ACT. The delay circuit (Delay) DL192 generates a column enable signal COLE obtained by delaying the row activation signal ACT.

  Further, the present embodiment is not limited to the synchronous pseudo SRAM, and may be a flash memory or the like, and any semiconductor memory device that operates in synchronization with a clock may be used. Can also be applied. In particular, it is suitable for application to a synchronous pseudo-SRAM that requires high integration and high speed.

  In the operation example of the present embodiment, the operation when the read signal READ is generated by an external signal has been described. However, the same operation is performed when the write signal WRITE is generated by an external signal.

[Modification of Fourth Embodiment]
In the present modification, even when the read signal READ or the write signal WRITE is generated during the refresh operation, in the burst read / write, several bits from the head are generated according to the first clock, as in the fourth embodiment. This relates to a synchronous pseudo SRAM that reads / writes the remaining bits and reads / writes the remaining bits in accordance with a clock after the second clock defined by the command latency CL.

  In this modification, a command shift circuit 480 is added to the control circuit 402 of the fourth embodiment so as to cope with the case where the read signal READ or the write signal WRITE is generated during the refresh operation.

  FIG. 22 is a diagram illustrating input / output signals of the command shift circuit 480. The command shift circuit 408 receives the read signal READ from the command decoder 410 and the refresh operation signal REFRESH from the refresh control circuit 420, and outputs a modified read signal READF. This modified read signal READF is sent in place of the read signal READ to the circuit to which the read signal READ is sent.

  FIG. 23 shows a detailed configuration of the command shift circuit 480. Referring to the drawing, an inverting AND circuit NAND81 receiving a refresh operation signal REFRESH and an inverting AND circuit NAND82 receiving a read signal READ constitute a flip-flop. Inverter IV81 inverts refresh operation signal REFRESH.

  The inverting AND circuit NAND83 that receives the output of the inverter IV81 and the inverting AND circuit NAND84 that receives the read signal READ constitute a flip-flop.

  An inverting AND circuit NAND85 receiving the output of the inverting AND circuit NAND83 and the reset signal ZPOR, and an inverting AND circuit NAND86 receiving the output of the inverting AND circuit NAND82 and the output of the inverting AND circuit NAND84 constitute a flip-flop. To do. The reset signal ZPOR is activated to “H” when the power is turned on.

  Inverter IV82 receives the output of NAND circuit NAND86. Inverter IV83 receives the output of inverter IV82. The inverting OR circuit NOR81 receives the output of the inverting AND circuit NAND86 and the output of the inverter IV83.

  The inverting AND circuit NAND87 receives the output of the inverting OR circuit NOR81 and the output of the inverter IV82. The delay circuit DL81 delays the output of the inverting AND circuit NAND87. Inverting OR circuit NOR82 receives the output of inverter IV83 and the output of delay circuit DL81. The delay circuit DL82 delays the output of the inverting OR circuit NOR82.

  The inverting AND circuit NAND88 receives the output of the delay circuit DL82 and the output of the inverting OR circuit NOR81. The delay circuit DL83 delays the output of the inverting AND circuit NAND88. The inverting AND circuit NAND89 receives the output of the delay circuit DL83 and the output of the inverting OR circuit NOR81.

  Inverter IV84 receives the output of NAND circuit NAND89. Inverter IV85 receives the output of inverter IV84. The inverting AND circuit NAND90 receives the output of the inverter IV85 and the output of the inverting AND circuit NAND89. The inverting OR circuit NOR83 receives the output of the inverting AND circuit NAND90 and the output of the inverter IV84. Inverter IV86 inverts the output of inverting OR circuit NOR83. Inverter IV87 inverts the output of inverter IV86.

  The inverting AND circuit NAND91 receives the output of the inverting OR circuit NOR83 and the output of the inverter IV87. The inverting OR circuit NOR84 receives the output of the inverting AND circuit NAND91 and the output of the inverter IV84. Inverter IV88 inverts the output of inverting OR circuit NOR84. Inverted OR circuit NAND85 receives the output of inverter IV84 and the output of inverter IV88. The inverter IV89 inverts the output of the inverting OR circuit NAND85 and outputs the corrected read signal READF.

  FIG. 24A shows a modified read signal READF when the read signal READ is input when the refresh operation is not performed. As shown in the figure, when the refresh operation is not performed, the refresh operation signal REFRESH is “L”. The timing at which the modified read signal READF generated by the command shift circuit 480 is activated is almost the same as the timing at which the read signal READ is activated. Therefore, even if this modified read signal READF is used instead of the read signal READ, the same operation as in the fourth embodiment can be performed.

  FIG. 24B is a diagram illustrating the modified read signal READF when the read signal READ is input during the refresh operation. As shown in the figure, the refresh operation signal REFRESH is “H” when the refresh operation is performed, but becomes “L” when the refresh operation is completed. The timing at which the modified read signal READF generated by the command shift circuit 480 is activated is immediately after the refresh operation signal REFRESH falls and the refresh ends. Therefore, if this modified read signal READF is used in place of the read signal READ, the same operation as in the fourth embodiment can be performed immediately after the end of the refresh. That is, in FIG. 20, a series of processing is performed starting from the clock CLK0 when the read signal READ is generated. However, in this modification, a series of processing is started from the clock when the corrected read signal READF is input. Processing will be performed.

  In this modification, the case where the read signal READ or the write signal WRITE is generated during the refresh operation has been described. However, a new read signal READ or the write signal WRITE is generated during the execution of the read or write operation or the like. The same can be applied to the case. In particular, when the word line to be newly read or written is different from the word line that has been previously read or written, the original word line is deactivated, the new word line is activated, and This modification is effective because processing such as amplification by a sense amplifier is required.

  In this modification, the command shift circuit 480 generates the corrected read signal READ by the read signal READ. However, the present invention is not limited to this, and the command shift circuit 480 generates the corrected write signal WRITEF by the write signal WRITE. There may be.

[Fifth Embodiment]
The present embodiment relates to a synchronous pseudo SRAM having both a synchronous mode and an asynchronous mode, and having a preamplifier that is a second amplifier circuit suitable for each mode. The sense amplifier that is the first amplifier circuit amplifies the potential of the bit line pair BL and ZBL, and the preamplifier that is the second amplifier circuit is connected to the plurality of bit line pairs BL and ZBL. It amplifies the potential of the global bit line pair GIO, ZGIO.

(Constitution)
FIG. 25 shows a configuration of a synchronous pseudo SRAM 500 according to the present embodiment. Referring to the figure, synchronous pseudo SRAM 500 includes a DRAM cell array 501, a control circuit 502, a peripheral circuit group 504, and an address buffer 503.

  The DRAM cell array 501 is a memory array composed of dynamic random access memory (DRAM) cells.

  The address buffer 503 receives the external address signal ADD [21: 0] and generates an internal address signal.

  The control circuit 502 includes a column control circuit 505, a command decoder 506, a common signal generation circuit 507, a synchronous preamplifier control circuit 508, an asynchronous preamplifier control circuit 509, a refresh control circuit 510, and a WAIT control circuit 511. Is provided.

  The column control circuit 505 outputs a column selection signal CSL based on the input address.

  Refresh control circuit 510 controls the self-refresh operation of the DRAM cell array based on an internal refresh timer (not shown).

  The WAIT control circuit 511 sets the level of the WAIT signal output via the WAIT terminal to “L” while the refresh control is performed by the control of the refresh control circuit 510.

  Command decoder 506 generates row activation signal ACT, read signal READ, and write signal WRITE according to the combination of the logic levels of the internal control signals generated from the external control signals.

  FIG. 26 shows the configuration of the common signal generation circuit 507. Referring to the figure, common signal generation circuit 507 includes a preamplifier activation preparation signal generator 523 and a synchronization instruction signal generator 524. As shown in the figure, the preamplifier activation preparation signal PAEM is generated by delaying the column selection signal CSL sent from the column control circuit 505 by α time by the delay circuit (Delay) DL53. The preamplifier activation preparation signal PAEM is sent to the synchronous preamplifier control circuit 508 and the asynchronous preamplifier control circuit 509.

  Synchronization instruction signal generator 524 includes an inverter IV54 that receives external chip enable signal CE #, an inverted AND circuit NAND53 that receives the output of inverter IV54 and external clock CLK, and an inverter IV53 that receives external chip enable signal CE #. Delay circuit (Delay) DL51 for delaying the output of inverter IV53 by β time, inverting AND circuit NAND54 receiving the external chip enable signal CE # and the output of delay circuit (Delay) DL51, and the output of inverting AND circuit NAND53 And an inverted AND circuit NAND58 receiving the output of the inverted AND circuit NAND55, and an inverted AND circuit NAND55 receiving the output of the inverted AND circuit NAND54 and the output of the inverted AND circuit NAND58.

  FIGS. 27A and 27B are timing charts at which the synchronization instruction signal SYNC is generated.

  Referring to FIG. 27A, when the external clock CLK is input, the synchronization instruction signal SYNC is generated at the rising edge of the first clock CLK after the external chip enable signal CE # is activated to “L”. The external chip enable signal CE # is deactivated to “H” and then becomes “L” after being delayed by β time by the delay circuit (Delay) DL51.

  Referring to FIG. 27B, when the external clock CLK is not input, the synchronization instruction signal SYNC becomes “L” indicating the asynchronous mode.

  The synchronization instruction signal SYNC is sent to the synchronous preamplifier control circuit 508 and the asynchronous preamplifier control circuit 509.

  FIG. 28 shows the configuration of the synchronization-compatible preamplifier control circuit 508. As shown in the figure, the synchronization-compatible preamplifier control circuit 508 includes a reference signal generator 521 and a synchronous operation preamplifier control signal generator 522.

  FIG. 29 shows the configuration of the reference signal generator 521. As shown in the figure, the reference signal generator 521 includes an inverting AND circuit NAND56 that receives the preamplifier activation preparation signal PAEM and the synchronization instruction signal SYNC, an inverter IV55 that receives the output of the inverting AND circuit NAND56, and an inverter IV55. A delay circuit (Delay) DL52 that delays the output by γ time and a delay circuit (High side Delay) HDL53 that delays the “H” level side of the output of the delay circuit (Delay) DL52 by ε time are provided. The output of the delay circuit (Delay) DL52 is the first reference signal PACL, and the output of the delay circuit (High-side Delay) HDL53 is the second reference signal PAEL.

  FIG. 30 is a diagram illustrating an example of a high-side delay. The high-side delay includes a P-channel MOS transistor P62, an N-channel MOS transistor N62, a resistor R, a capacitor C51, and an inverter IV56. The timing at which the node B of the high-side delay changes from “L” to “H” is later than the timing at which the node A changes from “L” to “H”, but the node B changes from “H” to “L”. The changing timing is the same as the timing at which the node A changes from “H” to “L”.

  FIG. 31 shows the configuration of the synchronization-compatible preamplifier control signal generator 522. As shown in the figure, the synchronization-compatible preamplifier control signal generator 522 receives the first reference signal PAEL and the second reference signal PACL, and receives the inverted preamplifier connection signal ZPADT, the preamplifier activation signal PAE, and the inverted preamplifier activation. A signal ZPAE and an inverted preamplifier equalize signal ZPAEQ are generated.

  FIG. 32 shows the timing at which a signal related to the synchronization-compatible preamplifier 512 is generated. Referring to the figure, when the synchronization mode is instructed, the synchronization instruction signal SYNC becomes “H” as described in FIG. The column selection signal CSL is activated to “H” at an appropriate timing.

  The preamplifier activation preparation signal PAEM is generated by delaying the column selection signal CSL by α time.

  The preamplifier activation preparation signal PAEM and the synchronization instruction signal SYNC are input to the inverting AND circuit NAND56 of the synchronization activation signal generator 521 to generate the first reference signal PACL delayed by γ time from the preamplifier activation preparation signal PAEM. Is done.

  Further, a second reference signal PAEL is generated in which the head of the pulse of the first reference signal PACL is delayed by ε time.

  The synchronous preamplifier control signal generator 522 activates the inverted preamplifier connection signal ZPADT to “L” when the first reference signal PACL is “H” and the second reference signal PAEL is “L”. The synchronization-compatible preamplifier control signal generator 522 generates the preamplifier activation signal PAE by delaying the second reference signal PAEL by δ time. The synchronization-compatible preamplifier control signal generator 522 inverts the preamplifier activation signal PAE to generate an inverted preamplifier activation signal ZPAE and an inverted preamplifier equalize signal ZPAEQ.

  On the other hand, when the synchronization instruction signal SYNC is “L” indicating the asynchronous mode, the first reference signal PACL and the second reference signal PAEL are not activated. As a result, the inverted preamplifier connection signal ZPADT and the preamplifier activation signal PAE are activated. Inverted preamplifier activation signal ZPAE and inverted preamplifier equalize signal ZPAEQ are not activated.

  FIG. 33 shows the configuration of the asynchronous preamplifier control circuit 509. As shown in the figure, the asynchronous preamplifier control circuit 509 delays the output of the inverted AND circuit NAND57 that receives the inversion of the preamplifier activation preparation signal PAEM and the synchronization instruction signal SYNC and the inverted AND circuit NAND57 by ρ time. Delay circuit (Delay) DL54 and inverter IV59 which receives the output of delay circuit (Delay) DL54 are provided. The output of the inverter IV59 is a preamplifier activation signal PAED.

  FIG. 34 shows the timing at which a signal related to the asynchronous preamplifier 513 is generated. With reference to the figure, when the asynchronous mode is instructed, the synchronization instruction signal SYNC becomes “L” as described in FIG. The column selection signal CSL is activated to “H” at an appropriate timing.

  The preamplifier activation preparation signal PAEM is generated by delaying the column selection signal CSL by α time.

  The preamplifier activation preparation signal PAEM and the synchronization instruction signal SYNC are sent to the asynchronous preamplifier control circuit 509, and the preamplifier activation signal PAED in which the preamplifier activation preparation signal PAEM is delayed by ρ time is generated.

  On the other hand, when the synchronization instruction signal SYNC is “H” indicating the synchronization mode, the preamplifier activation signal PAED is not activated.

  Referring to FIG. 25 again, peripheral circuit group 504 includes a synchronization-compatible preamplifier 512, an asynchronous-compatible preamplifier 513, a synchronization-compatible DB driver 514, an asynchronous-compatible DB driver 516, and an output circuit 515.

(Synchronous preamplifier 512)
FIG. 35 shows the configuration of the synchronization-compatible preamplifier 512. As shown in the figure, the synchronous preamplifier 512 includes a switch unit 561 controlled by an inverted preamplifier connection signal ZPADT, an equalize unit 562 controlled by an inverted preamplifier equalize signal ZPAEQ, a preamplifier activation signal PAE, and an inverted preamplifier. An amplification unit 563 controlled by an activation signal ZPAE and buffer units 564 and 565 controlled by a preamplifier activation signal PAE and an inverted preamplifier activation signal ZPAE are provided.

  Switch unit 561 includes a P-channel MOS transistor P32 and a P-channel MOS transistor P31. P channel MOS transistor P32 is arranged between global input / output line GIO and NODEX. P channel MOS transistor P31 is arranged between inverted global input / output line ZGIO and NODEY. An inverted preamplifier connection signal ZPADT is applied to the gates of P channel MOS transistor P32 and P channel MOS transistor P31.

  Equalize portion 562 includes a P channel MOS transistor P34 and a P channel MOS transistor P33. P-channel MOS transistor P34 is arranged between NODEX and the power supply. P-channel MOS transistor P33 is arranged between NODEY and the power supply. An inverted preamplifier equalize signal ZPAEQ is applied to the gates of P channel MOS transistor P34 and P channel MOS transistor P33.

  Amplifying portion 563 includes P channel MOS transistors P35 to P39 and an N channel MOS transistor N31. Between NODES and NODET, a P-channel MOS transistor P36 and a P-channel MOS transistor P37 connected in series are placed, and a P-channel MOS transistor P38 and a P-channel MOS transistor P39 connected in series are arranged in parallel with this. Is placed. The gates of P channel MOS transistors P36 and P37 are connected to NODEY. The gates of P channel MOS transistors P38 and P39 are connected to NODEX. P-channel MOS transistor P35 is arranged between the power supply and NODES. N-channel MOS transistor N31 is arranged between NODET and ground. Inverted preamplifier activation signal ZPAE is applied to the gate of P channel MOS transistor P35, and preamplifier activation signal PAE is applied to the gate of N channel MOS transistor N31.

  Buffer 564 includes P channel MOS transistors P40-P42 and an N channel MOS transistor N32. P-channel MOS transistor P40 and P-channel MOS transistor P41 are arranged between the power supply and NODEO. The gate of P channel MOS transistor P40 is connected to NODEX. A preamplifier activation signal PAE is applied to the gate of the P channel MOS transistor P41. P-channel MOS transistor P42 is arranged between NODEO and NODEP. An inverted preamplifier activation signal ZPAE is applied to the gate of the P channel MOS transistor P42. N-channel MOS transistor N32 is arranged between NODEP and the ground. N channel MOS transistor N32 has its gate connected to NODEX. Inverted preamplifier output data ZPDD is output from NODEX.

  Buffer 565 includes P channel MOS transistors P43 to P45 and an N channel MOS transistor N33. P-channel MOS transistor P43 and P-channel MOS transistor P44 are arranged between the power supply and NODEQ. The gate of P channel MOS transistor P43 is connected to NODEY. A preamplifier activation signal PAE is applied to the gate of the P channel MOS transistor P44. P channel MOS transistor P45 is arranged between NODEQ and NODER. Inverted preamplifier activation signal ZPAE is applied to the gate of P channel MOS transistor P45. N-channel MOS transistor N33 is arranged between NODER and ground. N channel MOS transistor N33 has its gate connected to NODEY. The preamplifier output data PDD is output from NODEY.

  Since the synchronization preamplifier 512 includes the switch unit 561, the global input / output pair GIO and ZGIO can be disconnected from the amplifier unit 523 at an appropriate timing by the inverted preamplifier connection signal ZPADT. As a result, once the potential of the global input / output pair GIO, ZGIO is taken in, the amplifying unit 523 can perform so-called confined amplification in which amplification is performed regardless of subsequent changes, and the amplification can be speeded up. . Further, since global input / output pair GIO, ZGIO is disconnected from amplification section 523, precharge processing can be performed in equalization section 562 simultaneously with amplification in amplification section 523, and the entire preamplifier can be processed at high speed.

  In particular, when a read process synchronized with the clock is performed, the address changes at a constant timing, and the address does not change at a random timing. Therefore, if the switch unit 561 is disconnected at a timing at which the address does not change, the global Data of the input / output line pair GIO and ZGIO is not removed.

  From the above, it can be said that this synchronization-compatible preamplifier 512 is suitable for a read operation synchronized with a clock.

  On the other hand, the synchronization-compatible preamplifier 512 is not suitable for an asynchronous read operation that does not synchronize with the clock, as described below.

  FIG. 36 is a diagram for explaining that the synchronous preamplifier 512 is not suitable for asynchronous reading. As shown in the figure, in asynchronous reading, reading processing is performed in accordance with a change in address.

  As shown in (1) of the figure, when the column address changes in a short time after the column address has changed, the inverted preamplifier equalize signal ZPAQ is activated in response to each change. As shown in (2) of the figure, their activation timing approaches. As a result, the precharge is not sufficiently performed. Since amplification is performed without precharging, the output data PDD of the preamplifier is distorted as shown in (3) of FIG. In order to avoid such a problem, it is necessary to access the next column after sufficiently providing a precharge period, and the processing by the synchronous preamplifier 512 is delayed.

  In addition, as shown in (4) of the figure, when an illegal address change occurs due to the influence of noise or the like, the column data of the illegal column address change is output to the global input / output line pair GIO and ZGIO. After that, column data with correct column address change is output. In this case, if the timing of disconnecting the global input / output line pair GIO, ZGIO and the amplifying unit 563 is early, illegal data is amplified and correct data is not amplified as shown in (5) of FIG. In order to avoid such a problem, it is necessary to delay the timing of disconnecting the global input / output line pair GIO, ZGIO and the amplifying unit 563, and the processing by the synchronization-compatible preamplifier 512 is delayed.

  As described above, when the synchronous preamplifier 512 is used for asynchronous reading, the processing is slow and it is not appropriate.

(Asynchronous preamplifier 513)
FIG. 37 shows the configuration of the asynchronous preamplifier 513. As shown in the figure, the asynchronous preamplifier 513 is a differential current mirror type amplifier.

  Referring to FIG. 37, P channel MOS transistors P51 and P52 form a current mirror circuit. N channel MOS transistor N51 is arranged between nodes ZPAN and NODEC. N channel MOS transistor N52 is arranged between NODEE and NODED. N channel MOS transistor N51 has its gate connected to global input / output line GIO. N channel MOS transistor N52 has its gate connected to inverted global input / output line ZGIO. P channel MOS transistor P53 is arranged between NODEC and NODED. A preamplifier activation signal PAED is applied to the gate of P channel MOS transistor P53.

  P channel MOS transistors P55 and P56 form a current mirror circuit. N channel MOS transistor N54 is arranged between nodes PAN and NODEH. N channel MOS transistor N53 is arranged between NODEF and NODEG. N channel MOS transistor N54 has its gate connected to inverted global input / output line ZGIO. N channel MOS transistor N53 has its gate connected to global input / output line GIO. P-channel MOS transistor P57 is arranged between NODEG and NODEH. Preamplifier activation signal PAED is applied to the gate of P channel MOS transistor P57.

  N-channel MOS transistor N55 is arranged between NODED and ground. A preamplifier activation signal PAED is applied to the gate of N channel MOS transistor N55. P-channel MOS transistor P54 is arranged between NODEE and NODEF. A preamplifier activation signal PAED is applied to the gate of P channel MOS transistor P54.

  Further, a P-channel MOS transistor P58 and a P-channel NOS transistor P59 are arranged in parallel between the power supply and the node ZPAN2. A preamplifier activation signal PAED is input to the gate of P-channel MOS transistor P58, and P-channel MOS transistor P59 has its gate connected to node PAN.

  N-channel MOS transistor N56, N-channel MOS transistor 57, and N-channel MOS transistor N58 are connected in series between node ZPAN2 and ground. N channel MOS transistor N56 has its gate connected to inverted global input / output line ZGIO. N channel MOS transistor N57 has its gate connected to node PAN2. Preamplifier activation signal PAED is input to the gate of N channel MOS transistor N58.

  Further, a P-channel MOS transistor P60 and a P-channel NOS transistor P61 are arranged in parallel between the power supply and the node PAN2. A preamplifier activation signal PAED is input to the gate of the P-channel MOS transistor P61, and the P-channel The gate of MOS transistor P60 is connected to node ZPAN.

  N-channel MOS transistor N59, N-channel MOS transistor 60, and N-channel MOS transistor N61 are connected in series between node PAN2 and ground. N channel MOS transistor N59 has its gate connected to inverted global input / output line ZGIO. N channel MOS transistor N60 has its gate connected to node ZPAN2. A preamplifier activation signal PAED is input to the gate of N channel MOS transistor N61.

  Furthermore, the inverting OR circuit NOR99 connected to the node PAN2 and the inverting OR circuit NOR98 connected to the node ZPAN2 constitute a flip-flop. Inverter IV51 inverts the output of inverting OR circuit NOR99 and outputs preamplifier output signal PAN3. Inverter IV52 inverts the output of inverting OR circuit NOR98 and outputs inverted preamplifier output signal ZPAN3.

FIG. 38 is a diagram showing the time change of the potential of each node of the asynchronous preamplifier 513.
This asynchronous preamplifier 513 is a so-called unconfined preamplifier that does not have a switch part like the synchronous preamplifier 512. Therefore, since the asynchronous preamplifier 513 is not disconnected from the global input / output lines GIO and ZGIO during amplification, it is suitable for asynchronous reading in which reading is performed according to an address change.

  Referring to FIG. 25 again, synchronization corresponding DB driver 514 outputs the received potential to data bus DB. FIG. 39 shows the configuration of the synchronization corresponding DB driver 514. As shown in the figure, the synchronization-corresponding DB driver 514 includes an inverter IV74 that receives the output PDD of the synchronization-corresponding preamplifier 512, inverts it, and outputs it to the data bus DB.

  Asynchronous DB driver 516 outputs the received potential to data bus DB. FIG. 40 shows the configuration of the asynchronous DB driver 516. This asynchronous DB driver 516 includes an inverter IV72 that receives the output PAN3 of the asynchronous preamplifier 513, inverts it and outputs it to the data bus DB.

  The output circuit 515 in FIG. 25 receives the data on the data bus DB and outputs it to the outside through the data output terminal DQ.

  As described above, the synchronous pseudo-SRAM according to the present embodiment has the preamplifier that operates properly in the synchronous mode and the preamplifier that operates appropriately in the asynchronous mode. The potential difference between the output lines GIO and ZGIO can be amplified.

  In this embodiment, the preamplifier for synchronous operation and the preamplifier for asynchronous operation are divided, but the present invention is not limited to this, and a preamplifier for burst mode and a preamplifier for random access mode may be provided. . In this case, the semiconductor memory device does not have a synchronous mode and an asynchronous mode, but has a burst mode and a random access mode. For the burst mode, a preamplifier capable of confining amplification such as the preamplifier 512 is suitable so that the prefetch operation and the pipeline operation can be efficiently performed.

  In this embodiment, the synchronous mode and the asynchronous mode are switched by the synchronization instruction signal SYNC. However, the present invention is not limited to this, and the synchronous mode and the asynchronous mode are provided depending on the potential applied to the bonding option PAD. It is good also as what switches.

  Further, in this embodiment, the synchronous compatible DB driver 514 and the asynchronous compatible DB driver 516 are provided. However, a synchronous and asynchronous DB driver may be used.

  FIG. 41 shows the configuration of a shared DB driver 590 that serves both as a synchronous DB driver 514 and an asynchronous DB driver 516. As shown in the figure, the shared DB driver 590 is composed of an inverter IV74 that receives the output of one buffer unit 525 and outputs it to the data bus DB. An inverting OR circuit NOR71 that receives the output PDD of the synchronous preamplifier 512 and the output PAN3 of the asynchronous preamplifier 513, and an inverter IV73 that inverts the output of the inverting OR circuit NOR71 and outputs it to the data bus DB.

  FIG. 42 is a diagram illustrating the layout of the synchronous preamplifier 512 and the asynchronous preamplifier 513. As shown in the figure, a synchronous preamplifier 512 is placed in the synchronous preamplifier placement area 596, and an asynchronous preamplifier 513 is placed in the asynchronous preamplifier placement area 597.

  Synchronous preamplifier 512 and asynchronous preamplifier 513 connected to each global input / output line pair GIO, ZGIO are arranged side by side in the column direction. The global input / output line pair GIO, ZGIO is different from the preamplifier arrangement layer, and the global input / output line pair GIO, ZGIO is connected to the synchronous preamplifier 512 and the asynchronous preamplifier 513 without branching.

  As described above, in the layout shown in FIG. 42, it is not necessary to branch the global input / output line pair GIO, ZGIO, and the global input / output line pair GIO, ZGIO can be easily wired. This layout is suitable when the size of the synchronous pseudo SRAM 500 can be increased in the column direction.

  FIG. 43 is a diagram illustrating another layout of the synchronous preamplifier 512 and the asynchronous preamplifier 513. As shown in the figure, in the synchronous / asynchronous preamplifier arrangement region 598, a synchronous preamplifier 512 and an asynchronous preamplifier 513 are arranged.

  Synchronous preamplifier 512 and asynchronous preamplifier 513 connected to each global I / O line pair GIO, ZGIO are arranged side by side in the row direction. The global input / output line pair GIO, ZGIO has branches, one of which is connected to the synchronous preamplifier 512 and the other of which is connected to the asynchronous preamplifier 513.

  As described above, in the layout shown in FIG. 43, it is necessary to branch the global input / output line pair GIO, ZGIO. This layout is suitable when the size of the synchronous pseudo SRAM 500 can be increased in the row direction.

[Sixth Embodiment]
The present embodiment relates to a synchronous pseudo SRAM having a byte mask function. In the synchronous pseudo SRAM, the data read from the memory cell can be prevented from being output to the outside by masking the upper byte or the lower byte. By the way, in the burst mode, there is a no-wrap mode. In the no-wrap mode, when the last column is reached during burst reading or writing, the process moves to the next row. In this case, row access processing such as inactivation of the selected word line, activation of a newly selected word line, and amplification processing by a sense amplifier is required. While the row access process is being performed, the WAIT signal is output to the outside. The external system side may give a byte mask signal after the WAIT signal is canceled, but for the external system, regardless of the presence or absence of such row access processing for shifting to the next row, It is desirable to set the byte mask in the same way. In the present embodiment, when burst read or burst write is performed over two rows, the first row and the second row, and the last column of the first row is reached on the way, the transition to the second row occurs. The present invention also relates to a synchronous pseudo SRAM that can provide a byte mask signal from the outside in the same manner as when not passing over two rows.

(Constitution)
FIG. 44 shows a configuration of a synchronous pseudo SRAM 600 according to the present embodiment. Referring to the figure, this synchronous pseudo SRAM 600 includes a DRAM cell array 601, a CLK buffer 604, a UB buffer 605, an LB buffer 606, a WE buffer 607, an ADV buffer 608, a control circuit 602, and a peripheral circuit. Circuit group 603 and BCR (Bus Configuration
Register) 610.

  The DRAM cell array 601 is a memory array composed of dynamic random access memory (DRAM) cells.

  The peripheral circuit group 603 includes a global input / output line pair GIOP (GIO and / GIO) (not shown), a column selection line provided corresponding to each column, a column selection gate, a sense amplifier, a preamplifier, and a write driver. And a row decoder and a column decoder. Peripheral circuit group 603 further includes an output circuit 620.

  The output circuit 620 holds data output from the DRAM cell array 601. The output circuit 620 receives the output enable signal OE for each upper byte and lower byte. The output circuit 620 outputs the upper byte of the held data to the outside through the data input / output terminal DQ when the upper byte output enable signal OE indicates enable “H”. The output circuit 620 outputs the lower byte of the held data to the outside through the data input / output terminal DQ when the lower byte output enable signal OE indicates enable “H”.

  The BCR 610 stores an interface with an external system, such as a burst length BL and a command latency CL.

  FIG. 45 shows a detailed configuration of the CE buffer 609. Referring to FIG. 8, CE buffer 608 is connected to inverter 1 including P-channel MOS transistor P71 and N-channel MOS transistor N71 to which external chip enable signal CE # is input, and to inverter 1. Inverter 2 including P channel MOS transistor P72 and N channel MOS transistor N72, and inverter 3 including P channel MOS transistor P73 and N channel MOS transistor N73 connected to inverter 2 are included. The output of the inverter 2 is an inverted internal chip enable signal ZINTCE, and the output of the inverter 3 is an internal chip enable signal INTCE.

  FIG. 46 shows a detailed configuration of the UB buffer 605. Referring to the figure, UB buffer 605 is connected to inverter 1 composed of P channel MOS transistor P75 and N channel MOS transistor N74 to which external higher byte mask signal UB # is input, and to inverter 1. Inverter 2 composed of P channel MOS transistor P76 and N channel MOS transistor N76, and inverter IV44 connected to inverter 2 are included. The output of the inverter IV44 becomes the internal upper byte mask signal INTUB. Further, P channel MOS transistor P74 is arranged between the power supply and P channel MOS transistor P75. An N channel MOS transistor N75 is arranged between the connection node of inverters 1 and 2 and the ground.

  An inverted internal chip enable signal ZINTCE is input to the gate of P channel MOS transistor P74 and the gate of N channel MOS transistor N75. When the chip is activated, the inverted chip enable signal ZINTCE becomes “L”. At this time, P-channel MOS transistor P75 is connected to the power supply, and the connection node between inverter 1 and inverter 2 is not grounded. Therefore, normal operation is performed.

  On the other hand, when the chip is inactivated, the inverted chip enable signal ZINTCE becomes “H”. At this time, P channel MOS transistor P75 is disconnected from the power supply, and the connection node between inverter 1 and inverter 2 is grounded. Therefore, the internal upper byte mask signal INTUB always remains “L”.

  Since the configurations of other input buffer CLK buffer 604, LB buffer 606, WE buffer 607, and ADV buffer 608 are the same as the configuration of UB buffer 605, description thereof will not be repeated.

  Referring to FIG. 44 again, control circuit 602 includes command decoder 611, ZRST generation circuit 612, ZUB0 generation circuit 613, ZLB0 generation circuit 614, ADV0 generation circuit 615, ZWE0 generation circuit 616, mask A control circuit 617, a row control circuit 618, a WAIT control circuit 619, and a refresh control circuit 621 are provided.

  Command decoder 611 generates row activation signal ACT and read signal READ according to the combination of the logic levels of the internal control signals generated from the external control signals.

  FIG. 47 shows a detailed configuration of the ZUB0 generation circuit 613. Referring to the figure, clocked inverter CIV61 receives internal upper byte mask signal INTUB. The output of the clocked inverter CIV61 is sent to a bistable circuit composed of an inverter IV21 and an inverter IV22. The output of the bistable circuit is sent to the inverter IV23. The output of the inverter IV23 and the internal clock INTCLK are sent to the inverting AND circuit NAND21. The output of the inverting AND circuit NAND21 is sent to the inverter IV24, and the output of the inverter IV24 becomes ZUB0.

  FIG. 48 shows a detailed configuration of the ZLB0 generation circuit 614. Referring to the figure, clocked inverter CIV62 receives internal lower byte mask signal INTLB. The output of the clocked inverter CIV62 is sent to a bistable circuit composed of an inverter IV25 and an inverter IV26. The output of the bistable circuit is sent to the inverter IV27. The output of the inverter IV27 and the internal clock INTCLK are sent to the inverting AND circuit NAND22. The output of the NAND circuit NAND22 is sent to the inverter IV28, and the output of the inverter IV28 becomes ZLB0.

  FIG. 49 shows a detailed configuration of the ADV0 generation circuit 615. Referring to the figure, clocked inverter CIV63 receives internal address fetch signal INTADV. The output of the clocked inverter CIV63 is sent to a bistable circuit composed of an inverter IV29 and an inverter IV30. The output of the bistable circuit and the internal clock INTCLK are sent to the inverting AND circuit NAND23. The output of the inverting AND circuit NAND23 is sent to the inverter IV31, and the output of the inverter IV31 becomes ADV0. On the other hand, the output of the bistable circuit is sent to the inverter IV32. The output of the inverter IV32 and the internal clock INTCLK are sent to the inverting AND circuit NAND24. The output of the inverting AND circuit NAND24 is sent to the inverter IV33, and the output of the inverter IV33 becomes ZADV0.

  FIG. 50 shows a detailed configuration of the ZWE0 generation circuit 616. Referring to the figure, clocked inverter CIV64 receives internal write enable signal INTWE. The output of the clocked inverter CIV64 is sent to a bistable circuit composed of an inverter IV34 and an inverter IV35. The output of the bistable circuit is sent to the inverter IV36. The output of the inverter IV36 and the internal clock INTCLK are sent to the inverting AND circuit NAND25. The output of the inverting AND circuit NAND25 is sent to the inverter IV37, and the output of the inverter IV37 becomes ZWE0.

  FIG. 51 shows a detailed configuration of the ZRST generation circuit 612. Referring to the figure, inverter IV38 receives read signal READ. The delay circuit (Delay) DL99 delays the output of the inverter IV99. The inverting OR circuit NOR21 receives the read signal READ and the output of the delay circuit (Delay) DL99. Inverter IV42 receives the output of inverting OR circuit NOR21. The output of the inverter IV42 becomes the inverted reset signal ZRST.

  FIG. 52 is a diagram illustrating timing at which the inverted reset signal ZRST is generated. As shown in the figure, the inverted reset signal ZRST is activated to become an “L” level pulse when the read signal READ is deactivated to “L”.

  FIG. 53 shows a detailed configuration of the mask control circuit 617. The figure shows only the lower side (LB), but the upper side (UB) is the same. Referring to FIG. 53, in first control circuit 631, NAND circuit NAND26 receives ADV0, ZLB0, and ZWE0. The NAND circuit NAND29 and the NAND circuit NAND30 constitute a flip-flop. The inverting AND circuit NAND29 receives the output of the inverting AND circuit NAND26. The inverted AND circuit NAND30 receives the inverted reset signal ZRST. Inverter IV39 receives the output of NAND circuit NAND29. The output of the inverter IV39 is the first output enable signal OE1. With this configuration, the first control circuit 631 has the external byte mask signal LB # set to “H” when the external byte mask signal LB # indicates that the first bit of the burst access is to be byte masked. The first output enable signal OE1 is set to “L” from the clock CLK to the time including the timing when the first bit is output from the output circuit 620.

  In second control circuit 632, NAND circuit NAND27 receives ZADV0, ZLB0, and ZWE0. The inverting AND circuit NAND31 and the inverting AND circuit NAND32 constitute a flip-flop. The inverting AND circuit NAND31 receives the output of the inverting AND circuit NAND27. The inverting AND circuit NAND31 receives the inverting reset signal ZRST. The inverting AND circuit NAND35 receives the ZWAIT signal and the output of the inverting AND circuit NAND31. The output of the inverting AND circuit NAND35 is the second output enable signal OE2. With such a configuration, the second control circuit 632 performs row access processing for shifting to the next row when the external byte mask signal LB # indicates that byte masking of bits other than the first bit is performed. If the WAIT signal is “H” at the timing when the bit is output to the output circuit 620 when it is not performed, the second output enable signal OE2 is set to “L” as usual. When it is “L”, the second output enable signal OE2 is not set to “L”, and a signal generated based on the byte mask signal (that is, the output of the NAND circuit NAND27) is output to the third control circuit 633. .

  In third control circuit 633, inverter IV41 receives the ZWAIT signal. The delay circuit (Delay) DL21 delays the output of the inverter IV41. The NAND circuit NAND28 receives the ZWAIT signal and the output of the delay circuit (Delay) DL21. The inverting AND circuit NAND33 and the inverting AND circuit NAND34 constitute a flip-flop. The inverting AND circuit NAND33 receives the output of the inverting AND circuit NAND27. Inverted logical product circuit NAND34, inverted reset signal ZRST, and the output of inverted logical product circuit NAND28 are received. Inverter IV40 receives the ZWAIT signal. The inverting AND circuit NAND36 receives the output of the inverter IV40 and the output of the inverting AND circuit NAND33. The output of the inverting AND circuit NAND36 is the third output enable signal OE3. With such a configuration, the third control circuit 633 receives and holds the signal generated based on the byte mask signal, and at the timing when the WAIT signal changes from “L” to “H”, the third output enable The signal OE3 is set to “L”.

  The inverting AND circuit NAND60 receives the first output enable signal OE1, the second output enable signal OE2, and the third output enable signal OE3. The inverter IV43 receives the output of the inverting AND circuit NAND60 and outputs an output enable signal OE. When at least one of the first output enable signal OE1, the second output enable signal OE2, and the third output enable signal OE3 is “L” by the inverting AND circuit NAND60 and the inverter IV43, the output enable signal OE becomes “L”.

  Referring to FIG. 44 again, row control circuit 618 controls row access processing (word line activation, amplification by a sense amplifier, etc.).

  The refresh control circuit 621 controls the self-refresh operation of the DRAM cell array based on an internal refresh timer (not shown).

  The WAIT control circuit 619 has reached the last column during the refresh control under the control of the refresh control circuit 621 and in the middle of burst reading in the no-wrap mode, so that the row access for shifting to the next row is performed. During processing (deactivation of the original row word line, activation of a new row word line, amplification by a sense amplifier, etc.), the level of the WAIT signal output via the WAIT terminal is set to “ L ”. That is, when the WAIT signal is “L”, the outside is informed of waiting until data is output.

(Access operation when not moving to the next row)
FIG. 54 is a timing chart showing signal changes when no shift to the next row is involved during burst reading in the synchronous pseudo SRAM 600 of the present embodiment. The operation of Examples 1 to 3 will be described with reference to FIG.

(Example 1) When there is no mask The external byte mask signals LB # and UB # do not become “H”. In this case, the first output enable signal OE1, the second output enable signal OE2, and the third output enable signal OE3 are “H” for the entire period.

(Example 2) When masking the second bit The external byte mask signals LB # and UB # are "H" in (1) of FIG. In this case, the first output enable signal OE1 and the third output enable signal OE3 are “H” for the entire period. On the other hand, the second output enable signal OE2 becomes “L” at the timing when the second bit is output from the output circuit 620 (from the rising edge of the clock CLK3 to the rising edge of the clock CLK4), as shown in (2) of FIG. Become.

(Example 3) When masking the first bit The external byte mask signals LB # and UB # are "H" in (3) of FIG. In this case, the second output enable signal OE2 and the third output enable signal OE3 are “H” for the entire period. The first output enable signal OE1 is output from the output circuit 620 from the clock CLK in which the external byte mask signals LB # and UB # are set to “H” as shown in (4) of FIG. It is “L” until the time including the timing (from the rising edge of the clock CLK0 to the rising edge of the clock CLK3).

(Access operation when transitioning to the next row in no-wrap mode)
FIG. 55 is a timing chart showing a change when the synchronous pseudo SRAM 600 of the present embodiment is set to the no-wrap mode and accompanied by a transition to the next row during burst reading. The operation of Examples 1 to 3 will be described with reference to FIG.

(Example 1) When there is no mask The external byte mask signals LB # and UB # do not become “H”. The first output enable signal OE1, the second output enable signal OE2, and the third output enable signal OE3 are “H” for the entire period.

(Example 2) When masking the second bit (with transition processing to the next row)
The external byte mask signals LB # and UB # are “H” in (1) of FIG. In this case, the first output enable signal OE1 and the second output enable signal OE2 are “H” for the entire period. The third output enable signal OE3 becomes “L” at the timing (from the rise of the clock CLK7 to the rise of the clock CLK8) when the WAIT signal becomes “H” as shown in (3) of FIG.

  As a result, the mask processing of the second bit is extended to the time when the row access processing of the next row ends and the WAIT signal becomes “H”.

(Example 3) When masking the third bit The external byte mask signals LB # and UB # are "H" in (3) of FIG. In this case, the first output enable signal OE1 and the third output enable signal OE3 are “H” for the entire period. The second output enable signal OE2 becomes “L” at the timing (from the rising edge of the clock CLK8 to the rising edge of the clock CLK9) when the third bit is output from the output circuit 620, as shown in (4) of FIG.

(Example 4) When masking the first bit Although not shown, it is the same as in (Example 3) of FIG.

  As is clear from the above description, the setting timing of the second bit byte mask signal, that is, the timing of applying the external byte mask signals LB # and UB # is indicated by either (A) in FIG. 54 or FIG. It is timing. Therefore, even when shifting to the next row in the middle of burst reading or burst writing, a byte mask signal can be applied from the outside in the same manner as when not shifting to the next row.

  Note that this embodiment is not applicable only to the no-wrap mode, but is also effective in the continuous mode in which reading / writing is continuously performed until the chip enable signal becomes inactive.

  Further, the present embodiment is not limited to the synchronous pseudo SRAM, and can be applied to any semiconductor memory device that operates in synchronization with a clock.

[Seventh Embodiment]
The present embodiment relates to a mobile / cellular RAM having both functions of a mobile RAM and a cellular RAM. Here, the cellular RAM is a synchronous pseudo SRAM described in Non-Patent Document 1. The mobile RAM is a pseudo SRAM having a function specific to a mobile phone.

(Constitution)
FIG. 56 shows a configuration of the mobile / cellular RAM 700 according to the present embodiment. Referring to FIG. 6, this mobile / cellular RAM 700 includes a DRAM cell array 701, a control circuit 707, and an input / output circuit 705.

  The DRAM cell array 707 is a memory array composed of dynamic random access memory (DRAM) cells.

  The input / output circuit 705 receives data from the outside through the data output terminal DQ and outputs the data to the outside.

  The control circuit 707 includes a common unit 702, a mobile RAM dedicated unit 703, a cellular RAM dedicated unit 704, and a mobile RAM / cellular RAM determination circuit 706.

  The mobile RAM / cellular RAM determination circuit 706 determines and operates any of the common unit 702, the mobile RAM dedicated unit 703, and the cellular RAM dedicated unit 704 in accordance with an external signal.

The common unit 702 performs a function common to the mobile RAM and the cellular RAM.
The mobile RAM dedicated unit 703 executes functions that only the mobile RAM has.

The cellular RAM dedicated unit 704 executes functions that only the cellular RAM has.
FIG. 57 shows a configuration of the common unit 702. As shown in the figure, the common unit 702 includes a refresh timer 721, a sense operation control circuit 722, an address queue countermeasure circuit 723, and an input / output buffer 724.

  The refresh timer 721 outputs a timing signal for performing self refresh.

The sense operation control circuit 722 controls the operation of the sense amplifier.
The address queue countermeasure circuit 723 is a circuit that controls so as not to generate an address queue.

  The input / output buffer 724 receives and holds an external control signal, an external address signal, an external clock, and the like, generates an internal control signal, an internal address signal, an internal clock, and the like, and holds data to be output to the outside.

  FIG. 58 shows the configuration of the cellular RAM dedicated unit 704. As shown in the figure, the cellular RAM dedicated unit 704 includes a synchronous interface circuit 741, a ZADV control circuit 742, a NOR interface circuit 743, other cellular compatible operation control circuit 744, and a BCR / RCR set circuit 745. Prepare.

The synchronous interface circuit 741 controls an operation synchronized with the clock.
The ZADV control circuit 742 controls external address acquisition based on the external address acquisition signal ADV #.

  The NOR interface circuit 743 controls the interface with the NOR flash memory.

  The other cellular compatible operation control circuit 744 controls, for example, an SRAM compatible interface.

The BCR / RCR set circuit 745 sets BCR and RCR.
FIG. 59 shows the configuration of the mobile RAM dedicated unit 703. As shown in the figure, the mobile RAM dedicated unit 703 includes a command mode circuit 731, a burst refresh circuit 732, an early write circuit 733, and a data holding block control circuit 734.

  Command mode circuit 731 sets and resets internal registers according to a combination of external signals.

  The burst refresh circuit 732 holds the refresh request in the internal counter, and continuously performs a refresh operation when a certain fixed timing is input.

  The early write circuit 733 controls the early write operation in which the timing of the write operation is advanced.

  The data holding block control circuit 734 holds only the data of the selected block by controlling so that only the selected block is refreshed.

  As described above, according to the RAM according to the present embodiment, it is configured to efficiently realize the functions of both the cellular RAM and the mobile RAM, so that the production management can be made efficient and the inventory is reduced at the time of product switching. And development costs can be reduced.

[Eighth Embodiment]
The present embodiment relates to a synchronous pseudo SRAM that performs precharge using a burst length counter.

(Constitution)
FIG. 60 shows a configuration of a synchronous pseudo SRAM 800 according to the present embodiment. Referring to FIG. 8, this synchronous pseudo SRAM 800 includes a DRAM cell array + peripheral circuit group 801, a control circuit 802, a command decoder 803, a BCR (Burst Configuration Register) 804, and a burst length counter 805.

  The DRAM cell array of the DRAM cell array + peripheral circuit group 801 is a memory array composed of dynamic random access memory (DRAM) cells. The peripheral circuit group includes a global input / output line pair GIOP (GIO and / GIO), a column selection line provided corresponding to each column, a column selection gate, a sense amplifier, a preamplifier, a write driver, Includes decoders, column decoders, etc.

  The command decoder 803 generates a row activation signal ACT, a read signal READ, and a write signal WRITE according to the combination of the logic levels of the internal control signals generated from the external control signal.

  The BCR 804 stores an interface with an external system, such as a burst length BL and a command latency CL.

  FIG. 61 shows a detailed configuration of the burst length counter 805. Referring to FIG. 9, burst length counter 805 includes a CSL counter 999 and an AND circuit AND101. The CSL counter 999 receives a column selection signal CSL. When the CSL counter 999 counts the pulses of the burst length BL column selection signals CSL, it outputs “H”. The AND circuit AND101 receives the external clock CLK and the output of the CSL counter 999, and receives the burst length reset signal BLRST at the timing when the first clock CLK after the output of the CSL counter 999 becomes “H” is input. Activates to “H”.

  The control circuit 802 includes a row control circuit 806. When the row control circuit 806 receives the burst length reset signal BLRST, the row control circuit 806 activates the precharge signal PRC. The precharge signal PRC inactivates the word line and precharges the bit line pair.

(Operation)
FIG. 62 shows a timing chart when the word line is deactivated. As shown in the figure, when the timing of the clock that receives the read signal READ or the write signal WRITE is set to the clock CLK0, the command latency CL = 2 and the burst length BL = 4 are used to select the last column of the burst access. Column select signal CSL is activated at the timing of clock CLK4. The burst length counter 805 activates the burst length reset signal BLRST to “H” at the timing of the clock CLK5 which is (CL + BL−1) = 5 clocks after CLK0. Then, based on the burst length reset signal BLRST, the precharge signal PRC is activated, the selected word line (X ₀ ) is deactivated, and the bit line pair is precharged.

  As described above, according to the synchronous pseudo SRAM according to the present embodiment, burst length counter 805 activates burst length reset signal BLRST when counting pulses of burst length BL column selection signals CSL. The word line can be deactivated without returning the external chip enable signal CE # to “H”.

  As described above, according to the synchronous pseudo SRAM according to the present embodiment, the word line is not deactivated by the external control, but the word line is deactivated by the internal control. Become.

  Note that a reset signal may be generated starting from the falling edge of the external address fetch signal ADV #, and the precharge signal PRC may be generated by the reset signal.

  In this embodiment, the word line is deactivated based on the burst length reset signal BLRST. However, the present invention is not limited to this. For example, a standby state in which neither reading nor writing is performed is performed. It is good.

  Further, the present embodiment is not limited to the synchronous pseudo SRAM, and can be applied to any semiconductor memory device that operates in synchronization with a clock.

[Ninth Embodiment]
The present embodiment relates to a synchronous pseudo SRAM having a fixed synchronous mode.

(Conventional synchronous mode / asynchronous mode setting)
First, the setting of the synchronous / asynchronous mode of the conventional CellularRAM® will be described.

  FIG. 63 is a diagram illustrating a conventional synchronous / asynchronous mode setting method. As shown in the figure, when tCSP is 20 ns or more, the asynchronous fixed mode is set regardless of the value of BCR [15] which is the 15th bit of BCR (Bus Configuration Register). When tCSP is less than 20 ns, the mode is set according to the value of BCR [15]. tCSP is the time from the fall of the external chip enable signal CE # to the rise of the external clock CLK.

  FIGS. 64A and 64B are diagrams for explaining mode setting based on the value of tCSP. In FIG. 64A, tCSP is 7.5 ns. In this case, since tCSP is less than 20 ns, the value of BCR [15] is referred to. When the value is 0, the synchronous / asynchronous mixed mode is set, and when the value is 1, the asynchronous fixed mode is set.

  In FIG. 64 (b), tCSP is 22.5 ns. In this case, since tCSP is 20 ns or more, the asynchronous fixed mode is set regardless of the value of BCR [15] when it becomes 20 ns from the falling edge of the external clock CLK.

  As is apparent from the above description, as shown in FIG. 64B, when the clock frequency is low, the asynchronous fixed mode is forcibly set. Therefore, it cannot be operated at a low clock frequency and in a synchronous mode.

  Therefore, the present embodiment provides a synchronous pseudo SRAM that can be set to the synchronous mode even when the clock frequency is low such that tCSP is 20 ns or more.

(Setting of synchronous / asynchronous mode of this embodiment)
FIG. 65 is a diagram illustrating a synchronous / asynchronous mode setting method according to the present embodiment. As shown in the figure, when the value of BCR [16] is 0, the synchronous fixed mode is set regardless of the values of tCSP and BCR [15]. On the other hand, when the value of BCR [16] is 1, it is set in the same manner as in the past according to the values of tCSP and BCR [15].

(Constitution)
FIG. 66 shows a configuration of a synchronous pseudo SRAM 900 according to the present embodiment. Referring to the figure, the synchronous pseudo SRAM 900 includes a DRAM cell array + peripheral circuit group 901, a BCR (Bus Configuration Register) 903, a tCSP determination circuit 906, a synchronization control circuit 904, an asynchronous control circuit 905, And a common control circuit 902.

  The DRAM cell array of the DRAM cell array + peripheral circuit group 901 is a memory array composed of dynamic random access memory (DRAM) cells. The peripheral circuit group includes a global input / output line pair GIOP (GIO and / GIO), a column selection line provided corresponding to each column, a column selection gate, a sense amplifier, a preamplifier, a write driver, Includes decoders, column decoders, etc.

The BCR 903 defines an interface with an external system.
The tCSP determination circuit 906 asserts the asynchronous control signal ASYNCTRG when the time from when the external chip enable signal CE # falls to when the external clock CLK rises becomes 20 ns or more. The tCSP determination circuit 906 receives BCR [15] and BCR [16], and does not perform processing for determining tCSP when BCR [15] = 1 or when BCR [16] = 0. This is because when BCR [16] = 0, it is the synchronous fixed mode, and when BCR [15] = 1, it is the asynchronous fixed mode, so it is not necessary to determine tCSP.

  The synchronous control circuit 904 receives BCR [16], asynchronous control signals ASYNTRG, BCR [15], and is activated when the combination thereof indicates the synchronous fixed mode or the synchronous / asynchronous mixed mode shown in FIG. That is, the synchronous control circuit 904 is activated when BCR [16] = 0, BCR [16] = 1, the asynchronous control signal ASYNCTR is inactivated, and BCR [15] = 0. Sometimes deactivated. The synchronization control circuit 904 controls an operation synchronized with the external clock CLK of the synchronous pseudo SRAM 900 when activated.

  Asynchronous control circuit 905 receives BCR [16], asynchronous control signals ASYNTRG, and BCR [15] and is activated when the combination indicates the asynchronous fixed mode or the synchronous / asynchronous mode shown in FIG. Otherwise, it is deactivated. That is, the asynchronous control circuit 905 is activated when BCR [16] = 1, and deactivated when BCR [16] = 0. The asynchronous control circuit 905 controls an operation that is not synchronized with the external clock CLK of the synchronous pseudo SRAM 900 when activated.

  The common control circuit 902 controls the operation regardless of the synchronization of the external clock CLK. As described above, according to the synchronous pseudo SRAM according to the present embodiment, the synchronous fixed mode can be set regardless of the value of tCSP, so that the synchronous pseudo SRAM operates in synchronization with the clock even when the clock frequency is low. be able to.

  In this embodiment, since the synchronous mode / asynchronous mode is set using adjacent bits such as BCR [15] and BCR [16], circuit connection can be facilitated.

  In this embodiment, the synchronous fixed mode is set according to the value of BCR [16]. However, the present invention is not limited to this. For example, the synchronous fixed mode may be set by other bits of the BCR, bits of other registers, bonding options, or an external signal.

  The present embodiment is not limited to the synchronous pseudo SRAM, and is a semiconductor memory device having a synchronous mode that operates in synchronization with the clock and an asynchronous mode that operates asynchronously with the clock. Anything can be applied.

[Tenth embodiment]
In the present embodiment, the activation / inactivation of the input buffer is controlled by the external chip enable signal CE #, and the synchronous type that avoids the problem when the external chip enable signal CE # is activated without synchronizing with the clock. The present invention relates to a pseudo SRAM.

(Constitution)
FIG. 67 shows a configuration of the synchronous pseudo SRAM 1000 according to the present embodiment. Referring to this figure, synchronous pseudo SRAM 1000 includes a DRAM cell array + peripheral circuit group 1001, a control circuit 1002, a CE buffer 1003, a CLK buffer 1004, a control buffer 1005, and an address buffer 1006.

  The DRAM cell array of the DRAM cell array + peripheral circuit group 1001 is a memory array composed of dynamic random access memory (DRAM) cells. The peripheral circuit group includes a global input / output line pair GIOP (GIO and / GIO), a column selection line provided corresponding to each column, a column selection gate, a sense amplifier, a preamplifier, a write driver, Includes decoders, column decoders, etc.

  The address buffer 1006 receives the external address signal ADD [21: 0] and generates an internal address signal.

  The CE buffer 1003 receives the external chip enable signal CE # and generates an internal chip enable signal INTCE. The internal chip enable signal INTCE is sent to the CLK buffer 1004, the control buffer 1005, and the address buffer 1006. These input buffers stop operating when the internal chip enable signal INTCE is “L” indicating deactivation of the chip, and are normal when the internal chip enable signal INTCE is “H” indicating chip activation. Perform the action. These input buffers cannot hold an external signal and cannot output an internal signal while the operation is stopped.

  The CLK buffer 1004 receives the external clock CLK, holds it as the buffer clock BUFFCLK, and generates the internal clock INTCLK.

  The control buffer 1005 receives control signals (including the address fetch signal ADV #) excluding the external chip enable signal CE # and generates an internal control signal. For example, control buffer 1005 generates internal address acquisition signal INTADV when it receives external address acquisition signal ADV #.

  Control circuit 1002 includes an ADV0 generation circuit 1010 and a RAS generation circuit 1011.

  ADV0 generation circuit 1010 generates address fetch trigger signal ADV0 based on internal chip enable signal INTCE, internal clock INTCLK, and inverted internal address fetch signal ZINTADV.

  The RAS generation circuit 1011 generates a row address strobe signal RAS in response to the address take-in trigger signal ADV0.

(Conventional ADV0 generation circuit)
FIG. 68 shows a configuration of a conventional ADV0 generation circuit 1050. Referring to the figure, inverted internal address fetch signal ZINTADV is input to clocked inverter CIV1. The output of the clocked inverter CIV1 and the internal clock INTCLK are input to the inverting AND circuit NAND1, and the output of the inverting AND circuit NAND1 is input to the inverter IV1. The output of the inverter IV1 becomes the address fetch trigger signal ADV0.

(Conventional operation)
A problem that occurs when the external chip enable signal CE # is changed asynchronously without using the conventional ADV0 generation circuit in synchronization with the external clock CLK will be described.

  FIG. 69 is a diagram showing the change timing of each signal when conventional ADV0 generation circuit 1050 is used. Referring to FIG. 69, external clock CLK, external address take-in signal ADV #, and external chip enable signal CE # are applied as shown in FIG. When the external chip enable signal CE # is “H”, the CLK buffer 1004 and the control buffer 1005 are stopped, only the external chip enable signal CE # is taken into the CE buffer 1003, and the internal chip enable signal INTCE is generated. . In response to activation of external chip enable signal CE # to “L”, inverted internal chip enable signal ZINTCE becomes “L”.

  When the inverted internal chip enable signal ZINTCE becomes “L”, the control buffer 1005 resumes operation, the external address take-in signal ADV # is taken into the control buffer 1005, and the internal address take-in signal INTADV is generated. At this time, since the external address take-in signal ADV # is “L”, the inverted internal address take-in signal ZINTADV becomes “L”.

  When the inverted internal chip enable signal ZINTCE becomes “L”, the CLK buffer 1004 resumes its operation, the external clock CLK is taken into the CLK buffer 1004, and the CLK buffer 1004 receives the stored buffer clock BUFFCLK. In response to the rise, an internal clock INTCLK having a constant pulse width is generated. Here, before the inverted internal chip enable signal ZINTCE becomes “L”, the CLK buffer 1004 does not hold the external clock CLK, so the buffer clock BUFFCLK in the CLK buffer 1004 shown in (1) of FIG. Does not have the pulse width of the external clock CLK. This narrows the interval between the timing of the first internal clock INTCLK and the timing of the second INTCLK.

  Clocked inverter CIV1 in ADV0 generation circuit 1050 receives inverted internal address take-in signal ZINTADV, and its output NODEA rises to “H” at the rise of internal clock INTCLK, as shown in (2) of FIG. .

  Inversion AND circuit NAND1 and inverter IV11 in ADV0 generation circuit 1050 generate address fetch trigger signal ADV0 based on output NODEA of clocked inverter CIV1 and internal clock INTCLK. The pulse of the address fetch trigger signal ADV0 is a pulse from the head of the internal clock INTCLK as shown in (3) of FIG.

  The RAS generation circuit 1011 activates the row address strobe signal RAS to “H” in response to the leading edge of the address acquisition trigger signal ADV0. As a result, the timing at which the row address strobe signal RAS is originally intended to be activated, that is, the rising edge of the next clock CLK after the input of the external chip enable signal CE # (this is the point at which access is originally started) is earlier. It has been found that the row address strobe signal RAS is activated at the timing and the subsequent processing is started by the activation.

(ADV0 generation circuit of this embodiment)
In order to avoid the above problem, the configuration of the ADV0 generation circuit of the present embodiment is different from the conventional one.

  FIG. 70 shows the configuration of the ADV0 generation circuit 1010 of the present embodiment. In this ADV0 generation circuit, a delay circuit (Delay) DL1, an inverting OR circuit NOR95, and an inverter IV12 are added to the conventional ADV0 generation circuit 1050. Referring to the figure, delay circuit (Delay) DL11 receives inverted internal chip enable signal ZINTCE. The inverted OR circuit NOR95 receives the output of the delay circuit (Delay) DL11 and the inverted internal address fetch signal ZINTADV. Inverter IV12 receives the output of inverted OR circuit NOR95 and outputs inverted delayed internal address fetch signal ZINTADVD. Inverted delayed internal address fetch signal ZINTADVD is input to clocked inverter CIV1. The output of the clocked inverter CIV1 and the internal clock INTCLK are input to the inverting AND circuit NAND1, and the output of the inverting AND circuit NAND1 is input to the inverter IV1. The output of the inverter IV1 becomes the address fetch trigger signal ADV0.

(Operation of this embodiment)
FIG. 71 is a diagram showing the timing of change of each signal when ADV0 generation circuit 1010 of the present embodiment is used.

  External clock CLK, external address capture signal ADV #, external chip enable signal CE #, internal chip enable signal INTCE, internal address capture signal INTADV, buffer clock BUFFCLK, and internal clock INTCLK are shown in FIG. It is the same as the timing.

  The delay circuit (Delay) DL11, the inverting OR circuit NOR95, and the inverter IV1 in the ADV0 generation circuit 1010 receive the inverted internal chip enable signal ZINTCE and the inverted internal address fetch signal ZINTADV, as shown in (2) of FIG. Inverted delayed internal address fetch signal ZINTADVD is output.

  Clocked inverter CIV1 receives inverted delayed internal address fetch signal ZINTADVD, and its output NODEA rises to "H" at the fall of internal clock INTCLK, as shown in (3) of FIG.

  Inversion AND circuit NAND1 and inverter IV11 in ADV0 generation circuit 1050 generate address fetch trigger signal ADV0 based on output NODEA of clocked inverter CIV1 and internal clock INTCLK. The pulse of the address fetch trigger signal ADV0 is the second and subsequent pulses of the internal clock INTCLK as shown in (4) of FIG. That is, the leading pulse of the address take-in trigger signal ADV0 generated by the ADV0 generation circuit 1050 is an internal clock pulse generated from an external clock pulse that rises while the external address take-in signal ADV # is activated. In order to realize this, the delay amount of the delay circuit (Delay) DL11 is determined.

  The RAS generation circuit 1011 activates the row address strobe signal RAS to “H” in response to the leading edge of the address acquisition trigger signal ADV0. As a result, the row address strobe signal RAS is activated at the next rising edge of the clock CLK after the timing when the row address strobe signal RAS is originally activated, that is, after the external chip enable signal CE # is input. In other words, the delay amount of the delay circuit (Delay) DL11 is set to a delay amount for realizing this.

  As described above, according to the synchronous pseudo SRAM according to the present embodiment, the operation of the input buffer is stopped when the chip is inactive, so that wasteful current consumption can be suppressed.

  In addition, since the inverted internal chip enable signal ZINTCE is delayed, no malfunction occurs even when the external chip enable signal CE # is changed asynchronously.

  In the present embodiment, a configuration and method for avoiding problems when the external chip enable signal CE # is activated without synchronizing with the clock when the input buffer is stopped by the external chip enable signal CE #. As described above, this is effective regardless of whether the input buffer is stopped by the external chip enable signal CE #.

  Note that the delay amount of the delay circuit DL11 is desirably half or less (that is, ¼) of half of one cycle of the external clock CLK. This is because a large delay amount affects other operations.

  In the present embodiment, the configuration and method for avoiding the problem when the external chip enable signal CE # is activated without being synchronized with the clock have been described. However, the external chip enable signal CE # is synchronized with the clock. Even when it is deactivated, there are the following problems. That is, when the external chip enable signal CE # is deactivated and data is written in the memory cell, if the precharge is performed immediately, the data in the memory cell may be destroyed.

  FIG. 72 is a diagram showing that the precharge timing is delayed when the external chip enable signal CE # is deactivated without synchronizing with the clock. As shown in the figure, when a predetermined time (Delay) has elapsed from the falling edge of the column selection signal CSL at the time when the external chip enable signal becomes inactive to "H", that is, normal if writing is in progress. The word line is deactivated after waiting until the writing is completed. By doing so, the destruction of data in the memory cell can be prevented.

  Note that this embodiment is not limited to a synchronous pseudo SRAM, and can be applied to any semiconductor memory device that operates in synchronization with a clock.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

50 command signal activation circuit, 60 determination circuit, 41, 44, 55 NAND gate, 42, 56, 57 inverter, 48 buffer, 43, 49, 58 delay circuit, 45, 52 flip-flop, 61 buffer circuit, 100, 200 , 300, 300a, 300b Synchronous pseudo SRAM 101, 201, 801, 901, 1001 DRAM cell array + peripheral circuit group, 102, 202, 302, 302a, 302b, 402, 502, 602, 802, 1002 control circuit, 103 , 403, 503, 1006 Address buffer, 104 trigger generation circuit, 105 counter enable circuit, 106 clock counter, 107 determination circuit, 108 latency register, 109, 306, 306a, 306b, 412, 511, 619 WAIT control times , 110 delay circuit, 111, 211, 305, 305a, 305b, 420, 510, 620 refresh control circuit, 121 latch circuit, 212, 301, 301a, 301b, 721 refresh timer, 213 refresh bank address designating circuit, 214, 417 , 803 Command decoder, 221 OR circuit, 222 Bank address counter, 223 Refreshed / unexecuted determination circuit, 224 Refreshed bank holding circuit, 225
First comparison circuit, 226 Read / write operation bank detection circuit, 227 Second comparison circuit, 303, 303a, 303b, 401, 501, 601, 701 DRAM cell array, 304 switch, 311, 311a, 311b Refresh timer output PAD, 312 , 312a, 312b Refresh timer input PAD, 313, 313a, 313b
Bonding option PAD, 314, 314a, 314b WAIT terminal, 315, 315a, 315b Control signal terminal, 316, 316a, 316b Data input / output terminal, 407, 505 Column control circuit, 409, 499, 618, 806 Row control circuit, 410 , 506, 611 Command decoder, 421 CDETRG generator, 422 COLP_SHFT generator, 431 One-shot pulse generator, 432 WAIT_ASYN generation circuit, 433 WAIT generation circuit, 408, 504, 603 Peripheral circuit group, 480 Command shift circuit, 507 Common Signal generation circuit, 508 synchronous preamplifier control circuit, 508 synchronous preamplifier control circuit, 509 asynchronous preamplifier control circuit, 404 RCR, 405, 610, 903 BCR, 406 Input / output circuits and buffers, 417 column decoder, 418 row decoder, 512 synchronous preamplifier, 513 asynchronous preamplifier, 514 synchronous DB driver, 515,620 output circuit, 516 asynchronous DB driver, 521 reference signal generator, 522 synchronous Corresponding preamplifier control signal generator, 523 preamplifier activation preparation signal generator, 524 synchronization instruction signal generator, 561 switch unit, 562 equalizing unit, 563 amplifying unit, 564, 565
Buffer unit, 590 Shared DB driver, 596 Synchronous preamplifier arrangement area, 576 Asynchronous preamplifier arrangement area, 598 Synchronous / asynchronous pair preamplifier arrangement area, 604, 1004 CLK buffer, 605 UB buffer, 606 LB buffer, 607
WE buffer, 608 ADV buffer, 609, 1003 CE buffer, 612 ZRST generation circuit, 613 ZUB0 generation circuit, 614 ZLB0 generation circuit, 615 ADV0 generation circuit, 616 ZWE0 generation circuit, 617 mask control circuit, 631 first control circuit, 632 2nd control circuit, 633 3rd control circuit, 702 common part, 703 mobile RAM dedicated part, 704 cellular RAM dedicated part, 705 input / output circuit, 706 mobile RAM / cellular RAM determination circuit, 722 sense operation control circuit, 723 address queue Countermeasure circuit, 724 I / O buffer, 731 Command mode circuit, 732 Burst refresh circuit, 733 Early write circuit, 734 Data holding block control circuit, 741 Synchronous interface circuit, 742 ZADV control circuit 743 NOR interface circuit, 744 Other cellular compatible operation control circuit, 745 BCR / RCR set circuit, 804 BCR, 805 burst length counter, 902 common control circuit, 904 synchronous control circuit, 905 asynchronous control circuit, 906 tCSP determination circuit, 400, 500, 600, 800, 900, 1000 Synchronous pseudo SRAM, 700 Mobile / cellular RAM, 999 CSL counter, 1005 control buffer, 1010 ADV0 generation circuit, 1011 RAS generation circuit, 221, OR42 OR circuit, AND1, AND41, AND101 AND circuit, IV1-IV3, IV11, IV12, IV21-IV44, IV51, IV52-IV56, IV59, IV71-IV74, IV81-IV89 inverter OR42 OR circuit, NOR21, NOR22, NOR71, NOR81 to NOR85, NOR95, NOR98, NOR99 Inverted OR circuit, NAND1, NAND21 to NAND36, NAND53 to NAND58, NAND60, NAND81 to NAND91 Inverted AND circuit, DL11, DL21, DL51 DL54, DL81-DL83, DL99, DL101, DL102, DL191, DL192 Delay circuit (Delay), HDL53 High-side Delay, C capacitor, R load, P31-P45, P51-P62, P71-P76 P-channel MOS transistor, N31 N33, N51 to N62, N71 to N76 N-channel MOS transistors, CV1, CV61 to CV64 Clocked inverter.

Claims (6)

A memory array having a plurality of dynamic random access memory memory cells arranged in a matrix;
A first circuit for generating a first signal defining a refresh timing;
An output terminal for outputting the first signal;
An input terminal for receiving a second signal for defining refresh timing from the outside;
A switch that receives the first signal and the second signal and outputs one of the signals;
A semiconductor memory device comprising: a second circuit that receives a signal output from the switch and performs refresh control based on the signal. The semiconductor memory device further includes:
The semiconductor memory device according to claim 1, further comprising a wait control circuit that outputs a wait signal to the outside while refresh control is being executed in the second circuit.   The semiconductor memory device according to claim 2, wherein the first circuit is a timer that outputs a signal having a constant period as the first signal. A semiconductor memory device comprising a first pseudo SRAM chip and a second pseudo SRAM chip,
The first pseudo SRAM chip is:
A memory array having a plurality of dynamic random access memory memory cells arranged in a matrix;
A first circuit that includes a timer circuit and generates a first signal that defines a refresh timing according to an output of the timer circuit;
An output terminal for outputting the first signal;
An input terminal for receiving a second signal defining the timing of refresh;
A selection circuit that receives the first signal and the second signal and selects one of the signals;
Receiving a signal output from the selection circuit, and performing a refresh control based on the signal,
The second pseudo SRAM chip is:
A memory array having a plurality of dynamic random access memory memory cells arranged in a matrix;
A first circuit that includes a timer circuit and generates a first signal that defines a refresh timing according to an output of the timer circuit;
An output terminal for outputting the first signal;
An input terminal for receiving a second signal defining the timing of refresh;
A selection circuit that receives the first signal and the second signal and selects one of the signals;
Receiving a signal output from the selection circuit, and performing a refresh control based on the signal,
The output terminal of the first pseudo SRAM chip and the input terminal of the second pseudo SRAM chip are electrically connected;
The selection circuit of the first pseudo SRAM chip and the selection circuit of the second pseudo SRAM chip have different selection states,
A semiconductor memory device in which the first pseudo SRAM chip and the second pseudo SRAM chip are accommodated in one package.   The semiconductor memory device according to claim 4, wherein the selection circuit of the first pseudo SRAM chip and the selection circuit of the second pseudo SRAM chip switch the selection state by a bonding pad. The first pseudo SRAM chip further includes:
A wait control circuit for outputting an external wait signal while refresh control is being executed in the second circuit of the first pseudo SRAM chip;
The second pseudo SRAM chip further includes:
A wait control circuit for outputting an external wait signal while refresh control is being executed in the second circuit of the second pseudo SRAM chip;
The semiconductor memory device further includes:
The semiconductor memory device according to claim 4, further comprising a weight terminal that outputs an output of a weight control circuit of at least one of the first pseudo SRAM chip and the second pseudo SRAM chip to the outside of the package.

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