JP2010193402A5 - - Google Patents

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JP2010193402A5
JP2010193402A5 JP2009038441A JP2009038441A JP2010193402A5 JP 2010193402 A5 JP2010193402 A5 JP 2010193402A5 JP 2009038441 A JP2009038441 A JP 2009038441A JP 2009038441 A JP2009038441 A JP 2009038441A JP 2010193402 A5 JP2010193402 A5 JP 2010193402A5
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Japan
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signal
phase
circuit
converter
power
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JP2009038441A
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JP2010193402A (en
JP5228184B2 (en
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一方、ステップS50において、最小の電力が得られたと判定されたとき、位相制御器38Bは、最小の電力が得られときの位相になるようにIFFT37から出力された非希望信号(=推定された非希望信号)の位相を制御してDA変換器39へ出力する。 On the other hand, in step S50, when the minimum power is determine a constant and obtained, the phase controller 38B is the minimum undesired signal outputted from IFFT37 so that the phase at which electric power is obtained (= The phase of the estimated undesired signal) is controlled and output to the DA converter 39.

上述したように、位相制御器38Bは、加算器33によって加算された受信信号の電力が最小になるように、推定された非希望信号の位相を調整するので、遅延回路32における遅延時間に誤差が発生しても、受信信号に含まれる非希望信号を正確に抑制できる。その結果、受信信号を高性能に復調できる。 As described above, the phase controller 38 B adjusts the phase of the estimated undesired signal so that the power of the received signal added by the adder 33 is minimized, so that the delay time in the delay circuit 32 is adjusted. Even if an error occurs, an undesired signal included in the received signal can be accurately suppressed. As a result, the received signal can be demodulated with high performance.

1,101 アンテナ、2,102 BPF、3,3A,3B,3C 信号抑制回路、4,31,106,114 AGC、5,34,107,115 AD変換器、6,6A,117 復調器、7 判定器、8 信号切換回路、10,10A,10B,10C,10D,10E,10F,10G,100 無線装置、32,32A 遅延回路、33 加算器、35,35A FFT、 36 信号除去器、37 IFFT、38,38A,38B 位相制御器、39,110 DA変換器、40 電力測定器、41 周波数特性測定回路、103 ミキサ、 104 ローカル信号発振器、105,109 BPF、108 信号検出回路、111 ローパスフィルタ、112 切替器、113 減算器、116 チャネル分離器。 1,101 antenna, 2,102 BPF, 3,3A, 3B, 3C signal suppression circuit, 4,31,10 6,114 AGC, 5,34,10 7,115 AD converter, 6,6A, 1 17 demodulation Unit, 7 decision unit, 8 signal switching circuit, 10, 10A, 10B, 10C, 10D, 10E, 10F, 10G, 100 wireless device, 32, 32A delay circuit, 33 adder, 35, 35A FFT, 36 signal remover 37 IFFT, 38, 38A, 38B Phase controller, 39 , 110 DA converter, 40 Power meter, 41 Frequency characteristic measurement circuit , 103 Mixer, 104 Local signal oscillator, 105, 109 BPF, 108 Signal detection circuit, 111 Low pass filter, 112 switcher, 113 subtractor, 116 channel separator.

JP2009038441A 2009-02-20 2009-02-20 Wireless device Active JP5228184B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2009038441A JP5228184B2 (en) 2009-02-20 2009-02-20 Wireless device

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Application Number Priority Date Filing Date Title
JP2009038441A JP5228184B2 (en) 2009-02-20 2009-02-20 Wireless device

Publications (3)

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JP2010193402A JP2010193402A (en) 2010-09-02
JP2010193402A5 true JP2010193402A5 (en) 2012-05-17
JP5228184B2 JP5228184B2 (en) 2013-07-03

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JP2009038441A Active JP5228184B2 (en) 2009-02-20 2009-02-20 Wireless device

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Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5360662B2 (en) * 2010-03-25 2013-12-04 株式会社国際電気通信基礎技術研究所 Wireless device
JP6448889B2 (en) * 2013-03-29 2019-01-09 日本信号株式会社 Train control device

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6130347Y2 (en) * 1980-11-15 1986-09-05
JP3919342B2 (en) * 1998-07-14 2007-05-23 株式会社ケンウッド Wideband digital receiver
JP2000134174A (en) * 1998-10-22 2000-05-12 Victor Co Of Japan Ltd Ofdm receiver
JP2991236B1 (en) * 1999-01-21 1999-12-20 株式会社ワイ・アール・ピー移動通信基盤技術研究所 Error estimation apparatus for direct-sequence reception data and direct-sequence reception apparatus
JP2001102942A (en) * 1999-09-30 2001-04-13 Hitachi Kokusai Electric Inc Direct conversion receiver
JP4214992B2 (en) * 2004-12-13 2009-01-28 パナソニック株式会社 High frequency receiver, integrated circuit used therefor, portable device using the same, transmitter used therefor, and method for manufacturing the high frequency receiver and the portable device

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