JP2010192664A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device and a method of manufacturing the semiconductor by which a BiCMOS semiconductor integrated circuit device is manufactured at a low cost and a high yield. <P>SOLUTION: An epitaxial base layer 24 comprising a p-type single crystal semiconductor is formed in an island shape on a substrate region 17 of a semiconductor layer 2 surrounded by a shallow trench 3 and a deep trench 6. A silicon nitride film 42 and a silicon oxide film 43 are formed on an entire surface of the semiconductor layer 2 including the island region. At least two apertures are formed at the silicon nitride film 42 and silicon oxide film 43 in different positions of the island region, and a semiconductor film 44 is formed on the silicon nitride film 42 and the silicon oxide film 43 on which the aperture portions are formed. The semiconductor film 44 is selectively removed, and a base electrode connected to the island region in one aperture and an emitter electrode connected to the island region in the other aperture are simultaneously formed. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a bistro moss (hereinafter referred to as a heterojunction bipolar transistor (HBT) as a bipolar transistor) and a MOS transistor (Metal Oxide Semiconductor Field Effect Transistor; MOSFET). The present invention relates to a structure of a (BiCMOS) type semiconductor integrated circuit device and a manufacturing method thereof.

With the development of ultra-high-speed communication technology such as high-speed Internet communication network, the development of bipolar transistors with high-speed operability and high-current drive capability is progressing. Among them, the HBT is characterized in that it has excellent high-speed operation and high current drive capability as compared with the Si homojunction bipolar transistor. For example, an HBT using a heterojunction structure such as Si / SiC, Si / SiGe, or Si / SiGeC is an element formed on a silicon substrate, but has conventionally been a transistor using a compound semiconductor such as GaAs. The operation is possible even in a high-frequency region that could not be operated. In a silicon-based HBT, generally, a heterojunction structure of IV groups such as SiC, SiGe, and SiGeC formed by epitaxial growth is applied to the base layer.

In the heterojunction structure using SiC, SiGe, or SiGeC, the content and distribution are adjusted by adding Ge or C to Si. Thereby, tensile stress and compressive strain stress can be applied to the Si single crystal, and the band gap can be adjusted continuously. In general, tensile stress is applied in the SiC system, and compressive stress is applied in the SiGe system. With this heterojunction structure, the base current can be suppressed, and the current gain (h _FE ) of the transistor can be maintained high even when the impurity concentration in the base layer is increased to reduce the resistance of the base layer. In addition, the base travel time of the carrier can be shortened by utilizing the continuous change of the band gap, and a device with high frequency characteristics having high ft (cutoff frequency) and high fmax (maximum oscillation frequency) can be obtained.

The above heterojunction structure is a combination of Si substrate and group IV of SiC layer, SiGe layer, or SiGeC layer, so it is highly compatible with general-purpose silicon processes, and has great advantages in terms of device integration and cost reduction. It has. In particular, since heterojunction bipolar transistors and MOSFETs can be integrated on a common Si substrate, the characteristics of MOS-type transistors such as rail-to-rail output, low current consumption, and low power supply voltage, and high precision and high performance of bipolar transistors A high-performance BiCMOS integrated circuit device having both the characteristics of stability and low noise and the characteristics of high-speed operation of the heterojunction bipolar transistor can be configured (see Patent Documents 1 and 2).

  13 to 18 are process sectional views showing an example of a manufacturing process of a BiCMOS integrated circuit device including a conventional HBT (SiGe vertical HBT). The problems of the conventional manufacturing process and the conventional method will be described with reference to these drawings. Note that the vertical HBT refers to an HBT element in which the main part of the junction interface of npn forming the heterojunction bipolar element is parallel to the main surface of the Si substrate, and the carrier flow is accordingly in the vertical direction. Each figure (a) shows an HBT formation part, and each figure (b) shows a MOS transistor formation part (hereinafter referred to as a CMOS formation part) on the same substrate.

As shown in FIG. 13A, in the HBT formation portion of the BiCMOS integrated circuit device, a buried collector layer 101 is formed on the upper part of the Si semiconductor substrate 100 having the (001) crystal plane as the main surface. The buried collector layer 101 is formed by implanting and diffusing n-type impurities such as phosphorus (P) and arsenic (As), for example. Further, on the buried collector layer 101 the n ^- epitaxial layer 102 is formed. Element isolation is formed on the surface portion of the substrate having the structure. In the example of FIG. 13A, the element isolation is constituted by a portion of the shallow trench 103 in which silicon oxide (silicon oxide) is embedded, a non-doped (undoped) polysilicon film 104, and a silicon oxide film 105 surrounding it. The deep trench 106 is formed. In the example of FIG. 13A, Si substrate regions 107 and 108 separated by the shallow trench 103 are formed in the n ⁻ epitaxial layer 102. The Si substrate region 107 is an HBT element formation region, and the Si substrate region 108 is a region used as an n ⁺ collector extraction layer of the HBT element.

On the other hand, as shown in FIG. 13B, the CMOS forming portion of the BiCMOS integrated circuit device includes an n-type MOS transistor forming region 116 and a p-type MOS transistor forming region 117. Here, the n-type MOS transistor formation region 116 includes an n-type gate electrode 109a provided on the p-type diffusion layer 112, an LDD (Lightly Doped Drain) sidewall spacer 111, an n ⁻ region 113 serving as an LDD, and n An n-type MOS transistor composed of ⁺ source / drain regions 122 and 123 is formed. The p-type MOS transistor formation region 117 includes a p-type gate electrode 109b provided on the n-type diffusion layer 114, an LDD sidewall spacer 111, a p ⁻ region 115 serving as an LDD, and a p ⁺ source / drain region 120. , 121 is formed as a p-type MOS transistor. The n-type MOS transistor formation region 116 and the p-type MOS transistor formation region 117 are separated by a shallow trench 103.

In the text, subscripts − and subscripts + such as n ⁻ , n ⁺ , p ⁻ and p ^{+ in} the figure represent the concentration. The subscript-meaning low concentration indicates a concentration on the order of approximately 10 ¹⁶ to 10 ¹⁸ cm ^-3 , and the subscript + indicating high concentration indicates a concentration on the order of approximately 10 ¹⁹ to 10 ²⁰ cm ^-3. Yes.

  As shown in FIGS. 13A and 13B, a protect layer is formed in the HBT formation portion and the CMOS formation portion. The protect layer is a film in which a silicon oxide (silicon oxide) film 118 and a non-doped (undoped) polysilicon film 119 are deposited in order from the lower layer. In the protection layer, an opening through which the HBT element formation region 107 is exposed is formed by dry etching. This protective layer is a sacrificial protective film that is necessary for process processing in forming the HBT element, but does not become an element component. Further, as shown in FIG. 13B, since the CMOS region is covered with the protection layer, it is masked for processing for forming the HBT element. At the stage where the formation of the HBT element shown in FIG. 13B is started, the formation of all the components of the MOS transistor including the source / drain regions has been completed.

  Next, as shown in FIG. 14A, a heterojunction structure 124 composed of a SiC layer, a SiGe layer, or a SiGeC layer is formed on the HBT element formation region 107 by epitaxial growth. FIG. 14B is a cross-sectional view showing the state of the CMOS formation portion in the process shown in FIG. 14A, but the heterojunction structure 124 is selectively formed only on the HBT element formation region 107. There is no change above.

  Subsequently, as shown in FIGS. 15A and 15B, a silicon oxide film 125 is deposited on the HBT formation portion and the CMOS formation portion. In the silicon oxide film 125, an opening exposing a specific portion of the HBT element formation region 107 (in FIG. 15A, an inclined portion of the mesa portion) is formed by wet etching. After the opening is formed, as shown in FIGS. 16A and 16B, a non-doped polysilicon film 126 and a silicon oxide film 127 are further deposited on the entire HBT formation portion and the CMOS formation portion. . The layer film is used as a base lead electrode of the HBT element.

  Next, a part of the non-doped polysilicon film 126 and the silicon oxide film 127 on the heterojunction structure 124 is selectively etched away, and an emitter opening region occupying about half of the island region made of the heterojunction structure 124 is formed. It is formed. In the etching, the silicon oxide film 125 functions as a dry etching stopper film. Thereafter, a thin silicon oxide film 128 and impurity-doped polysilicon are deposited on the entire surface, and the entire surface is etched back. As a result, sidewall spacers 129 made of impurity-doped polysilicon are formed in the emitter opening region. At this time, the interval between the sidewall spacers 129 facing each other in the emitter opening region determines the emitter width W and the emitter length L. In FIG. 16A, the opening width in the left-right direction in the drawing is defined as the emitter width W, and the opening width in the direction perpendicular to the paper surface is defined as the emitter length L.

  When the emitter opening region is formed, as shown in FIG. 17A, after the silicon oxide films 128 and 125 exposed between the sidewall spacers 129 are removed, n-type impurities used as the emitter electrode are removed. A doped polysilicon film is deposited. The polysilicon film and the silicon oxide film 127 are selectively etched to form the emitter electrode 130. At this time, the silicon oxide film 127 in the CMOS formation portion is completely removed as shown in FIG. Thereafter, as shown in FIG. 18A, the non-doped polysilicon film 126 is patterned, and the external base electrode 131 is formed. At this time, in the CMOS formation portion, as shown in FIG. 18B, the non-doped polysilicon film 126, the silicon oxide film 125, and the non-doped polysilicon film 119 are all removed as in the HBT element formation region. The silicon film 118 is left.

As described above, in the CMOS forming portion, after the protection layer is formed, the deposited film is removed entirely by etching for processing the HBT element.
JP 2000-332025 A JP 2002-208690 A

  However, the above prior art has the following problems.

  First, in order to form an HBT element, as described above, many films need to be deposited and masked for their removal and processing. In the case of a general vertical HBT element, as described above, in particular, when separating and forming the epitaxial base layer formed of the heterojunction structure 124 and the polysilicon film constituting the emitter electrode 130 and the like, A process is required. That is, a deposition process of various insulating films and polysilicon films, a masking process for processing the deposited film, a dry etching process, a wet etching process, and the like are necessary, and the number of processes is necessarily increased. In addition, a film deposition for forming the sidewall spacer 129 and a process for processing the film are also required. Further, since it is necessary to form the emitter electrode 130 and the external base electrode 131 separately, a masking process for processing them is also required twice. Since reduction of the number of processes is extremely effective for reducing the manufacturing cost, in the BiCMOS integrated circuit device, sharing of the process between the HBT element forming process and the MOSFET element forming process is an important issue. That is, whether or not the process can be shared appears as a difference between the number of masks and the number of processes, and increases or decreases the manufacturing cost.

  Second, in the prior art, as described above, the side wall spacer 129 is often formed on the epitaxial base layer, and the oxidation for separating the emitter base layer in the opening in which the side wall spacer 129 is formed. The film thickness of the silicon film 125 is extremely thin. Therefore, when the processing margin of the sidewall spacer 129 becomes small due to the miniaturization of processing dimensions, the epitaxial base layer and the emitter electrode 130 formed thereon are brought into contact with each other through the silicon oxide film 125, and short-circuiting defects frequently occur. To come. In addition, in the HBT element, since the relationship of intrinsic base resistance ∝ (emitter width W / emitter length L) × sheet resistance Rsbi of intrinsic base layer 124 is established, the base resistance is reduced by reducing the emitter width W. Is possible. However, in the above-described conventional structure, the side wall spacer 129 in the opening where the emitter electrode 130 is formed defines the contact area between the epitaxial base layer and the emitter electrode. For this reason, a space for arranging the sidewall spacer 129 is required, and there is a limit to miniaturization of the emitter opening. Therefore, from the viewpoint of realizing a finer structure, a structure that can maintain a low base resistance and does not have the sidewall spacer 129 is desired.

  Third, as shown in FIG. 18A, the vertical HBT element has a large step at the emitter electrode 130 portion. Therefore, an interlayer insulating film is formed on the HBT formation portion and the CMOS formation portion in a step after FIG. 18A and FIG. 18B, and the surface is flattened by CMP (chemical mechanical polishing) or the like. In this case, the difference in aspect ratio (ratio of pattern width to depth) between the contact hole formed on the emitter electrode 130 and the contact hole on the silicon substrate formed in the CMOS formation portion becomes large. When such a contact hole with a large aspect ratio is simultaneously dry-etched, the contact hole of the emitter electrode 130 is shallow, so that there is a high possibility that excessive overetching or damage of implantation of etching ions into the bottom of the contact hole will occur.

  Fourth, in the structure of the emitter electrode 130 and the external lead base electrode 131 shown in FIGS. 18A and 18B, the end of each electrode is formed so that a contact hole can be reliably formed on each electrode. It is necessary to secure a margin to the contact hole. When a mask alignment shift occurs when a contact hole is formed on the electrode by dry etching, the contact hole is formed in a misaligned state. At this time, when the contact hole protrudes from the electrode, an opening is also formed in the insulating film formed around the electrode. There is a possibility that the emitter or the base and other unrelated parts are short-circuited through the contact hole.

  The present invention has been proposed in view of the above-described conventional circumstances, and provides a semiconductor device capable of realizing a BiCMOS type semiconductor integrated circuit device at a low cost and a high manufacturing yield, and a manufacturing method thereof. Objective.

  In order to solve the above problems, the present invention employs the following technical means. That is, the semiconductor device according to the present invention includes the first conductivity type semiconductor layer. A first region surrounded by the element isolation region of the semiconductor layer includes an island region made of a single crystal semiconductor of a second conductivity type that is opposite to the first conductivity type. In addition, a collector extraction layer formed in a second region different from the first region of the semiconductor layer, and a first layer formed in the semiconductor layer across the first region and the second region. A conductive collector layer. Furthermore, the base electrode is formed of a second conductivity type semiconductor film formed in contact with a predetermined portion of the surface of the island region, and is formed in contact with other portions of the island region apart from the base electrode. An emitter electrode made of a first conductivity type semiconductor film is provided. In the semiconductor device according to the present invention, the base electrode and the emitter electrode are formed by processing a common semiconductor film formed on the semiconductor layer.

On the other hand, in another aspect, the present invention can provide a method for manufacturing a semiconductor device suitable for manufacturing the semiconductor device. That is, in the method of manufacturing a semiconductor device according to the present invention, first, an element isolation region is formed in the first conductivity type semiconductor layer. Next, in the first region of the semiconductor layer surrounded by the element isolation region, an island region made of a second conductivity type single crystal semiconductor having a conductivity type opposite to the first conductivity type is formed. Subsequently, an insulating film is formed on the entire surface of the semiconductor layer including the island region. At least two openings are formed in the insulating film at different positions on the island region, and a semiconductor film is formed over the insulating film in which the openings are formed. Then, a part of the semiconductor film is removed, and a base electrode connected to the island region in one opening and an emitter electrode connected to the island region in the other opening are formed at the same time. Thereafter, a second conductivity type impurity is introduced into the base electrode, and a first conductivity type impurity is introduced into the emitter electrode. In addition, a collector extraction layer is formed by introducing an impurity of the first conductivity type into a second region of the semiconductor layer different from the first region. For example, the semiconductor layer is made of silicon, and the island region is made of a Si-IV group single crystal semiconductor such as a SiGe single crystal semiconductor, a SiC single crystal semiconductor, or a SiGeC single crystal semiconductor.

  In the semiconductor device and the semiconductor device manufacturing method, the base electrode and the emitter electrode are formed by processing a common semiconductor film. Therefore, in the conventional method, the insulating film interposed between the emitter electrode and the base electrode can be reduced. As a result, the number of insulating film depositions and processings can be reduced, and the manufacturing cost can be reduced. In addition, since the gate electrode and the emitter electrode can be electrically separated without forming a sidewall spacer at the connection portion between the emitter electrode and the island region, the gate electrode and the emitter electrode can be manufactured with a high manufacturing yield even when the pattern size is miniaturized. be able to. In addition, since it is not necessary to form sidewall spacers, it is easy to reduce the emitter size. Furthermore, since the emitter electrode is not laminated on the base electrode as in the prior art, the height of the emitter electrode can be reduced compared to the conventional case, and the level difference caused by the gate electrode and the emitter electrode is suppressed. can do.

  In the method for manufacturing a semiconductor device, the manufactured semiconductor device includes a first MOS transistor having a first conductivity type channel and a second conductivity type in a region of a semiconductor layer different from the first and second regions. A second MOS transistor having a channel may be provided. In this case, in the step of introducing the impurity into the emitter electrode, the source region or the drain region of the first MOS transistor is simultaneously formed, and in the step of introducing the impurity into the base electrode, the source region or the second MOS transistor is formed. A configuration in which the drain region is formed at the same time can be employed. Thereby, in the manufacturing method of a semiconductor device, the number of steps for introducing impurities can be reduced as compared with the conventional method.

  In this method of manufacturing a semiconductor device, an interlayer insulating film is further formed on the semiconductor layer so as to cover the gate electrode, the emitter electrode, the first MOS transistor, and the second MOS transistor. A contact hole penetrating through may be formed at the same time. The contact holes formed simultaneously include, for example, a gate electrode, an emitter electrode, a gate electrode, a source electrode and a drain electrode of the first MOS transistor, and a gate electrode, a source electrode and a drain electrode of the second MOS transistor. It is particularly suitable for reaching each. As described above, since the step due to the gate electrode and the emitter electrode can be suppressed, when the MOS transistor is formed on the same substrate, the emitter electrode has the same height as the gate electrode of the MOS transistor. Become. Therefore, the aspect ratio difference between each contact hole for forming a contact connected to each electrode of the MOS transistor and each contact hole for forming a contact with each electrode of the HBT element can be reduced. As a result, damage that has conventionally occurred due to dry etching when forming contact holes in the interlayer insulating film can be significantly reduced.

  From the viewpoint of further reducing the number of processes, the introduced impurity is the same in the emitter electrode, the base electrode, the source region or drain region of the first MOS transistor, and the source region or drain region of the second MOS transistor. It is preferable to adopt a configuration that is activated in the heat treatment step.

  Note that in the step of removing a part of the semiconductor film, the etching for removing the semiconductor film is performed in a state where there is no etching mask on the semiconductor film serving as the emitter electrode and the etching mask is present on the semiconductor film serving as the base electrode. Can be implemented. Thereby, the emitter electrode embedded in the other opening can be formed in a self-aligned manner. In addition, when forming a contact hole for forming a contact connected to the emitter electrode, the contact hole is formed by applying an insulating film exposed around the emitter electrode and dry etching conditions with a high selectivity. The alignment margin of the contact hole on the emitter electrode can be remarkably reduced. Therefore, a contact hole having a large opening diameter can be formed as compared with the conventional method, and the contact area between the contact plug and the emitter electrode can be increased. Further, when realizing the same contact resistance as the conventional one, the area of the emitter electrode can be made smaller than the conventional one. Therefore, the contact hole formed on the emitter electrode can be configured to include the emitter electrode in plan view.

  According to the present invention, compared with the conventional method, the number of steps such as deposition and processing of the insulating film can be greatly reduced, and the manufacturing cost can be reduced. Further, since it is not necessary to form a sidewall spacer at the connection portion between the emitter electrode and the island region, a semiconductor device can be manufactured with a high manufacturing yield even when the pattern dimension is miniaturized. Furthermore, the emitter size can be easily reduced, and the base resistance can be easily reduced. In addition, since a step due to the gate electrode or the emitter electrode can be suppressed, in the BiCMOS type semiconductor device, the aspect ratio difference of the contact hole for forming the contact connected to each of the HBT element and the MOS transistor is reduced. The manufacturing yield can be increased.

  In the present invention, the emitter electrode has a buried structure, so that the alignment margin of the contact hole on the emitter electrode can be remarkably reduced, and a contact hole having a large opening diameter can be formed. As a result, the contact area between the contact plug and the emitter electrode can be increased as compared with the conventional case.

  Hereinafter, an embodiment according to the present invention will be described in detail with reference to the drawings. The embodiments of the present invention can be modified into various alternative embodiments, and the scope of the present invention should not be construed as being limited by the embodiments described below.

  1 to 10 are process cross-sectional views illustrating a manufacturing process of a semiconductor device according to an embodiment of the present invention. The semiconductor device exemplified in this embodiment is a semiconductor integrated circuit device including a SiGe vertical HBT as a bipolar transistor and a low-voltage drive CMOS device as a MOS transistor. The elements indicated by the same reference numerals on the respective drawings mean the same elements, each figure (a) shows an HBT formation part, and each figure (b) shows a MOS transistor formation part (hereinafter referred to as the following) on the same substrate. This is referred to as a CMOS formation portion.

  As shown in FIG. 1A, in the HBT formation portion of the BiCMOS integrated circuit device according to the present embodiment, the buried collector layer 1 is formed on the upper part of the Si semiconductor substrate 10 having the (001) crystal plane as the main surface. ing. The buried collector layer 1 is formed, for example, by implanting n-type impurities such as phosphorus (P) and arsenic (As) into the Si semiconductor substrate 10 at a high concentration. The buried collector layer 1 is formed in a state where a resist mask or the like covering the region for forming the CMOS type transistor in the CMOS forming portion is provided. For this reason, as shown in FIG. 1B, the buried collector layer 1 is not formed in the region where the CMOS transistor is formed in the CMOS formation portion.

After the formation of the buried collector layer 1, the n-type low impurity concentration semiconductor layer 2 is formed on the surface of the Si semiconductor substrate 10 by Si epitaxial growth. An element isolation region is formed on the surface portion of the substrate on which the semiconductor layer 2 is formed. In the example of FIG. 1A, the element isolation region is composed of a shallow trench 3 and a deep trench 6. Here, the shallow trench 3 is formed by embedding a silicon oxide (silicon oxide) film in a shallow trench formed in the substrate. The deep trench 6 is formed by embedding a non-doped (undoped) polysilicon film 4 in a deep trench having a silicon oxide film 5 formed on the surface. In the example of FIG. 1A, Si substrate regions 7 and 8 separated by a shallow trench 3 are formed in the n ⁻ epitaxial semiconductor layer 2 of the HBT formation portion. The Si substrate region 7 is an HBT element formation region (first region), and the Si substrate region 8 is used as an n ⁺ collector extraction layer formation region (second region). The shallow trench 3 is an element isolation for isolating at least the semiconductor layer 2, and the deep trench 6 is an element isolation region for isolating at least the buried collector layer 1 and a well layer (described later) of the CMOS formation portion.

On the other hand, as shown in FIG. 1B, the CMOS forming portion of the BiCMOS integrated circuit device according to this embodiment includes an n-type MOS transistor forming region 16 and a p-type MOS transistor forming region 17. An n-type MOS transistor is formed in the n-type MOS transistor formation region 16, and an n-type MOS transistor is formed in the p-type MOS transistor formation region 17. In this embodiment, at the time when the formation of the HBT element is started in the HBT formation portion (at the time when formation of a heterojunction structure 24 described later is started), the n-type MOS transistor formation region 16 has a low impurity concentration that is a P well. A gate electrode 9a made of an n-type polysilicon film provided on the p-type diffusion layer 12, an LDD (Lightly Doped Drain) sidewall spacer 11, and an n ⁻ region 13 which is an n-type low impurity concentration LDD are formed. . In the p-type MOS transistor formation region 17, a p-type gate electrode 9 b made of a p-type polysilicon film provided on the low impurity concentration n-type diffusion layer 14 which is an N well, an LDD sidewall spacer 11, p A p ⁻ region 15, which is a type low impurity concentration LDD, is formed. The n-type MOS transistor formation region 16 and the p-type MOS transistor formation region 17 are separated only by the shallow trench 3.

As in the prior art, subscripts − and subscripts + such as n ⁻ , n ⁺ , p ⁻ and p ⁺ in the text and drawings represent the concentration. The subscript-meaning low concentration indicates a concentration on the order of approximately 10 ¹⁶ to 10 ¹⁸ cm ^-3 , and the subscript + indicating high concentration indicates a concentration on the order of approximately 10 ¹⁹ to 10 ²⁰ cm ^-3. Yes.

In the above-described prior art, the formation of the HBT element is started after the high impurity concentration source / drain diffusion layers (n ⁺ source / drain regions 122 and 123 and p ⁺ source / drain regions 120 and 121) in the CMOS forming portion are formed. However, in this embodiment, as shown in FIGS. 1A and 1B, the source / drain regions (high-concentration impurity regions) of the MOS transistor are still formed at the start of the formation of the HBT element. Not. In this embodiment, the source / drain regions of the MOS transistor are formed simultaneously with the implantation into the emitter electrode and base electrode of the HBT element, as will be described later. As a result, the HBT formation process and the MOS transistor formation process are shared, thereby realizing process reduction and cost reduction. Note that the structure of the MOS transistor shown in FIG. 1B can be formed by a well-known method, and thus description thereof is omitted here.

  Subsequently, as shown in FIG. 2A, an insulating film 41 is formed on the entire surface. Here, a silicon oxide film is deposited as the insulating film 41 by LP-CVD (low pressure chemical vapor deposition). The insulating film 41 is not limited to a silicon oxide film, and may be a silicon nitride film. Thereafter, a resist mask (not shown) having an opening exposing HBT element formation region 7 is formed on insulating film 41. Here, the opening end of the resist mask is located on the shallow trench 3 that partitions the HBT element formation region 7. Then, the insulating film 41 corresponding to the opening is removed by etching the insulating film 41 using the resist mask as an etching mask. In the conventional method shown in FIGS. 14A and 14B, two layers of a silicon oxide film 118 and a non-doped polysilicon film 119 are deposited as a protective layer. On the other hand, in this embodiment, since one insulating film is deposited, the process is reduced in this respect as well.

  Subsequently, an island-like heterojunction structure 24 composed of a SiGe layer doped with a p-type impurity is formed by epitaxial growth on the Si substrate region 7 exposed in the opening formed in the insulating film 41. The SiGe layer functions as a base conductive layer (epitaxial base layer). The heterojunction structure 24 may be composed of a SiC layer or a SiGeC layer. FIG. 2B is a cross-sectional view showing a state of the CMOS formation portion when the heterojunction structure 24 is formed on the Si substrate region 7. Since the heterojunction structure 24 is selectively formed only on the HBT element formation region 7, there is no heterojunction structure in the CMOS formation portion.

Subsequently, as shown in FIG. 3A, a silicon nitride film 42 and a silicon oxide film 43 are sequentially deposited from the lower layer on the entire substrate including the heterojunction structure 24 by LP-CVD. A resist mask 51 is formed on the deposited silicon oxide film 43 to cover the region of the heterojunction structure 24 excluding the external base layer formation region and the emitter layer formation region. By etching using the resist mask 51, the silicon oxide film 43 and the silicon nitride film 42 are sequentially patterned to form an external base layer formation region 91 and an emitter layer formation region 92 where the heterojunction structure 24 is exposed on the surface. Is done. In this embodiment, the insulating film 41 made of a silicon oxide film functions as an etching stopper film when the silicon nitride film 42 is etched. For example, wet etching using a diluted etching solution of hydrofluoric acid can be applied to the etching of the silicon oxide film 43, and wet etching using hot phosphoric acid at about 150 ° C. is applied to the etching of the silicon nitride film 42. be able to. Alternatively, dry etching using a fluorocarbon-based mixed gas such as CHF ₃ can be applied as an etching gas. In this etching, since the CMOS formation portion is not covered with the resist mask 51, the silicon nitride film 42 and the silicon oxide film 43 on the insulating film 41 are all removed as shown in FIG.

  After removing the resist mask 51, a non-doped polysilicon film 44 is deposited on the entire surface, as shown in FIGS. 4 (a) and 4 (b). The film need only be non-doped, and is not limited to polysilicon, and a single crystal or amorphous silicon film can also be used. Thereafter, as shown in FIG. 5A, a resist mask 52 is formed on the non-doped polysilicon film 44 to cover portions corresponding to the external base electrode and the emitter electrode. By etching the polysilicon film 44 using the resist mask 52, the external base electrode 31 and the emitter electrode 32 are formed. At this time, the polysilicon film 44 is selectively etched away with respect to the insulating film 41 and the silicon oxide film 43. Since the resist mask 52 is not formed in the CMOS formation portion, the polysilicon film 44 is completely removed and the insulating film 41 is exposed as shown in FIG. 5B.

  When the formation of the pattern of the external base electrode 31 and the pattern of the emitter electrode 32 is completed as described above, as shown in FIGS. 6A and 6B, the region including the external base electrode 31 and the p-type are formed. A resist mask 53 having an opening is formed in the MOS transistor formation region 17. By using the resist mask 53 as an ion implantation mask, p-type impurities are ion-implanted at a high concentration, whereby a p-type layer 33 having a high impurity concentration is formed on the surface of the external base electrode 31. The electrode 9b becomes p-type, and the p-type source 20 and the p-type drain 21 are formed simultaneously.

Subsequently, after removing the resist mask 53, as shown in FIGS. 7A and 7B, a region including the emitter electrode 32, a region including the Si substrate region 8 serving as an n ⁺ collector extraction layer, and n A resist mask 54 having an opening is formed in the type MOS transistor formation region 16. High-impurity concentration n-type layer 34 is formed on the surface of emitter electrode 32 by ion-implanting n-type impurities at a high concentration using resist mask 54 as an ion implantation mask. In n-type MOS transistor formation region 16, a gate electrode is formed. 9a becomes n-type, and n-type source 22 and n-type drain 23 are formed simultaneously. Thereafter, the resist mask 54 is removed.

  In the present embodiment, p-type impurity ions are implanted into the external base electrode 31 and the like first, and then n-type impurity ions are implanted into the emitter electrode 32 and the like. N-type impurity ion implantation may be performed, and then p-type impurity ion implantation may be performed. In this embodiment, the source / drain regions are formed in the CMOS forming portion by ion implantation of p-type and n-type impurities through the insulating film 41 as the protection layer. However, before the ion implantation, the insulating film 41 is formed. May be removed. Depending on the presence or absence of the insulating film 41, the implantation depth of the source / drain regions can be changed. It is also possible to control the implantation depth of the source / drain regions by controlling the film thickness of the insulating film 41. In this embodiment, since the insulating film 41 is a silicon oxide film, the insulating film 41 can be easily removed by wet etching using an etchant such as buffered hydrofluoric acid or diluted hydrofluoric acid.

  When the ion implantation is completed as described above, after the silicon oxide film 43 and the insulating film 41 exposed on the surface are removed by wet etching, as shown in FIGS. 8A and 8B, A thin silicon oxide film 45 is deposited on the entire surface of the substrate by low pressure CVD or normal pressure CVD. The silicon oxide film 45 is contacted with a contact region (a contact region of the external base electrode 31, a contact region of the emitter electrode 32, a contact region of the collector extraction layer, and a contact region of the CMOS formation portion) by using a photolithography technique and an etching technique. An opening is formed in the. After the opening is formed in the silicon oxide film 45, a cobalt (Co) film and a titanium (Ti) film are sequentially stacked on the entire surface of the substrate by sputtering. Heat treatment is performed in this state, and the external base electrode 31 and the emitter electrode 32 made of a polysilicon film exposed at the opening of the silicon oxide film 45 are reacted with Ti or Co to form an n-type silicon single layer. The silicon of the source 20, the n-type drain 21, the p-type source 22, and the p-type drain 23 is reacted with Ti or Co. As a result, silicide layers 61, 62, 63, 64, 65, 66, 67, 68, 69 are formed on the surface portions of the respective portions exposed to the opening of the silicon oxide film 45 and in contact with the cobalt film, and have low resistance. It becomes. The silicon oxide film 45 is removed after the silicide layers 61 to 69 are formed.

  In the subsequent processes, wirings connected to the HBT element, n-type MOS transistor, and p-type MOS transistor are formed by a standard multilayer wiring process. That is, as shown in FIGS. 9A and 9B, after an interlayer insulating film 46 made of an oxide film or the like is deposited on the substrate, a known lithography technique and etching technique are applied to the interlayer insulating film 46. As a result, contact holes 71, 72, 73, 74, 75, 76, 77, 78, and 79 that reach the silicide layers 61 to 69 through the interlayer insulating film 46 are formed.

  Thereafter, as shown in FIGS. 10A and 10B, after a Ti film and a TiN film are formed in the contact holes 71 to 79, a tungsten (W) film is embedded, and the surface is formed by CMP or the like. By removing unnecessary portions, W plugs 81, 82, 83, 84, 85, 86, 87, 88, 89 are formed. Next, an aluminum alloy film is formed on the substrate, and the aluminum alloy film is patterned by using a mask (not shown) having an opening in a predetermined portion, thereby being connected to each W plug and on the interlayer insulating film 46. A metal wiring (not shown) extending in the direction is formed. Such a wiring process is repeatedly performed as necessary to complete the semiconductor device.

  In the semiconductor device of the present embodiment configured as described above, the emitter electrode 32 of the HBT element and the external base electrode 31 are formed by processing the common semiconductor film 44, and between the emitter and base. Are separated from each other by the silicon nitride film 42 and the interlayer insulating film 46. In this structure, the external base electrode and the emitter electrode do not overlap each other as in the conventional technique separated by the extremely thin silicon oxide film 128 and the sidewall spacer 129. For this reason, even when the processing margin becomes small due to miniaturization of the processing dimensions, it is possible to suppress the occurrence of short-circuit failure between the base and the emitter. In addition, since there is no sidewall spacer, it is possible to easily reduce the emitter size by reducing the thickness of the insulating film between the emitter electrode 32 and the base electrode 31, compared with the conventional structure, and to easily reduce the base resistance. .

  Furthermore, in the configuration of this embodiment, the upper surface position of the emitter electrode 32 is lower than the conventional one by the thickness of the polysilicon film and the silicon oxide film 127 that constitute the external base electrode. As a result, the upper end of the emitter electrode 32 has the same height as the upper ends of the gate electrodes 9a and 9b of the CMOS element. Therefore, the depth of the contact hole formed in the interlayer insulating film 46 is almost the same on the external base electrode 31 and the emitter electrode 32, on the gate electrodes 9a and 9b, and on the source / drain regions 20 to 23. Compared to the structure, the aspect ratio difference between the contact holes is reduced. Therefore, excessive overetching, etching ion implantation damage, silicide film breakage, etc. during contact hole dry etching can be prevented, and as a result, a semiconductor device can be manufactured with a high manufacturing yield.

  By the way, in the manufacturing method of the above-mentioned semiconductor device, the same effect can be produced even when a part of the manufacturing process is changed. Hereinafter, the modification will be described with reference to FIGS. 11 and 12. FIGS. 11A and 11B are cross-sectional views showing processes corresponding to the processes described with reference to FIGS. 5A and 5B. In this modification, when the non-doped polysilicon film 44 is patterned, a resist mask 55 that covers a portion corresponding to the external base electrode and exposes a portion corresponding to the emitter electrode is formed in place of the resist mask 52 described above. . Then, the non-doped polysilicon film 44 is patterned by anisotropic dry etching through the resist mask 55. Thereby, a self-aligned buried emitter electrode 36 can be realized, and the occupied area of the HBT element can be reduced as compared with the above-described embodiment. As shown in FIG. 11B, the structure of the CMOS forming portion is not changed even when the semiconductor device manufacturing method according to this modification is applied.

  After the buried emitter electrode 36 is formed as described above, the p-type impurity is ion-implanted at a high concentration as described with reference to FIGS. A high impurity concentration p-type layer 33 is formed on the surface. In the p-type MOS transistor formation region 17, the gate electrode 9b becomes p-type, and the p-type source 20 and p-type drain 21 are formed simultaneously. Further, as described with reference to FIGS. 7A and 7B, n-type impurities are ion-implanted at a high concentration, whereby a high-impurity concentration n-type layer 34 is formed on the surface of the emitter electrode 36. In the n-type MOS transistor formation region 16, the gate electrode 9a becomes n-type, and the n-type source 22 and the n-type drain 23 are formed simultaneously.

  Subsequently, as shown in FIG. 12A, the silicon oxide film 43 and the insulating film 41 are removed, and contact regions (the contact region of the external base electrode 31, the contact region of the emitter electrode 36, the contact region of the collector extraction layer, and the contact region) A silicon oxide film 47 having an opening in the contact region of the CMOS formation portion is formed. Thereafter, a cobalt (Co) film and a titanium (Ti) film are sequentially laminated from the lower layer over the entire surface of the substrate by sputtering, and heat treatment is performed in this state, and the cobalt oxide film 47 is exposed to the opening of the silicon oxide film 47. A silicide layer is formed on the surface of each part in contact with the film. At this time, the emitter electrode 36 has a convex shape protruding upward from the upper surface of the silicon nitride film 42 by removing the silicon oxide film 33, and the silicide layer 62 is formed on the surface of the convex emitter electrode 36. It is formed. As shown in FIG. 12B, the CMOS forming portion is not different from the above-described embodiment. Thereafter, in the above-described embodiment, each process described with reference to FIGS. 9 to 10 is performed to complete the semiconductor device. The contact hole formed on the emitter electrode 36 preferably has an opening including the emitter electrode 36 in plan view.

  In this modification, the area of the emitter electrode 36 can be reduced as compared with the above-described embodiment. In addition, a contact hole larger than the emitter electrode itself (a contact hole including the emitter electrode in plan view) can be formed on the emitter electrode 36. This is because the periphery of the emitter electrode 36 is surrounded by the silicon nitride film 42 and is separated from the external base electrode 31 by a certain distance. That is, in the dry etching of the contact hole, the silicon nitride film 43 is used as an etching stopper film by adopting a condition in which the silicon oxide film constituting the interlayer insulating film 46 and the silicon nitride film 43 have a large etching rate selection ratio. This is because it can function. Further, since the emitter electrode 36 has a convex shape that protrudes upward from the upper surface of the silicon nitride film 42, the contact area between the contact plug and the emitter electrode 36 is also increased by forming a contact hole having a large opening diameter. Can be bigger.

  In the present modification, as described above, a contact hole can be formed in the entire emitter electrode. In addition to the effects described in the above embodiment, the contact area between the emitter electrode and the contact hole is increased to reduce the contact resistance. And the effect that the parasitic resistance can be reduced can be acquired.

  As described above, according to the present invention, the deposition process of various films and the dry etching process associated with the formation of the emitter electrode opening in the conventional method are not required, so that the number of processes can be greatly reduced. According to the invention, the external base electrode and the emitter electrode are simultaneously formed by processing a common semiconductor film, and the opening for connecting the external base electrode and the heterojunction structure (epitaxial base layer) is formed. An opening for connecting the part, the emitter electrode, and the heterojunction structure is simultaneously opened. Therefore, the photolithography process can be reduced twice compared with the conventional method in which the external base electrode and the emitter electrode are formed in separate processes. Further, the deposition process of the polysilicon film for the external base electrode and the emitter electrode can be reduced once.

  Further, in the present invention, after processing the emitter electrode and the base electrode of the HBT element, p-type and n-type impurity ions are implanted into the external base electrode and the emitter electrode, respectively, and at the same time, n-type, p Ion implantation is performed to form a high impurity concentration source / drain. In the conventional method, the high impurity concentration source / drain implantation in the CMOS forming portion is completed before the start of the HBT element formation, whereas in the present invention, the external base electrode implantation, the Pch-MOS source / drain implantation, and the emitter electrode implantation are performed. And Nch-MOS source / drain implantation are used to achieve significant process and cost reductions.

  Further, according to the present invention, since it is not necessary to provide a sidewall spacer in the opening for connecting the emitter electrode and the heterojunction structure, conventionally, there is no sidewall spacer having an emitter width W defined by the sidewall spacer interval. Can be extended by minutes. As a result, the conventional base resistance can be maintained even when the emitter size defined by the dimension of the opening is reduced. Alternatively, when the emitter size is the same as the conventional one, the base resistance can be reduced as compared with the conventional one.

  Furthermore, in the present invention, the height of the emitter electrode is close to the height of the external base electrode and the gate electrode of the CMOS transistor, so that the contact hole can be easily etched. In the present invention, the emitter electrode has a buried structure, so that the alignment margin of the contact hole on the emitter electrode can be remarkably reduced, and a contact hole having a large opening diameter can be formed. As a result, the contact area between the contact plug and the emitter electrode can be increased as compared with the conventional case.

  The present invention has been described based on the preferred embodiments. The present invention is not limited to the above-described embodiments, and various modifications can be made by those skilled in the art within the technical idea of the present invention. For example, each process such as film formation and etching shown in the above embodiment can be replaced with another equivalent process.

  According to the present invention, a BiCMOS type semiconductor integrated circuit device can be realized at a low cost and with a high manufacturing yield, which is useful as a semiconductor device and a manufacturing method thereof.

Sectional drawing which shows the manufacture process of the semiconductor device in one Embodiment of this invention Sectional drawing which shows the manufacture process of the semiconductor device in one Embodiment of this invention Sectional drawing which shows the manufacture process of the semiconductor device in one Embodiment of this invention Sectional drawing which shows the manufacture process of the semiconductor device in one Embodiment of this invention Sectional drawing which shows the manufacture process of the semiconductor device in one Embodiment of this invention Sectional drawing which shows the manufacture process of the semiconductor device in one Embodiment of this invention Sectional drawing which shows the manufacture process of the semiconductor device in one Embodiment of this invention Sectional drawing which shows the manufacture process of the semiconductor device in one Embodiment of this invention Sectional drawing which shows the manufacture process of the semiconductor device in one Embodiment of this invention Sectional drawing which shows the manufacture process of the semiconductor device in one Embodiment of this invention Process sectional drawing which shows the manufacture process of the semiconductor device in the modification of one Embodiment of this invention Process sectional drawing which shows the manufacture process of the semiconductor device in the modification of one Embodiment of this invention Process sectional view showing the manufacturing process of a conventional semiconductor device Process sectional view showing the manufacturing process of a conventional semiconductor device Process sectional view showing the manufacturing process of a conventional semiconductor device Process sectional view showing the manufacturing process of a conventional semiconductor device Process sectional view showing the manufacturing process of a conventional semiconductor device Process sectional view showing the manufacturing process of a conventional semiconductor device

10, 100 Silicon substrate 1, 101 Embedded collector layer 2, 102 Semiconductor layer 3, 103 Shallow trench 4, 104 Non-doped polysilicon 5, 105 Silicon oxide film 6, 106 Deep trench 7 Si substrate region (first region)
8 Si substrate region (second region)
9a, 109a n-type gate electrode 9b, 109b p-type gate electrode 16, 116 n-type MOSFET formation region 17, 117 p-type MOSFET formation region 20, 120 p-type MOSFET source region 21, 121 p-type MOSFET drain region 22, 122 n Type MOSFET source region 23, 123 n type MOSFET drain region 24, 124 heterojunction epitaxial film 31, 131 base electrode 32, 130 emitter electrode 33 base electrode p ⁺ injection layer 34 emitter electrode n ⁺ injection layer 35 collector extraction layer n ⁺ injection Layer 36 Embedded emitter electrode 41 Insulating film (silicon oxide film)
42 Silicon nitride film 43 Silicon oxide film 44 Non-doped polysilicon films 45 and 47 Silicon oxide film 46 Interlayer insulating films 51 to 55 Resist masks 61 to 69 Silicide layers 71 to 79 Contact holes 81 to 89 Contact plugs

Claims (9)

A first conductivity type semiconductor layer;
An island region made of a single crystal semiconductor of a second conductivity type that is opposite to the first conductivity type, formed in a first region of the semiconductor layer surrounded by an element isolation region;
A collector extraction layer formed in a second region of the semiconductor layer different from the first region;
A collector layer of a first conductivity type formed inside the semiconductor layer over the first region and the second region;
A base electrode made of a semiconductor film of a second conductivity type formed in contact with a predetermined portion of the surface of the island region;
An emitter electrode made of a semiconductor film of a first conductivity type formed apart from the base electrode and in contact with the other part of the island region;
With
The semiconductor device, wherein the base electrode and the emitter electrode are formed by processing a common semiconductor film formed on the semiconductor layer. The semiconductor layer is made of silicon, and the island region is made of a Si-IV group single crystal semiconductor.
The semiconductor device according to claim 1. Forming an element isolation region in the semiconductor layer of the first conductivity type;
Forming in the first region of the semiconductor layer surrounded by the element isolation region an island region made of a second conductivity type single crystal semiconductor having a conductivity type opposite to the first conductivity type;
Forming an insulating film on the entire surface of the semiconductor layer including the island region;
Providing openings at different positions of the insulating film formed on the island region;
Forming a semiconductor film on the insulating film in which the opening is formed;
Removing a part of the semiconductor film and simultaneously forming a base electrode connected to the island region in one opening and an emitter electrode connected to the island region in the other opening;
Introducing a second conductivity type impurity into the base electrode and introducing a first conductivity type impurity into the emitter electrode;
Introducing a first conductivity type impurity into a second region of the semiconductor layer different from the first region to form a collector extraction layer;
A method for manufacturing a semiconductor device, comprising: The semiconductor device includes a first MOS transistor having a first conductivity type channel and a second MOS transistor having a second conductivity type channel in a region of the semiconductor layer different from the first and second regions. With
In the step of introducing an impurity into the emitter electrode, a source region or a drain region of the first MOS transistor is simultaneously formed,
The method for manufacturing a semiconductor device according to claim 3, wherein in the step of introducing an impurity into the base electrode, a source region or a drain region of the second MOS transistor is simultaneously formed. Forming an interlayer insulating film on the semiconductor layer, covering the gate electrode, the emitter electrode, the first MOS transistor, and the second MOS transistor;
Passing through the interlayer insulating film, the gate electrode, the emitter electrode, the gate electrode, the source electrode and the drain electrode of the first MOS transistor, and the gate electrode, the source electrode and the drain electrode of the second MOS transistor Simultaneously forming contact holes reaching each of the
The method for manufacturing a semiconductor device according to claim 4, further comprising:   Impurities introduced into the emitter electrode, the base electrode, the source region or drain region of the first MOS transistor, and the source region or drain region of the second MOS transistor are activated in the same heat treatment step. The method of manufacturing a semiconductor device according to claim 4, wherein   In the step of removing a part of the semiconductor film, the etching for removing the semiconductor film has no etching mask on the semiconductor film to be the emitter electrode, and there exists an etching mask on the semiconductor film to be the base electrode. The method for manufacturing a semiconductor device according to claim 3, wherein the emitter electrode is formed in a state and is embedded in the other opening.   The method of manufacturing a semiconductor device according to claim 7, wherein the contact hole formed on the emitter electrode includes the emitter electrode in a plan view.   9. The method of manufacturing a semiconductor device according to claim 3, wherein the semiconductor layer is made of silicon, and the island region is made of a Si—IV group single crystal semiconductor.

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