JP2010191758A - Verification support program, verification support device, and verification support method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To efficiently execute simulation of a multi-CPU system at a high speed. <P>SOLUTION: A verification support device 100 executes simulation of software 101 to be verified by a multi-CPU simulator 110 to obtain a simulation result 102, uses a multi-CPU scheduler 200 to sort an instruction group to be executed by a multi-CPU model 210 in order of time, calculating an execution interval of the instruction group, and executes simulation of the instruction group by necessary minimum processing because of giving an instruction to execute a corresponding instruction at each execution interval. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a verification support program, a verification support apparatus, and a verification support method for simulating an instruction that has received an execution instruction using a multiprocessor model in which a plurality of processors are implemented by software.

  In recent years, in the case of a system having a certain scale or more, such as an electronic device for in-vehicle use, a technology related to a multi-CPU system that improves processing speed by preparing a plurality of CPUs and operating each CPU in a coordinated manner, Many technologies related to a multi-CPU system that facilitates development by assigning one CPU for each function are used. When verifying software to be executed by these multi-CPU systems, the multi-CPU model simulator in which the multi-CPU is realized by software is often used because it is more convenient for the user than the actual machine and can be simulated at high speed. (For example, see Patent Document 1 below.)

  FIG. 13 is a block diagram showing a configuration of a conventional multi-CPU simulator. As shown in FIG. 13, the conventional multi-CPU simulator 1300 performs execution control of a plurality of CPU models 11 (for example, CPU models 1 and 2) and inter-CPU communication control by the multi-CPU scheduler 10. In the multi-CPU simulator 1300 shown in FIG. 13, two CPU models 11 are prepared to perform a simulation when two CPUs operate cooperatively. Therefore, when simulating an operation by a multi-CPU system having a larger number of CPUs, a CPU model corresponding to the system configuration is prepared.

  And FIG. 14 is explanatory drawing which shows operation | movement of the conventional multi CPU simulator. When the multi-CPU scheduler 10 loads the software to be verified, the CPU model 11 is synchronized by transmitting an instruction to execute the corresponding instruction (transaction etc.) to each CPU model 11 every predetermined unit time. . For example, in the case of the multi-CPU scheduler 10, an instruction (when there is an instruction to be executed) is executed every unit time of 0.25 [ms]. Therefore, in the operation illustrated in FIG. 14, an instruction execution instruction is transmitted from the multi-CPU scheduler 10 at timings 0.25, 0.5, and 0.75 [ms] per unit time, and the synchronization of each CPU model 11 is performed. Is managed. Then, when the processing of all the CPU models 11 under the control of the multi-CPU scheduler 10 is completed, the processing shifts to processing at the next execution time.

  In addition, a conventional multi-CPU system has a configuration in which a plurality of CPUs are connected by a predetermined network in order to realize data transmission / reception between CPUs, and a multi-CPU simulator corresponding to such a system is also provided. . FIG. 15 is a block diagram showing a configuration of a multi-CPU simulator in which CPUs are connected by a network circuit. As shown in FIG. 15, in the multi-CPU simulator 1500, a network circuit 12 for connecting each CPU model 11 is prepared. Therefore, the multi-CPU scheduler 10 manages instructions to be executed by each CPU model 11 by performing inter-CPU communication control via the network circuit 12.

  FIG. 16 is an explanatory diagram showing the operation of the multi-CPU simulator in which the CPUs are connected by a network circuit. A case where 1 [byte] data is transmitted from the CPU model 1 to the CPU model 2 at a timing of 0.27 [ms] will be described with reference to FIG. The transmission speed of the network circuit 12 is 19.2 [kbps]. Then, the data transmission to the CPU model 2 is completed at the timing of 0.67 [ms], so that a delay of about 400 [μs] occurs. As described above, since the multi-CPU scheduler 10 synchronizes the CPU models of the multi-CPU model 11 at every timing of 0.25 [ms], the CPU model 1 is at timing of 0.5 [ms]. Is sent to the CPU model 2.

JP 2008-59192 A

  However, in the case of the conventional multi-CPU simulator as described above, if the multi-CPU system is highly integrated and the processing performance is improved, if the data transmission speed between the CPUs is increased, the transaction may not be synchronized. There is. FIG. 17 is an explanatory diagram showing the operation of the multi-CPU simulator in which the CPUs are connected by a high-speed network circuit. The data transmission between the CPUs when the transmission speed of the network circuit 12 of the multi-CPU simulator 1500 described in FIG. 15 is increased to 1 [Mbps] will be described using FIG.

  As shown in FIG. 17, when data of 4 [bytes] is transmitted to the CPU model 2 from the CPU model 1 at the timing of 270 [μs] (the same timing as 0.27 [ms] in FIG. 16), it is about 32 [μs]. ] Delay occurs. That is, data transmission to the CPU model 2 is completed at a timing of 302 [μs]. However, since the next synchronization management timing by the multi-CPU scheduler 10 is 0.50 [ms], the CPU model 2 cannot be notified of the data transmission request from the CPU model 1 when the data transmission is completed. Therefore, there is a problem that it cannot be processed as a normal transaction.

  Even in a multi-CPU system in a high-speed transmission environment, in order to perform normal transaction processing, it is necessary to set a shorter unit time interval for synchronization between CPUs. For example, if the multi-CPU scheduler 10 is set to synchronize every 25 [μs] intervals as shown between 0.5 and 0.75 [ms] in FIG. 17, normal transactions can be performed. However, since the number of calculations for synchronization only becomes 10 times, there is a problem that the processing load is greatly increased and the simulation speed is lowered.

  An object of the present invention is to provide a verification support program, a verification support apparatus, and a verification support method for executing a simulation of a multi-CPU system at high speed and efficiently in order to solve the above-described problems caused by the prior art.

  In order to solve the above-described problems and achieve the object, the verification support program, the verification support apparatus, and the verification support method perform a simulation of an instruction received an execution instruction using a multiprocessor model in which a plurality of processors are realized by software. In the executing computer, processing for sorting the instruction group including information on the processor model to be executed in the multiprocessor model and the execution time in order of execution time, and execution of the instructions that are consecutive in the sorted instruction group It is a requirement to include a process for calculating an execution interval of an instruction group with reference to time and a process for giving an instruction to execute a corresponding instruction to a processor model to be executed for each calculated execution interval.

  According to the verification support program, the verification support apparatus, and the verification support method, when an instruction group of software to be verified that is to be verified in a system in which a plurality of processors perform cooperative operations such as a multi-CPU system is acquired, each instruction is in order of execution time. It is sorted and the execution interval of each instruction is calculated. In the multiprocessor model, the acquired instruction group can be simulated by executing processing corresponding only to the calculated execution interval.

  According to the verification support program, the verification support apparatus, and the verification support method, there is an effect that the simulation of the multi-CPU system can be executed at high speed and efficiently.

It is explanatory drawing which shows the outline | summary of the verification assistance process concerning this Embodiment. It is explanatory drawing which shows the structure of the simulator of the multi CPU system concerning this Embodiment. It is a block diagram which shows the hardware constitutions of a verification assistance apparatus. It is a block diagram which shows the functional structure of a verification assistance apparatus. 6 is an explanatory diagram illustrating an operation of the verification support apparatus according to Embodiment 1. FIG. FIG. 6 is an explanatory diagram illustrating an operation at the time of data transmission in the verification support apparatus according to the first embodiment. It is explanatory drawing which shows the structure of each data used by a verification assistance apparatus. 3 is a flowchart showing a processing procedure of a multi-CPU scheduler in the first embodiment. 3 is a flowchart illustrating a processing procedure of a CPU model in the first embodiment. 10 is an explanatory diagram illustrating an operation of a verification support apparatus according to Embodiment 2. FIG. FIG. 10 is an explanatory diagram illustrating an operation at the time of data transmission in the verification support apparatus according to the second embodiment. 10 is a flowchart illustrating a processing procedure of a multi-CPU model according to the second embodiment. It is a block diagram which shows the structure of the conventional multi CPU simulator. It is explanatory drawing which shows operation | movement of the conventional multi CPU simulator. It is a block diagram which shows the structure of the multi CPU simulator which connected between CPU by the network circuit. It is explanatory drawing which shows operation | movement of the multi CPU simulator which connected between CPUs by the network circuit. It is explanatory drawing which shows operation | movement of the multi CPU simulator which connected between CPUs by the high-speed network circuit.

  Exemplary embodiments of a verification support program, a verification support apparatus, and a verification support method will be described below in detail with reference to the accompanying drawings. In the verification support program, the verification support apparatus, and the verification support method, the instruction group to be executed by the multi-CPU system is sorted in order of time, the execution interval of the instruction group is calculated, and the execution instruction of the corresponding instruction is given for each execution interval The instruction group can be simulated with the minimum necessary processing.

(Overview of verification support processing)
First, an overview of verification support processing according to the present embodiment will be described. FIG. 1 is an explanatory diagram showing an overview of verification support processing according to the present embodiment. As shown in FIG. 1, the verification support apparatus 100 can obtain a simulation result 102 by executing a simulation of the verification target software 101 using the multi-CPU simulator 110.

  The multi-CPU simulator 110 is a functional unit that realizes the operation of the multi-CPU system by software, and includes a multi-CPU scheduler 200 and a multi-CPU model 210. The multi-CPU scheduler 200 sorts the instruction groups constituting the verification target software 101 acquired by the verification support apparatus 100 in the order of execution time, and gives an execution instruction for the corresponding instruction to the multi-CPU model 210 in the order of execution time.

  The multi-CPU model 210 is configured by CPU models 1 to N in which the operations of a plurality of CPUs that operate cooperatively when the verification target software 101 is processed are realized by software. Therefore, when the multi-CPU model 210 receives an instruction execution instruction from the multi-CPU scheduler 200, the multi-CPU model 210 executes processing using the corresponding CPU model. The execution result of the verification target software 101 by the multi-CPU model 210 is output as the simulation result 102.

  As described above, in the verification support processing according to the present embodiment, the multi-CPU scheduler 200 acquires the time at which each CPU model performs processing, and gives an execution instruction to the CPU corresponding to the acquired time. The simulation of the verification target software 101 can be realized. Further, since it is only necessary to transmit an execution instruction at an execution time according to the instruction, a normal transaction is possible regardless of the transmission speed between CPUs. Hereinafter, a specific configuration for realizing the verification support processing according to the present embodiment as described above will be described with reference to two examples of the first and second embodiments.

(Configuration of multi-CPU simulator)
First, the configuration of the multi-CPU simulator 110 that performs the simulation of the verification target software 101 in common with the first and second embodiments will be described. FIG. 2 is an explanatory diagram showing the configuration of the multi-CPU simulator according to the present embodiment. As shown in FIG. 2, the multi-CPU simulator 120 includes a multi-CPU scheduler 200 and a multi-CPU model 210 including CPU models 1 and 2. Also, in each CPU model, there is a scheduler in the CPU for controlling the operation timing in the CPU model, a hardware model corresponding to the actual hardware inside the CPU, and a software model corresponding to the software executed by these hardware And are prepared.

(Hardware configuration of verification support device)
Next, a specific hardware configuration of the verification support apparatus 100 will be described. FIG. 3 is a block diagram of a hardware configuration of the verification support apparatus according to the embodiment. The configuration of the verification support apparatus 100 is also common to the first and second embodiments, and the general-purpose information processing apparatus as illustrated in FIG. 3 is caused to execute the verification support program that realizes the verification support process according to the present embodiment. Thus, the function as the verification support apparatus 100 can be realized.

  In FIG. 3, a verification support apparatus 100 includes a CPU (Central Processing Unit) 301, a ROM (Read-Only Memory) 302, a RAM (Random Access Memory) 303, a magnetic disk drive 304, a magnetic disk 305, and a communication. An I / F (Interface) 306, an input device 307, and an output device 308 are provided. Each component is connected by a bus 310.

  Here, the CPU 301 governs overall control of the verification support apparatus 100. The ROM 302 stores various programs such as a boot program and a verification support program for realizing the verification support processing according to the present embodiment. The RAM 303 is used as a work area for the CPU 301. The magnetic disk drive 304 controls data update / reference with respect to the magnetic disk 305 according to the control of the CPU 301. The magnetic disk 305 stores data written under the control of the magnetic disk drive 304. In the hardware configuration of FIG. 3, the recording support example of the verification support apparatus 100, that is, the magnetic disk 305 is used. However, other recording media such as an optical disk and a flash memory may be used.

  The communication I / F 306 is connected to a network (NET) 309 such as a LAN (Local Area Network), a WAN (Wide Area Network), and the Internet through a communication line, and the other verification support apparatus 100 and other devices are connected via the network 309. Connected to an external device. The communication I / F 306 controls an internal interface with the network 309 and controls input / output of data from an external device. As a configuration example of the communication I / F 306, for example, a modem or a LAN adapter may be employed.

  The input device 307 receives input from the outside to the verification support apparatus 100. Specific examples of the input device 307 include a keyboard and a mouse. As illustrated in FIG. 1, the verification target software 101 to be simulated by the verification support apparatus 100 may be stored in advance in a storage area such as the ROM 302, the RAM 303, or the magnetic disk 305, but input from the input device 307. And may be stored in the storage area described above.

  In the case of a keyboard, for example, keys for inputting characters, numbers, various instructions, and the like are provided to input data. Moreover, a touch panel type input pad or a numeric keypad may be used. In the case of a mouse, for example, the cursor is moved, a range is selected, or a window is moved or the size is changed. Further, a trackball or a joystick may be used as long as they have the same function as a pointing device.

  The output device 308 outputs various data stored in the verification support apparatus 100, the simulation result 102, and the like. Specific examples of the output device 308 include a display and a printer.

  In the case of a display, for example, data such as a cursor, an icon or a tool box, a document, an image, and function information is displayed. Further, a CRT, a TFT liquid crystal display, a plasma display, or the like can be employed as this display. In the case of a printer, for example, image data and document data are printed. Further, a laser printer or an ink jet printer can be employed.

(Functional configuration of verification support device)
Next, a functional configuration of the verification support apparatus 100 according to the present embodiment will be described. FIG. 4 is a block diagram illustrating a functional configuration of the verification support apparatus. Here, a functional configuration for realizing the operation as the multi-CPU scheduler 200 and the multi-CPU model 210 as described with reference to FIG. 1 will be described. Note that the operation of the multi-CPU model 210 uses the function of the conventional multi-CPU model, and therefore only the unique configuration for realizing the verification support processing according to the present embodiment will be described.

  As illustrated in FIG. 4, the verification support apparatus 100 includes a sorting unit 401, a calculation unit 402, a control unit 403, a determination unit 404, a notification unit 405, and an extraction unit 406. Specifically, the functions (sorting unit 401 to extracting unit 406) for realizing the multi-CPU scheduler 200 and the multi-CPU model 210 are stored in a storage area such as the ROM 302, the RAM 303, and the magnetic disk 305 shown in FIG. The function is realized by causing the CPU 301 to execute the stored verification support program or by the communication I / F 306.

  When the sorting unit 401 acquires the verification target software 101 to be executed by the multi-CPU model 210, the sorting unit 401 has a function of sorting the instruction group in the verification target software 101 in order of execution time. Each instruction in the verification target software 101 includes information on the CPU model (for example, CPU model 1) to be executed in the multi-CPU model 210 and the execution time. Therefore, the sorting unit 401 refers to the execution time of each instruction and sorts the instruction group in the order of the instruction with the earlier execution time to the instruction with the later execution time.

  Note that each instruction has various information regarding the execution time, such as when an absolute time is set based on the clock of the verification support apparatus 100 or when a relative time is set based on the first instruction. However, in any case, the operation is performed in synchronization with the time of the multi-CPU scheduler 200. The sorted instruction group is stored in a storage area such as the RAM 303 and the magnetic disk 305.

  The calculation unit 402 has a function of calculating the execution interval of the instruction group with reference to the execution times of the consecutive instructions of the instruction group sorted by the sorting unit 401. Consecutive instructions refer to adjacent instructions at the execution time. Specifically, if the instructions 1 to 3 illustrated in FIG. 1 are used, the instructions 1 and 2 and the instructions 2 and 3 are consecutive instructions. Then, the calculation unit 402 calculates the interval at which the instructions are executed by obtaining the difference between the execution times of these consecutive instructions. The calculated execution interval is stored in a storage area such as the RAM 303 and the magnetic disk 305.

  For each execution interval calculated by the calculation unit 402, the control unit 403 gives an instruction to execute the corresponding instruction to the CPU model to be executed. For example, in the case of a process in which the instruction 1 is executed by the CPU model 1 at a timing of 0.22 [ms] and the instruction 2 is executed by the CPU model 2 at a timing of 0.5 [ms], each timing is set. An execution instruction is given to the CPU model to be executed in the multi-CPU model 210. The execution instruction output from the control unit 403 is stored in a storage area such as the RAM 303 and the magnetic disk 305.

  As described above, the instruction group of the verification target software 101 can be simulated by the sorting unit 401, the calculation unit 402, and the control unit 403. However, each command further includes the same command depending on the execution content and the execution result. The next execution is determined. Therefore, the multi-CPU model 210 is provided with a function unit (determination unit 404) that determines the next execution schedule of the executed instruction.

  The determination unit 404 determines whether or not an instruction executed by the multi-CPU model 210 has a next execution schedule. When the determination unit 404 determines that there is a next execution schedule, an instruction group including instructions to be executed next time is added to the sorting unit 401. The sort unit 401 sorts each instruction including the newly added instruction again in the order of execution time.

  Further, the command executed by the multi-CPU model 210 includes a process for transmitting data to other CPU models. The multi-CPU model 210 is provided with a function unit (notification unit 405) for notifying another CPU model as a data transmission destination when an instruction for performing such data transmission is executed.

  When the instruction executed by the multi-CPU model 210 includes a request for transmitting arbitrary data to another processor model, the notification unit 405 notifies the sorting unit 401 of an instruction corresponding to the transmission request. When the instruction including the transmission request is notified from the notification unit 405, the sorting unit 401 sorts the instruction group including the instruction corresponding to the transmission request in the order of execution time. Further, when an instruction that gives an execution instruction at a certain execution interval is an instruction corresponding to the above-described transmission request, the control unit 403 sends the corresponding data together with the execution instruction of the instruction to another CPU model as a transmission destination. give.

  By using the functional units 401 to 405 described above, the multi-CPU scheduler 200 only needs to give an execution instruction to the multi-CPU model 210 only at the scheduled execution time of the instruction group included in the verification target software 101. . Therefore, the verification target software 101 can be simulated with the minimum necessary processing. In addition, a normal transaction can be realized at the correct timing regardless of the transmission speed in the multi-CPU system.

  In addition to the method for obtaining the instruction execution interval as described above, the verification support apparatus 100 uses the extraction unit 406 to set the timing for each unit time as a reference time and set this reference time as a trigger, and the multi-CPU model A method of actually operating the multi-CPU scheduler 200 can be used only at an execution time including a timing at which an execution instruction to 210 is transmitted.

  The extraction unit 406 uses a time for each unit time as a reference time from an arbitrary time, and includes the execution time of any instruction sorted by the sorting unit 401 within the unit time from the reference time To extract. That is, the time starting from 0 and adding 250 [μs] as a unit time is set as the reference time. Therefore, 0, 250, 500, 750, 1000,... [Μs] are the reference times. An arbitrary interval can be set for this unit time.

  Then, the extraction unit 406 extracts a reference time in which the execution time of each instruction is included in less than 250 [μs] from the reference time in the order sorted by the sorting unit 401. For example, when instruction 1 (execution time: 250 [μs]), instruction 2 (execution time: 770 [μs]) and the instruction group are sorted, 250 and 750 [μs] are extracted as the reference time.

  When the extraction unit 406 extracts the reference time including the instruction execution time, the control unit 403 gives an instruction execution instruction to the CPU model corresponding to each reference time. As described above, the instruction execution time may not match the reference time. Therefore, the control unit 403 transmits the difference from the reference time to the execution time as a standby time together with the execution instruction to the CPU model.

  In the CPU model, when an execution instruction is received, the CPU model waits for a waiting time and then executes a process according to the execution instruction. In the case of the instruction 1 described above, since the difference between the reference time (250 [μs]) and the execution time (250 [μs]) is 0 [μs], the corresponding CPU model is 0 [μs] after the reference time. That is, the process according to the command is executed without waiting. In the case of the instruction 2, since the difference between the reference time (750 [μs]) and the execution time (770 [μs]) is 20 [μs], the CPU in question corresponds to the instruction after waiting for 20 [μs]. Perform the appropriate process.

  As described above, when the extraction unit 406 is used, the multi-CPU scheduler 200 of the verification support apparatus 100 transmits an execution instruction to the target CPU model 210 only when there is a process to be executed for each unit time. Good. Further, even when a process such as data transmission between CPU models is executed depending on the CPU model, a process for notifying the multi-CPU scheduler 200 of the time when the transmission process is completed can be performed normally. Transactions can be realized.

  In the following, specific processing when an execution instruction is given at the timing calculated by the calculation unit 402 will be described as Embodiment 1, and specific processing when an execution instruction is given at the reference time extracted by the extraction unit 406 will be described. Each will be described as a second embodiment.

(Embodiment 1)
FIG. 5 is an explanatory diagram illustrating the operation of the verification support apparatus according to the first embodiment. In the first embodiment, the execution instruction from the multi-CPU scheduler 200 to the corresponding CPU model (CPU models 1 and 2) in the multi-CPU model 210 is issued only at the timing when the process is scheduled by the instruction of the verification target software 101. Sent.

  FIG. 5 illustrates a process in which the multi-CPU scheduler 200 transmits an instruction execution instruction to each CPU model at the timing of 270, 400, 510 [μs] (250, 500 [μs] in FIG. 5 represents Memory that shows the timing standard). Since the instructions 1 and 2 are transmitted to the CPU model 1 at the timings 270 and 400 [μs], the CPU model 1 executes processing according to the instructions 1 and 2. At timing 510 [μs], since instruction 3 is transmitted to the CPU model 2, the CPU model 2 executes processing according to the instruction 3. In addition, the execution result of the instruction in each CPU model is transmitted to the multi-CPU scheduler 200 as a return value (details will be described later).

  In the multi-CPU scheduler 200, when all the processing obtained as the execution time of the instruction group of the verification target software 101 is completed, if the return value transmitted from each CPU model includes an instruction to be executed next time, The process proceeds until the scheduled execution time of this instruction, and an execution instruction is transmitted to the target CPU model. The multi-CPU scheduler 200 repeats the above processing until there is no instruction execution schedule.

  FIG. 6 is an explanatory diagram showing an operation at the time of data transmission in the verification support apparatus of the first embodiment. In FIG. 6, a process when there is data transmission between CPU models will be described. Command 1 in FIG. 6 is processing for transmitting data from the CPU model 1 to the CPU model 2. In this case, when the instruction 1 is executed by the CPU model 1, the “transmission request” for data to the CPU 2 and the “next time” for executing this instruction are transmitted as return values to the multi-CPU scheduler 200.

  The instruction 2 is an instruction for executing a transmission request transmitted from the CPU model 1. Therefore, the multi-CPU scheduler 200 advances the process to “next time” transmitted from the CPU model 1 and transmits data to the CPU model 2 in response to the “transmission request”. When receiving the return value of the execution result of the instruction 2 by the CPU model 2, the multi-CPU scheduler 200 causes the next instruction 3 to be executed based on the return value. In the CPU model 1, processing corresponding to the instruction 3 is executed, and the execution result is transmitted to the multi-CPU scheduler 200. The multi CPU scheduler 200 accepts the execution result and proceeds to the next instruction 4.

<Data structure>
Next, data handled in the process described with reference to FIGS. 5 and 6 will be described in more detail. The configuration of data used when the verification target software 101 is simulated by the verification support apparatus 100 will be described. FIG. 7 is an explanatory diagram illustrating a configuration of data used by the simulator by the verification support apparatus. As shown in FIG. 7, the verification support apparatus 100 uses three types of data groups 710 to 730 representing the execution parameter A, the return value B, and the scheduler management data C. Each data has the following structure.

・ Execution parameter A
This is a data group to be transmitted to the CPU model when an execution instruction is given to the CPU model, [execution time, length of received data (“0” when there is no received data), received data (only when there is)] It is comprised by three types of data.

・ Return value B
This is a data group that is returned to the multi-CPU scheduler 200 after an instruction is executed by the CPU model. [Scheduled execution time (only when there is a scheduled execution), presence / absence of scheduled execution, transmission data length list (transmitted data) If there is no data, “0”), the transmission data list and the destination CPU number list] are included.

・ Scheduler management data C
In the multi-CPU scheduler 200, it is a data group used for managing the execution order of each CPU model, [CPU number (identifier of CPU to be processed), scheduled execution time, received data length (received data is If there is no data, the received data is “0”) and received data].

<Processing procedure of multi-CPU scheduler>
Next, the processing procedure of the multi-CPU scheduler 200 when simulating the verification target software 101 using each data described above will be described. FIG. 8 is a flowchart showing a processing procedure of the multi-CPU scheduler in the first embodiment. In the flowchart of FIG. 8, first, scheduler management data C of each CPU model is acquired and stored in the execution list (step S801).

Next, the execution parameter A is created from the scheduler management data C (step S802). In step S802, an execution parameter A that matches the following conditions is created from the scheduler management data C stored as an execution list.
-Scheduler management data C at the top of the execution list
Scheduler management data whose CPU number and scheduled execution time coincide with the first scheduler management data C in the execution list

In step S802, each data of the execution parameter A is created using information of the scheduler management data C as described below.
Execution parameter A
-Execution time ← Scheduled execution time of scheduler management data C-Length of received data ← Length of received data for scheduler management data C-Received data ← Received data for scheduler management data C

  When the execution parameter A is created in step S802, the scheduler management data C for which the execution parameter A has been created is deleted from the execution list (step S803). Thereafter, the processing of the target CPU model in the multi-CPU model 210 is executed with reference to the execution parameter A (step S804).

  When the target CPU model executes the process according to the execution parameter in step S804, the return value B corresponding to the execution result of the target CPU model is collected (step S805). Then, with reference to the collected return value B, it is determined whether or not the next and subsequent instructions are scheduled to be executed (step S806). If it is determined that there is an execution schedule (step S806: Yes), scheduler management data C corresponding to the execution schedule is created and stored in the execution list (step S807).

In step S807, if there is an execution schedule, scheduler management data C is generated as follows.
Scheduler management data C
-CPU number ← CPU number of the CPU model that executed the process immediately before-Scheduled execution time ← Scheduled next execution time of return value B-Length of received data ← None-Received data ← None

  After the process of step S807 is completed, or when it is determined in step S806 that there is no execution schedule (step S806: No), it is next determined whether or not there is data to be transmitted to another CPU model. (Step S808). If it is determined that there is transmission data (step S808: Yes), scheduler management data C corresponding to the transmission content is created and stored in the execution list (step S809).

In step S809, the following processing is repeated until the number of elements in the transmission data list of the return value B collected in step S805 becomes zero.
1. Create scheduler management data C CPU number: Top element of destination CPU number list of return value B Scheduled execution time: Execution time immediately before execution + length of transmission data of return value B x delay coefficient Length of received data: 2. The first element of the length of the transmission data of the return value B. Reception data: the first element of the transmission data list of the return value B. The scheduler management data C created by 2.1 is stored in the execution list. After the storage, the top elements of the return value B destination CPU number list, transmission data length list, and transmission data list are removed.

  After the process of step S809 is completed, or when it is determined that there is no transmission data (step S808: No), the execution list is sorted by the scheduled execution time of the scheduler management data C (step S810). Thereafter, it is determined whether or not the execution list is 0 (step S811).

  If it is determined in step S811 that the execution list has become 0 (step S811: Yes), the series of processing ends. If scheduler management data C remains in the execution list (step S811: No), the process returns to step S802, and all instructions are simulated.

<Processing procedure of multi-CPU model>
Next, the processing procedure of the multi CPU model 210 will be described. FIG. 9 is a flowchart illustrating the processing procedure of the CPU model according to the first embodiment. The processing of the multi-CPU model 210 described below is triggered by reception of an execution instruction transmitted from the multi-CPU scheduler 200. In the flowchart of FIG. 9, first, the execution time of the execution parameter A is set to the time of the simulator in the multi-CPU model 210 (step S901).

  Next, it is determined whether or not the data in the list storing the execution parameter A is 0 (step S902). If it is determined in step S902 that the number of data in the list in which the execution parameter A is stored is 0 (step S902: Yes), the simulation is executed at the designated time (step S906). On the other hand, when it is determined that the data of the execution parameter A remains in the list (step S902: No), it is determined whether there is reception data in the first execution parameter A (step S903).

  If it is determined in step S903 that there is received data (step S903: Yes), the received data event is notified to the target CPU model (step S904), and the notified execution parameter A is deleted from the list (step S904). Step S905), the process returns to step S902 again. On the other hand, if it is determined that there is no reception data in the first execution parameter A (step S903: No), the simulation is executed as it is at the designated time (step S906).

  After the simulation is executed in step S906, it is determined whether there is a next execution model (step S907). If it is determined that there is a next execution model (step S907: Yes), the next execution schedule of the scheduler management data C is set to be present (step S908), and the execution schedule time of the execution model with the earliest next execution schedule is returned. The value B is stored (step S909). On the other hand, if it is determined that there is no next execution model (step S907: No), the next execution schedule of the scheduler management data C is set to none (step S910).

  When the next execution schedule of the scheduler management data C is set in steps S908 and S910, it is next determined whether there is transmission data from the CPU model being processed to another CPU model (step S911). If it is determined that there is transmission data (step S911: Yes), information (transmission destination CPU number, data length, transmission data) regarding the transmission data is stored in the return value B (step S912), and a series of Terminate the process. If it is determined that there is no transmission data (step S911: No), the process of step S912 is skipped and the series of processes ends.

  As described above, in the first embodiment, the execution instruction can be transmitted only at the scheduled execution time of the instruction group included in the verification target software 101. Therefore, the multi-CPU model 210 may be operated only at the timing of executing the instruction, and the verification target software 101 can be simulated with the minimum necessary processing. Even if the actual transmission speed in the multi-CPU system is high, normal transactions can be realized at the correct timing.

(Embodiment 2)
FIG. 10 is an explanatory diagram illustrating the operation of the verification support apparatus according to the second embodiment. In the second embodiment, only when there is an instruction to be executed at the reference time for each unit time, an execution instruction is transmitted from the multi-CPU scheduler 200 and the corresponding processing is executed by the multi-CPU model 210.

  The multi-CPU scheduler 200 sets the reference time every time it adds 0 as an initial value and 25 [μs] as a unit time (see the scale on the right side of the timing in FIG. 10). FIG. 10 illustrates a process in which the multi-CPU scheduler 200 transmits an instruction execution instruction to the CPU model corresponding to the timings of 270, 302, 400, and 510 [μs].

  Therefore, the instructions 1 and 3 are transmitted to the CPU model 1 in unit time of timing 250 and 400 [μs], respectively. In the CPU model 1, since processing corresponding to the instructions 1 and 3 is executed at 270,400 [μs], after the unit time (250,400 [μs]), the system waits for the difference time and responds to the instruction. Execute the process. In addition, the instructions 2 and 4 are transmitted to the CPU model 2 at unit times of timing 300 and 500 [μs], respectively. In the CPU model 2, processing corresponding to the instructions 2 and 4 is executed in 302, 510 [μs], and therefore, after the unit time (300, 500 [μs]), the CPU 2 waits for the difference time and then the instructions 2 and 4 The process according to is executed. In addition, the execution result of the instruction in each CPU model is transmitted to the multi-CPU scheduler 200 as a return value (details will be described later).

  Further, in the multi-CPU scheduler 200, when all the processing obtained as the execution time of the instruction group of the verification target software 101 is completed, an instruction to be executed next time is included in the return value transmitted from each CPU model. Advances the process until the scheduled execution time of this instruction, and transmits an execution instruction to the target CPU model. The multi-CPU scheduler 200 repeats the above processing until there is no instruction execution schedule.

  In the case of the second embodiment, the multi-CPU scheduler 200 accepts an execution instruction in the unit time including the time for sending the instruction execution instruction and receiving the return value in the unit time, and the multi-CPU model 210 accepts the execution instruction. The CPU (the CPU 301 of the verification support apparatus 100) is executed only in the unit time including the time for executing the process according to the instruction, that is, in the shaded portion in FIG. Since the process is skipped at other times, efficient simulation is possible.

  FIG. 11 is an explanatory diagram showing an operation at the time of data transmission in the verification support apparatus of the second embodiment. In FIG. 11, a process when there is data transmission between CPU models will be described. An instruction 1 in FIG. 11 is a process for transmitting data from the CPU model 1 to the CPU model 2. In this case, when the instruction 1 is executed by the CPU model 1, a “transmission request” for data to the CPU model 2 and “next time” for executing this instruction are transmitted as return values to the multi-CPU scheduler 200. .

  The instruction 2 is an instruction for executing a transmission request transmitted from the CPU model 1. Therefore, in the CPU model 2, when data from the multi-CPU scheduler 200 is received, after executing the model A, the CPU model 2 waits until the timing 302 [μs], so that the received event is notified at the original event reception time. Execute an event including

<Processing procedure of multi-CPU scheduler>
Next, a processing procedure of the multi-CPU scheduler 200 when simulating the verification target software 101 will be described. In the case of the second embodiment, each data described in FIG. 7 is used as in the first embodiment. Further, the processing itself of the multi-CPU scheduler 200 is the same as the processing procedure of the first embodiment described with reference to FIG. Among these processes, when transmitting an execution parameter, difference information between the execution time and the reference time is provided as a standby time. In the multi-CPU model 210, processing can be delayed based on this difference information.

<Processing procedure of multi-CPU model>
Next, the processing procedure of the multi CPU model 210 will be described. FIG. 12 is a flowchart showing the processing procedure of the multi-CPU model in the second embodiment. The processing of the multi-CPU model 210 described below is triggered by reception of an execution instruction transmitted from the multi-CPU scheduler 200. In the flowchart of FIG. 12, first, the execution time of the execution parameter A is set to the time of the simulator in the multi-CPU model 210 (step S1201).

  Next, it is determined whether or not the data in the list storing the execution parameter A is 0 (step S1202). If it is determined in this step S1202 that the number of data in the list in which the execution parameter A is stored is 0 (step S1202: Yes), the unit time (in the case of FIG. 11, 25 [ The simulation is executed up to the break of [mu] s]) (step S1206). A difference between the process of step S1206 and the process of later-described step S1204 of the multi-CPU model 210 according to the first embodiment. On the other hand, when it is determined that the data of the execution parameter A remains in the list (step S1202: No), it is determined whether there is reception data in the first execution parameter A (step S1203).

  If it is determined in step S1203 that there is received data (step S1203: Yes), the received data event is notified of a delay to the target CPU model (event notification including delay information) (step S1204). After deleting the execution parameter A from the list (step S1205), the process returns to the process of step S1202. On the other hand, when it is determined that there is no received data in the first execution parameter A (step S1203: No), the simulation is executed as it is at the designated time (step S1206).

  After the simulation is executed in step S1206, it is determined whether there is a next execution model (step S1207). If it is determined that there is a next execution model (step S1207: Yes), the next execution schedule of the scheduler management data C is set to be present (step S1208), and the execution schedule time of the execution model with the earliest next execution schedule is returned. Stored in the value B (step S1209). On the other hand, if it is determined that there is no next execution model (step S1207: No), the next execution schedule of the scheduler management data C is set to none (step S1210).

  When the next execution schedule of the scheduler management data C is set in steps S1208 and S1210, it is next determined whether or not there is transmission data from the CPU model being processed to another CPU model (step S1211). If it is determined that there is transmission data (step S1211: Yes), information about the transmission data (destination CPU number, data length, transmission data) is stored in the return value B (step S1212). Terminate the process. If it is determined that there is no transmission data (step S1211: No), the process of step S1212 is skipped, and the series of processes ends.

  As described above, according to the second embodiment, an execution instruction may be transmitted to the target multi-CPU model 210 only when there is a process to be executed every unit time. Even when processing such as data transmission between CPUs is executed depending on the CPU model, a normal transaction can be executed by adding processing for notifying the multi-CPU scheduler 200 of the time when transmission processing is completed. Can be realized.

  As described above, according to the present embodiment, when the instruction group of the verification target software 101 is acquired, the instructions are sorted in order of execution time, and the execution interval of each instruction is calculated. In the multi-CPU model 210, the acquired instruction group can be simulated by executing processing corresponding only to the calculated execution interval. Therefore, the simulation of the multi CPU system can be executed at high speed and efficiently.

  Further, as described with reference to FIG. 17, the conventional multi-CPU simulator 1500 has a problem that the simulation speed decreases in inverse proportion to the increase in the transmission speed between CPUs. On the other hand, in this embodiment, it is possible to realize a simulation of processing including data transmission between CPU models regardless of the transmission speed between CPU models. That is, there is also an effect that the collaborative operation can be verified when desired software is executed for an arbitrary multi-CPU system.

  Note that the verification support method described in this embodiment can be realized by executing a program prepared in advance on a computer such as a personal computer or a workstation. This program is recorded on a computer-readable recording medium such as a hard disk, a flexible disk, a CD-ROM, an MO, and a DVD, and is executed by being read from the recording medium by the computer. Further, this program may be a medium that can be distributed via a network such as the Internet.

  In addition, the verification support apparatus 100 described in the present embodiment is a specific application IC (hereinafter simply referred to as “ASIC”) such as a standard cell or a structured ASIC (Application Specific Integrated Circuit), or a PLD (Programmable) such as an FPGA. It can also be realized by Logic Device). Specifically, for example, the function (sorting unit 401 to extracting unit 406) of the above-described verification support apparatus 100 is defined by HDL description, and the HDL description is logically synthesized and given to the ASIC or PLD to provide verification support. The device 100 can be manufactured.

  The following additional notes are disclosed with respect to the embodiment described above.

(Supplementary note 1) A computer that simulates an instruction received an execution instruction using a multiprocessor model in which a plurality of processors is realized by software.
Sorting means for sorting an instruction group including information on a processor model to be executed and execution time in the multiprocessor model in order of execution time;
A calculation unit that calculates an execution interval of the instruction group with reference to an execution time of each successive instruction of the instruction group sorted by the sorting unit;
Control means for giving an instruction to execute a corresponding instruction to a processor model to be executed for each execution interval calculated by the calculating means;
Verification support program characterized by functioning as

(Supplementary note 2)
Functioning as a determination means for determining whether or not an instruction executed by the computer is scheduled to be executed next time,
The verification support according to appendix 1, wherein the sorting means sorts a group of instructions including the instruction scheduled to be executed next time in order of execution time when it is determined by the determining means that the next execution is scheduled. program.

(Supplementary note 3)
When the instruction executed by the computer includes a request to transmit arbitrary data to another processor model, the instruction corresponding to the transmission request is made to function as a notification unit that notifies the sorting unit,
The sorting means sorts the instruction group including the instructions corresponding to the transmission request notified by the notifying means in order of execution time,
The control means, when an instruction corresponding to the execution interval is an instruction corresponding to the transmission request, gives the arbitrary data to the other processor model together with an instruction to execute the instruction. The verification support program described in 1.

(Supplementary Note 4) A computer that simulates an instruction received an execution instruction using a multiprocessor model in which a plurality of processors is realized by software.
Sorting means for sorting an instruction group including information on a processor model to be executed and execution time in the multiprocessor model in order of execution time;
A reference time such that the execution time of any instruction sorted by the sorting means is included in the unit time from each reference time is set as the reference time from any time to the unit time. Extraction means for extracting from the reference time,
Control means for giving an execution instruction of the corresponding instruction and a waiting time until execution of the execution instruction to the execution target processor model for each reference time extracted by the extraction means,
Verification support program characterized by functioning as

(Supplementary note 5)
Functioning as a determination means for determining whether or not there is a next execution schedule of the instruction executed by the computer,
5. The verification support according to appendix 4, wherein the sorting means sorts a group of instructions including instructions to be executed next time in order of execution time when it is determined by the determining means that the next execution is scheduled. program.

(Supplementary note 6)
When the instruction executed by the computer includes a request to transmit arbitrary data to another processor model, the instruction corresponding to the transmission request is made to function as a notification unit that notifies the sorting unit,
The sorting means sorts the instruction group including the instructions corresponding to the transmission request notified by the notifying means in order of execution time,
The control means, for each reference time extracted by the extraction means, when the corresponding instruction is an instruction corresponding to the transmission instruction, gives the arbitrary data together with an instruction to execute the instruction to the other processor model. The verification support program according to appendix 5, characterized by:

(Supplementary note 7) A verification support apparatus for simulating an instruction received an execution instruction using a multiprocessor model in which a plurality of processors are realized by software,
Sorting means for sorting an instruction group including information on a processor model to be executed and execution time in the multiprocessor model in order of execution time;
A calculation unit that calculates an execution interval of the instruction group with reference to an execution time of each successive instruction of the instruction group sorted by the sorting unit;
Control means for giving an instruction to execute a corresponding instruction to a processor model to be executed for each execution interval calculated by the calculating means;
A verification support apparatus comprising:

(Supplementary note 8) A verification support apparatus for simulating an instruction received an execution instruction using a multiprocessor model in which a plurality of processors are realized by software,
Sorting means for sorting an instruction group including information on a processor model to be executed and execution time in the multiprocessor model in order of execution time;
A reference time such that the execution time of any instruction sorted by the sorting means is included in the unit time from each reference time is set as the reference time from any time to the unit time. Extraction means for extracting from the reference time;
For each reference time extracted by the extraction means, a control means for giving an execution instruction of the corresponding instruction and a waiting time until execution of the execution instruction to the processor model to be executed,
A verification support apparatus comprising:

(Additional remark 9) The computer which simulates the instruction | indication which received the execution instruction using the multiprocessor model which implement | achieved several processors by software,
A sorting step of sorting the instruction group including information on a processor model to be executed and execution time in the multiprocessor model in order of execution time;
A calculation step of calculating an execution interval of the instruction group with reference to an execution time of each successive instruction of the instruction group sorted by the sorting step;
An instruction step for giving an instruction to execute a corresponding instruction to a processor model to be executed for each execution interval calculated by the calculation step;
The verification support method characterized by performing this.

(Additional remark 10) The computer which simulates the instruction which received the execution instruction using the multiprocessor model which realized a plurality of processors by software,
A sorting step of sorting the instruction group including information on a processor model to be executed and execution time in the multiprocessor model in order of execution time;
With each unit time as a reference time from an arbitrary time, each reference time such that the execution time of any instruction sorted by the sorting step is included in the unit time from each reference time An extraction process for extracting from the reference time;
For each reference time extracted by the extraction step, an instruction step for giving an instruction to execute the corresponding instruction and a waiting time until execution of the execution instruction to the processor model to be executed;
The verification support method characterized by performing this.

DESCRIPTION OF SYMBOLS 100 Verification support apparatus 101 Verification object software 102 Simulation result 110 Multi CPU simulator 200 Multi CPU scheduler 210 Multi CPU model 401 Sort part 402 Calculation part 403 Control part 404 Judgment part 405 Notification part 406 Extraction part

Claims (5)

A computer that simulates instructions that have received instructions for execution using a multiprocessor model in which multiple processors are implemented by software.
Sorting means for sorting an instruction group including information on a processor model to be executed and execution time in the multiprocessor model in order of execution time;
A calculation unit that calculates an execution interval of the instruction group with reference to an execution time of each successive instruction of the instruction group sorted by the sorting unit;
Control means for giving an instruction to execute a corresponding instruction to a processor model to be executed for each execution interval calculated by the calculating means;
Verification support program characterized by functioning as A computer that simulates instructions that have received instructions for execution using a multiprocessor model in which multiple processors are implemented by software.
Sorting means for sorting an instruction group including information on a processor model to be executed and execution time in the multiprocessor model in order of execution time;
A reference time such that the execution time of any instruction sorted by the sorting means is included in the unit time from each reference time is set as the reference time from any time to the unit time. Extraction means for extracting from the reference time,
Control means for giving an execution instruction of the corresponding instruction and a waiting time until execution of the execution instruction to the execution target processor model for each reference time extracted by the extraction means,
Verification support program characterized by functioning as A verification support apparatus that simulates an instruction received an execution instruction using a multiprocessor model in which a plurality of processors is realized by software,
Sorting means for sorting an instruction group including information on a processor model to be executed and execution time in the multiprocessor model in order of execution time;
A calculation unit that calculates an execution interval of the instruction group with reference to an execution time of each successive instruction of the instruction group sorted by the sorting unit;
Control means for giving an instruction to execute a corresponding instruction to a processor model to be executed for each execution interval calculated by the calculating means;
A verification support apparatus comprising: A verification support apparatus that simulates an instruction received an execution instruction using a multiprocessor model in which a plurality of processors is realized by software,
Sorting means for sorting an instruction group including information on a processor model to be executed and execution time in the multiprocessor model in order of execution time;
A reference time such that the execution time of any instruction sorted by the sorting means is included in the unit time from each reference time is set as the reference time from any time to the unit time. Extraction means for extracting from the reference time;
For each reference time extracted by the extraction means, a control means for giving an execution instruction of the corresponding instruction and a waiting time until execution of the execution instruction to the processor model to be executed,
A verification support apparatus comprising: A computer that simulates an instruction received an execution instruction using a multiprocessor model in which a plurality of processors is realized by software.
A sorting step of sorting the instruction group including information on a processor model to be executed and execution time in the multiprocessor model in order of execution time;
A calculation step of calculating an execution interval of the instruction group with reference to an execution time of each successive instruction of the instruction group sorted by the sorting step;
An instruction step for giving an instruction to execute a corresponding instruction to a processor model to be executed for each execution interval calculated by the calculation step;
The verification support method characterized by performing this.

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