JP2010191645A - Address mapping method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an address mapping method which suppresses occurrence frequency of mishit of a TLB (Translation Look aside Buffer) during program execution. <P>SOLUTION: A part of an entry of a TLB mechanism 2 is secured as an exclusive entry 21 of a task text part. A page size is designated to the exclusive entry 21 so that a whole text part of the task (A) is fitted in, and a logical address and a physical address on a main storage 5 are associated and set. Further, an OS manages the TLB mechanism 2 so that the exclusive entry 21 may be locked and may not be changed in order to prevent the exclusive entry 21 from being changed when the TLB mishit occurs. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an address mapping method in TLB for converting a logical address into a physical address.

  In systems related to field control and safety instrumentation in various plants, an MMU (Memory Management Unit) built-in CPU is used as a CPU for executing control calculations, and an OS (Operating System) is an MMU TLB (Translation Look aside Buffer). ) Memory access is executed using the mechanism.

  A logical address and a physical address on the main memory are associated with the TLB. When an application task accesses a logical address provided from the OS, the CPU converts the logical address to a physical address using the TLB mechanism, Reads and writes data by accessing the physical address space on the main memory. At this time, the address translation is performed according to the page size range set in the TLB mechanism. For example, when the page size is set to 4 KB and the logical address is set to 0x1000 in the TLB mechanism, the 4 KB range of the logical address: 0x10000 to 0x1FFF can be converted into the corresponding physical address. In the TLB mechanism, the conversion size, logical address, and physical path address are set as one set, and the number of sets that can be set is determined according to the CPU specifications.

An address conversion procedure when a conversion table is already set in the TLB mechanism is shown below.
(Step # 1) Task accesses the logical address space (Step # 2) Search whether there is a corresponding logical address on the TLB mechanism (Step # 3) Detect that the logical address corresponding to the TLB mechanism is set ( TLB hit)
(Step # 4) The detected logical address is converted by the conversion table, and the physical address space is accessed.

Next, an address conversion procedure when no conversion table is set in the TLB mechanism is shown below.
(Step # 1) Task accesses the logical address space (Step # 2) Search whether there is a logical address corresponding to the TLB mechanism (Step # 3) Detect that the logical address corresponding to the TLB mechanism is not set ( TLB miss hit)

At this time, an exception occurs, the TLB exception handler routine is called, and the following processing is executed.
(Step # 5) The page table area on the main memory is searched and the physical address corresponding to the logical address is detected (Step # 6). The physical address detected from the page table area is set in the TLB mechanism (Step # 7). Address conversion using the set conversion table and access to the physical address space

  Thus, when a TLB miss occurs, processing for changing the setting of the TLB mechanism is executed. This process is originally unnecessary for the CPU, and if TLB misses occur frequently, it adversely affects the execution speed of the process that the CPU should perform, such as control computation.

  The TLB mechanism has an advantage that the frequency of occurrence of TLB misses can be reduced and the performance can be improved by increasing the conversion size, but there is a disadvantage that a wasteful area in the main memory is increased. On the contrary, if the conversion size is reduced, the main memory can be used effectively and the access authority of each area can be set finely. Thus, there is an advantage that the security can be improved, but there is a disadvantage that TLB misses increase.

JP 2004-94906 A

  The text part of the application relating to field control and safety instrumentation has a size of about 4 MB. However, since the conversion size of the TLB mechanism is normally set to 4 KB, the TLB mechanism is set to TLB in a state where the text part is divided in units of 4 KB. In addition, since the text part is not fixedly set to TLB, the area of the text part set in TLB dynamically changes with the occurrence of a miss hit, and access to the text part erased from TLB is performed. Sometimes TLB misses occur. For this reason, the number of times the TLB exception handler routine is called increases, which adversely affects performance.

  An object of the present invention is to provide an address mapping method capable of suppressing the frequency of occurrence of TLB misses during program execution.

The address mapping method according to the present invention is a TLB address mapping method for converting a logical address into a physical address, and providing a TLB logical address with an area that can accommodate the entire text portion of the application task; and execution of the application task And a step of fixedly assigning a physical address of the entire text portion to the area.
According to this address mapping method, when an application task is executed, the physical address of the entire text part of the application task is fixedly assigned to the TLB, so that no TLB miss occurs during logical access to the text part. The frequency of miss hits can be suppressed.

  According to the switching of the application task, there may be provided a step of switching the allocation to the area to the physical address of the entire text portion of the application task to be executed.

  According to the switching of the application task, there may be provided a step of switching the allocation of the TLB to a predetermined area to the physical address of the data part of the application task to be executed.

  There may be provided a step of accumulating a history of TLB misses and a step of assigning a physical address in which frequent occurrence of TLB misses is recognized by the step of accumulating the history to a logical address of the TLB.

  According to the address mapping method of the present invention, when an application task is executed, the physical address of the entire text part of the application task is fixedly assigned to the TLB, so that no TLB miss occurs during logical access to the text part. , The occurrence frequency of TLB misses can be suppressed.

The figure which shows the hardware constitutions of MMU built-in type CPU. The figure which shows an example of the entry method of a TLB mechanism. The figure which shows the switching method of a TLB entry. The timing chart which shows the switching operation | movement of a TLB entry.

  Hereinafter, an embodiment of an address mapping method according to the present invention will be described.

  FIG. 1 is a diagram illustrating a hardware configuration of an MMU built-in CPU.

  As shown in FIG. 1, the CPU 10 has a built-in MMU 1, and the MMU 1 is provided with a TLB mechanism 2. Further, the CPU 10 is provided with a control arithmetic mechanism 3 that executes an application relating to field control and safety instrumentation, and a cache memory 4.

  Further, the CPU 10 is connected to the main memory 5 via the memory bus 6.

  FIG. 2 is a diagram illustrating an example of an entry method of the TLB mechanism.

  As shown in FIG. 2, “task A” which is an application task related to field control or safety instrumentation is divided into a text part and a data part and held in the main memory 5. The text part is the program body of task A, and the data part is composed of data such as variables and arrays other than the program body of task A.

  As shown in FIG. 2, in this embodiment, a part of the entry of the TLB mechanism 2 is secured as the task text part dedicated entry 21. Also, the page size is designated for the dedicated entry 21 so that the entire text part of task A can be accommodated (16 MB in the example of FIG. 2), and the logical address and the physical address on the main memory 5 are set in association with each other .

  Furthermore, in order to prevent the dedicated entry 21 from being changed when a TLB miss hit occurs, the OS locks the dedicated entry 21 and manages the TLB mechanism 2 so that it is not changed. Therefore, the address of the text part is not erased from the TLB mechanism 2 including the area that has not been accessed for a long time.

  On the other hand, for the data part of task A, since the setting change to the TLB mechanism 2 is performed when a miss hit occurs, the address of the data part assigned to the entry of the TLB mechanism 2 dynamically changes.

  In this way, in this embodiment, since the entire area of the text part of task A is fixed to the TLB mechanism 2, no TLB miss occurs even if any area of the text part is logically accessed. As a result, TLB misses can be greatly reduced, and the CPU resources previously allocated to exception handler processing at the time of TLB misses can be used for original processing related to field control such as control computation or safety instrumentation. As a result, the performance of the system can be improved.

  In the above embodiment, the entire text portion is accommodated in a single entry, but it may be divided into a plurality of entries. In this case, the address of the entire text portion can be held in the TLB mechanism by locking all the plurality of entries.

  FIG. 3 is a diagram showing a TLB entry switching method when an application task is executed as a multitask. Normally, in a system related to field control and safety instrumentation, there are a plurality of application tasks in the system, and the real-time OS switches tasks and executes processing in multitasking.

  FIG. 3 shows an example in which task A and task B are switched and executed as application tasks. In this case, the entire text part of task A must be set in the TLB mechanism 2 while task A is being executed, and the entire text part of task B must be set in the TLB mechanism 2 while task B is being executed. Therefore, when the task A is executed, the entire text portion of the task A is accommodated in the dedicated entry 21, and during the execution of the task A, the dedicated entry 21 is locked to prevent the change. Similarly, the entire text portion of task B is accommodated in dedicated entry 21 when task B is executed, and dedicated entry 21 is locked while task B is being executed.

  FIG. 4 is a timing chart showing the operation in this case.

  As shown in FIG. 4, in this embodiment, the contents of the dedicated entry 21 of the TLB mechanism 2 are changed at the timing when the OS switches the task context.

For example, when switching from task A to task B, the OS executes the following processing.
(Step # 1) An interrupt occurs during the execution of task A, and the process moves to the OS.
(Step # 2) The OS performs a switching process from task A to task B. At this time, the OS sets the entire text area of task B for the dedicated entry 21 of the TLB mechanism 2 where the entire text area of task A has been set (FIG. 3).
(Step # 3) The OS dispatches task B (starts execution).
(Step # 4) The execution of task B is started. At this time, since the entire text portion area of task Bn is already set in the TLB mechanism 2, no TLB miss occurs in the logical access to the text portion of task B.

  Similarly, when switching from task B to task A, the entire text part area of task A is set for the dedicated entry 21 of the TLB mechanism 2 instead of the entire text part area of task B.

  In this way, by setting the text portion of the task corresponding to the TLB mechanism 2 at the time of task switching, it is possible to avoid a TLB miss in the logical access to the text portion and improve the system performance.

  In the present embodiment, an example in which only the text portion set in the TLB mechanism 2 is switched has been shown. However, when the data constituting the data portion is greatly different among a plurality of application tasks, the TLB mechanism 2 is switched when switching tasks. The data part set in (1) may be switched simultaneously with the text part. For example, the TLB mechanism 2 is provided with a specific entry group range for setting a data part, the task A data part is executed when the task A is executed, the task B data part is executed when the task B is executed, Should be set. In this case, since the address of the data part set in the TLB mechanism 2 is always optimized for the task being executed, TLB misses can be further suppressed.

  In contrast to the above embodiments, a TLB miss analysis mechanism can be added to the OS.

The operation of the TLB miss analysis mechanism is shown below.
(1) If a TLB miss occurs, leave the address in the log.
(2) When a log is accumulated to some extent, an area of an address where TLB misses frequently occur in a certain past period is extracted.
(3) The extracted address area is held in the TLB mechanism, and the change is prevented by locking this holding area.
(4) When (1) to (3) are repeated and a region where TLB misses occur more frequently than the previously extracted region is extracted, a newly extracted region is used instead of the previous region. Is set in the holding area of the TLB mechanism, and this holding area is locked.

  Such a TLB miss analysis mechanism can effectively suppress the number of TLB misses even when the occurrence location of a TLB miss changes, such as in a system in which the memory usage changes dynamically.

  In the case of multitask operation, the TLB miss hit analysis is independently executed for each task, so that the address set in the TLB mechanism can be optimized for each task.

  The scope of application of the present invention is not limited to the above embodiment. The present invention can be widely applied to an address mapping method in TLB for converting a logical address into a physical address.

2 TLB mechanism (TLB)
10 CPU

Claims (4)

In an address mapping method in TLB for converting a logical address into a physical address,
Providing an area that can accommodate the entire text portion of the application task as a logical address of the TLB;
A fixed assignment of the physical address of the entire text portion to the area when executing the application task;
An address mapping method comprising: The address mapping method according to claim 1, further comprising a step of switching allocation to the area to a physical address of the entire text portion of the application task to be executed in response to switching of the application task. . 3. The address according to claim 2, further comprising a step of switching allocation of the TLB to a predetermined area to a physical address of a data part of the application task to be executed in response to switching of the application task. Mapping method. Accumulating a history of TLB misses;
Assigning a physical address in which frequent occurrence of TLB misses is recognized by the step of accumulating the history to a logical address of the TLB;
The address mapping method according to claim 1, further comprising:

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