JP2010182869A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device capable of dissolving a decrease in yields caused by polishing waste produced during CMP processing. <P>SOLUTION: A semiconductor substrate is provided in which an insulating film 21 is formed on one surface side, a concave 22a is provided on the outermost circumference of the insulating film, and a metallic layer 24 fills in the concave and covers the insulating film 21. A part of the metallic layer buried in the concave portion is removed, while feeding polishing liquid containing oxidant to the substrate and removing the metallic layer covering the one surface by the chemical mechanical polish processing. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  Conventionally, there is a CMP method as a method for planarizing the surface of an insulating film or the like formed on a semiconductor substrate. The planarization process by the CMP method is performed, for example, in an element isolation formation process using an STI (Shallow Trench Isolation) technique, a multistage wiring formation process using Cu, W, or the like called a damascene process.

  FIG. 8 shows a CMP apparatus used when performing the CMP method. In FIG. 8A, reference numeral 121 denotes a polishing head, reference numeral 122 denotes a semiconductor substrate, reference numeral 123 denotes a retainer ring, reference numeral 124 denotes a membrane made of neoprene rubber, and reference numeral 125 denotes a polishing pad. , 126 indicates a peripheral pressurizing unit, 128 indicates a dresser, and 129 indicates a platen. Moreover, in FIG.8 (b), the code | symbol 127 has shown the slurry supply port.

  In order to polish the semiconductor substrate 122 using the CMP apparatus shown in FIG. 8A, first, the semiconductor substrate 122 is chucked inside the retainer ring 123 in the polishing head 121 and polished on the platen 129. Transport onto the pad 125. Next, the polishing pad 125 is dressed by the dresser 128. Next, slurry is supplied from the slurry supply port 127 and the polishing pad 125 is rotated to diffuse the slurry over the entire surface of the polishing pad 125. Next, the polishing head 121 is lowered onto the rotating polishing pad 125, and the retainer ring 123 is brought into contact with the polishing pad 125. Thereafter, the air chamber separated by the membrane 124 in the polishing head 121 is pressurized. As a result, the membrane 124 swells, a load is applied to the entire surface of the semiconductor substrate 122, and the surface of the semiconductor substrate 122 is polished. When the semiconductor substrate 122 is polished, the amount of pressurization of the peripheral pressure unit 126 is adjusted so that the polishing is uniformly performed over the entire surface of the semiconductor substrate 122.

FIG. 9 shows a state in which polishing processing by the CMP method is performed on an actual object to be polished. In FIG. 9A, an insulating film 116 such as a SiO ₂ film is laminated on a semiconductor substrate (not shown). The insulating film 116 is provided with a plurality of recesses 116a. A TiN / Ti film 117 is laminated on the surfaces of the insulating film 116 and the recess 116a. Further, a W film (tungsten film) 118 is formed so as to fill the recess 116 a and cover the surface of the insulating film 116.
When the polishing process by the CMP method is performed on the semiconductor substrate shown in FIG. 9A to remove a part of the TiN / Ti film 117 and the W film 118 to expose the insulating film 116 on the surface, FIG. As shown in FIG. 4, it is ideal that the W film 118 and the TiN / Ti film 117 are removed on the upper surface of the insulating film 116 so that the polished surfaces of the W film 118 and the insulating film 116 are flat over the entire surface. is there.

However, in practice, as shown in FIG. 10, a recess having a depth indicated by a symbol A is generated in the central portion of the insulating film 116. The depth A is about 20 nm at the maximum. Such a phenomenon is called erosion. Erosion is a W film having a high polishing rate because the selection ratio of the W film 118 and the insulating film (SiO ₂ film) 116 is different (W: SiO ₂ = 100: 1) in a place where the existence density of the W film 118 is high. This is a phenomenon that occurs because the insulating film (SiO ₂ film) 116 is polished together with 118. In addition, when the void 118a as shown in FIG. 11 is present in the W film 118, when the upper portion of the void is opened after the CMP process, foreign matter 114 such as polishing dust enters the void 118a as shown in FIG. As a result, there arises a problem that yield decreases.

JP 2000-2182 A JP 2003-273051 A JP 2004-31570 A

  Patent Documents 1 to 3 disclose means for preventing erosion in the CMP method. However, even with these means, there has been a problem that yield reduction due to polishing dust or the like cannot be solved.

The method for manufacturing a semiconductor device of the present invention provides a semiconductor substrate in which an insulating film is formed on one side, a recess is provided on the outermost peripheral portion of the insulating film, and a metal layer is formed to fill the recess and cover the insulating film. Then, while supplying a polishing liquid containing an oxidizing agent, the metal layer covering the one surface is removed by chemical mechanical polishing, and a part of the metal layer embedded in the recess is removed.
In the semiconductor device manufacturing method of the present invention, an insulating film is formed on one side, a recess is provided on the outermost peripheral portion of the insulating film, and a metal layer that fills the recess and covers the insulating film is formed. The semiconductor substrate is chemically machined under the condition that the metal layer covering the one surface is removed and a part of the metal layer embedded in the recess is removed while supplying a polishing liquid containing an oxidizing agent. Polishing.

  According to the method for manufacturing a semiconductor device of the present invention, it is possible to eliminate a decrease in yield due to polishing dust or the like.

FIG. 1 is a schematic plan view showing a semiconductor substrate used in a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 2 is a cross-sectional view showing a main part of the semiconductor substrate of FIG. FIG. 3 is a schematic plan view showing the main part of the semiconductor substrate of FIG. 4A and 4B are views showing a CMP apparatus used in the method for manufacturing a semiconductor device according to an embodiment of the present invention, wherein FIG. 4A is a side sectional view and FIG. 4B is a plan view. FIG. 5 is a view showing a main part of a semiconductor substrate processed by the method for manufacturing a semiconductor device according to an embodiment of the present invention, wherein (a) is a schematic cross-sectional view showing a state immediately after processing, (b) ) Is a schematic cross-sectional view showing a state in which polishing scraps are captured. FIG. 6 is a schematic plan view showing another example of the main part of the semiconductor substrate used in the method for manufacturing a semiconductor device according to the embodiment of the present invention. FIG. 7 is a schematic plan view showing another example of the main part of the semiconductor substrate used in the method for manufacturing a semiconductor device according to the embodiment of the present invention. 8A and 8B are schematic views showing a CMP apparatus used in a conventional method for manufacturing a semiconductor device, wherein FIG. 8A is a sectional view and FIG. 8B is a plan view. 9A and 9B are process diagrams for explaining a conventional method for manufacturing a semiconductor device, in which FIG. 9A is a cross-sectional view of a semiconductor substrate before polishing treatment, and FIG. 9B is a cross-sectional view of a semiconductor substrate after polishing treatment. It is sectional drawing which shows the state polished by ideal. FIG. 10 is a cross-sectional view of a semiconductor substrate after a conventional polishing process, showing a state in which the semiconductor substrate is actually polished. FIG. 11 is a process diagram illustrating a conventional method for manufacturing a semiconductor device, and is a cross-sectional view showing another example of a semiconductor substrate before polishing. FIG. 12 is a schematic cross-sectional view illustrating a problem when the semiconductor substrate of FIG. 10 is polished.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
The method for manufacturing a semiconductor device of the present invention prepares a semiconductor substrate that has been subjected to predetermined processing, and performs chemical mechanical polishing on the semiconductor substrate, thereby causing excessive erosion in the outermost peripheral portion of the semiconductor substrate. The metal layer in the recess in the outermost periphery of the insulating film of the semiconductor substrate is partially removed. Furthermore, polishing debris generated by chemical mechanical polishing is captured in a recess on the insulating film formed by removing a part of the metal layer. Details will be described below.

  First, as shown in FIG. 1, a semiconductor substrate 1 is prepared. A plurality of semiconductor chips 2 including semiconductor devices are formed on the semiconductor substrate 1. The semiconductor chip 2 is divided into a plurality of effective chips 2 a and a plurality of ineffective chips 2 b formed near the end 1 a of the semiconductor substrate 1. Here, the effective chip 2 a refers to a semiconductor chip 2 that is built in one semiconductor substrate 1 and that is entirely contained in the semiconductor substrate 1. Further, the non-effective chip 2 b refers to a chip in which only a part of the chip is accommodated in the semiconductor substrate 1 among the semiconductor chips 2 formed in one semiconductor substrate 1. The semiconductor substrate 1 shown in FIG. 1 includes an effective chip region 12a that is a formation region of the effective chip 2a, a non-effective chip region 12b that is a formation region of the non-effective chip 2b and is located outside the effective chip region 12a. It is divided into. The non-effective chip area 12 b is an annular area surrounding the effective chip area 12 a and is provided on the outermost peripheral portion 1 b of the semiconductor substrate 1. Among the effective chips 2a, a semiconductor chip located on the outermost peripheral portion 1b side of the effective chip region 12a is particularly referred to as an outermost peripheral effective chip 2c. The outermost peripheral effective chip 2c is adjacent to the non-effective chip 2b.

  Next, FIG. 2 shows a cross-sectional view of the semiconductor substrate 1. FIG. 2 shows an insulating film 21 made of silicon oxide or the like laminated on the semiconductor substrate 1. The insulating film 21 is formed on almost the entire surface of the semiconductor substrate 1 by a CVD method or the like so as to cover a semiconductor device such as a transistor (not shown) provided on the semiconductor substrate 1. The insulating film 21 is provided with a plurality of recesses 22. The recess 22 is formed by a photolithography technique and an etching technique. The recess 22 is provided not only on the insulating film 21 on the outermost peripheral portion 1 b of the semiconductor substrate 1 but also on the entire surface of the insulating film 21. That is, the recess 22 is provided in a portion other than the outermost peripheral portion of the insulating film 21. Of the recesses 22, the recesses 22 disposed on the outermost peripheral portion 1 b of the semiconductor substrate 1 are referred to as dummy recesses 22 a. When patterning the recesses with a stepper, in order to use the same reticle, a recess corresponding to the dummy recess 22a is also formed in the effective chip 2a in the effective chip region 12a. However, even in this case, excessive erosion is caused only by the dummy recess 22a disposed in the outermost peripheral portion 1b of the semiconductor substrate 1, and excessive erosion is generated in the dummy recess 22a formed in the effective chip 2a. Does not occur. For the same reason as described above, the recesses 22 other than the dummy recesses 22a are formed in both the effective chip region 12a and the non-effective chip region 12b. The dummy recess 22a has the same depth, shape, and the like as the recess 22 except that the formation position is a specific position.

  As shown in FIG. 2, a TiN film / Ti film laminated film 23 is formed as a barrier metal on the inner surfaces of the recess 22 and the dummy recess 22a. The laminated film 23 is also formed on the one surface 21 a of the insulating film 21. Further, the laminated film 23 is formed with a metal layer 24 that fills the recess 22 and the dummy recess 22 a and covers the insulating film 21. The metal layer 24 is made of, for example, a W film (tungsten film).

FIG. 3 shows a partially enlarged view of the non-effective chip region 12b. A cross-sectional view corresponding to the line XX ′ in FIG. 3 is the cross-sectional view in FIG. In FIG. 3, a boundary portion that partitions the ineffective chip 2 b is indicated by a one-dot chain line L ₁ . In addition, the direction of the end 1a of the semiconductor substrate 1 with respect to the ineffective chip 2b shown in FIG. As shown in FIG. 3, a recess 22 and a dummy recess 22a are formed in the ineffective chip 2b. The dummy recess 22 a is provided in the ineffective chip 2 b along the boundary portion L ₁ of the ineffective chip 2 b adjacent to the end 1 a of the semiconductor substrate 1. In Figure 3, it has a plurality of holes 22b provided along the boundary L ₁ and dummy recess 22a. In addition, although illustration is abbreviate | omitted in FIG. 3, the recessed part 22 and the recessed part corresponding to the dummy recessed part 22a are formed in the effective chip | tip 2a. A recess corresponding to the dummy recess 22a is provided at the boundary of the effective chip 2a.

  As described above, the semiconductor substrate 1 in which the insulating film 21 is formed on the one surface side, the dummy concave portion 22a is provided in the outermost peripheral portion of the insulating film 21, and the metal layer 24 that fills the dummy concave portion 22a and covers the insulating film 21 is formed. Prepare.

  Next, a chemical mechanical polishing process (hereinafter referred to as a CMP (Chemical Mechanical Polish) process) is performed on the prepared semiconductor substrate 1. FIG. 4 shows a CMP apparatus used when performing the CMP process. A CMP apparatus 31 shown in FIG. 4A includes a platen 32 that is rotatable about a rotation shaft 32a, a polishing pad 33 that is affixed on the platen 32, and a polishing pad 33 that is placed on the polishing pad 33 for polishing. A dresser 34 for dressing the pad 33 and a polishing head 35 for holding the semiconductor substrate 1 and pressing the semiconductor substrate 1 against the polishing pad 33 are provided. As the polishing pad 33, for example, a polishing pad 33 made of polyurethane is used. The polishing head 35 includes a retainer ring 37 adjacent to the outermost peripheral portion 1 b of the semiconductor substrate 1, a peripheral pressure portion 38 that adjusts the pressing force against the outermost peripheral portion 1 b of the semiconductor substrate 1, and a pressing force on the entire surface of the semiconductor substrate 1. And a membrane 39 made of neoprene rubber or the like for adjusting the pressure. Further, as shown in FIG. 4B, a slurry supply port 40 for supplying a polishing liquid is provided in the substantially central portion of the polishing pad 33.

  Next, the CMP process of the semiconductor substrate 1 using the CMP apparatus 31 shown in FIG. 4 will be described. First, the semiconductor substrate 1 is chucked inside the retainer ring 37 of the polishing head 35 with the metal layer 24 facing down. Next, the semiconductor substrate 1 is transferred onto the polishing pad 33 attached on the platen 32. Next, the polishing pad 33 is dressed by the dresser 34. Next, a polishing liquid containing an oxidizing agent is supplied from the slurry supply port 40, the polishing pad 33 is rotated together with the platen 32, and the polishing liquid is diffused over the entire surface of the polishing pad 33 by the action of centrifugal force generated by the rotation. Next, the polishing head 35 is lowered together with the semiconductor substrate 1 on the rotating polishing pad 33, and the retainer ring 37 is brought into contact with the polishing pad 33. Thereafter, the inside of the air chamber separated by the membrane 39 in the polishing head 35 is pressurized. As a result, the membrane 39 swells, a load is applied to the entire surface of the semiconductor substrate 1, and the semiconductor substrate 1 is polished while the semiconductor substrate 1 is moved relative to the polishing pad 33.

The processing conditions of the CMP process are a process of removing the metal layer 24 covering the one surface 21a of the insulating film 21 and removing a part of the metal layer 24 embedded in the dummy recess 22a while supplying a polishing liquid containing an oxidizing agent. Perform under conditions. That is, it is performed under conditions that cause excessive erosion in the outermost peripheral portion of the semiconductor substrate. For example, hydrogen peroxide is preferable as the oxidizing agent contained in the polishing liquid. The polishing liquid preferably contains silica in deionized water as an abrasive.
This processing condition is different from the conventional condition (the condition that does not cause excessive erosion) in which the metal layer 24 covering the one surface 21a of the insulating film 21 is removed but the metal layer 24 buried in the dummy recess 22a is not removed. The conditions are such that the concentration of the oxidant is increased. The polishing liquid preferably contains an oxidizing agent, and the content of the oxidizing agent in the polishing liquid in this embodiment may be higher than the conventional concentration. For example, when the oxidant concentration in the conventional condition in which the metal layer 24 buried in the dummy recess 22a is not removed is 2% by mass, in this embodiment, the oxidant concentration is in the range of 3 to 5% by mass. Good.

  Further, as another processing condition, a condition in which the pressing force of the polishing pad 33 by the retainer ring 27 is increased with respect to a condition that does not cause excessive erosion. For example, when the pressing force of the retainer ring 37 is 200 hPa under a condition that does not cause excessive erosion, the pressing force may be in the range of 200 to 300 hPa in this embodiment.

  Further, another processing condition is a condition in which the relative movement speed between the polishing pad 33 and the semiconductor substrate 1 is increased with respect to a condition that does not cause excessive erosion. For example, when the rotation speed of the platen 32 under the condition that does not cause excessive erosion is 90 rpm, the rotation speed may be in the range of 100 to 120 rpm in the present embodiment.

  By performing the CMP process on the semiconductor substrate 1 under the above processing conditions, the metal layer 24 covering the one surface 21a of the insulating layer 21 is removed and embedded in the dummy recess 22a as shown in FIG. A part of the metal layer 24 is removed. In this way, excessive erosion occurs in the dummy recess 22a. When the erosion depth B (depth corresponding to the reference A in FIG. 10) generated in the normal CMP process shown by reference B in FIG. 5A is 15 nm, the excess erosion depth C shown in reference C is: This is about 4 times that of about 60 nm. Due to the excessive erosion, the metal layer 24 embedded in the dummy recess 22a is partially removed, so that a recess 21b is provided in the insulating film 21. Polishing waste 51 generated by the subsequent CMP process is captured in the recess 21b.

  On the other hand, in the recesses 22 other than the dummy recess 22a, only the metal tank 24 on the one surface 21a of the insulating film 21 is removed without causing excessive erosion, and the metal layer 24 in the recess 22 remains as it is. This remaining metal layer 24 is used as, for example, a contact plug of a semiconductor device. The recesses other than the dummy recess 22a include a recess corresponding to the dummy recess 22a provided in the effective chip region 12a. Since excessive erosion does not occur in this recess, the metal layer 24 remains as it is, but since this recess is equivalent to the dummy recess 22a, it is not used for a contact plug or the like.

  As described above, by changing the processing conditions of the CMP process from the conventional conditions, the excessive erosion part (recessed part 21b) as shown in FIG. It can be formed on the peripheral non-effective chip 2b. This uses a deviation in polishing conditions between the non-effective chip 2b and the outermost peripheral effective chip 2c inside. That is, in the non-effective chip 2b located on the outermost periphery, the polishing liquid dropped on the polishing pad 33 is first consumed as an abrasive, so that the oxidizing action of the metal layer 24 by the oxidizing agent contained in the polishing liquid is first performed. Will work. On the other hand, the outermost peripheral effective chip 2c on the inner side has already deteriorated because the oxidizing agent has acted on the non-effective chip 2b, so that the oxidizing action is less than that on the non-effective chip 2b. Increasing the oxidant concentration further widens the difference in the degree of oxidation between the non-effective chip 2b and the other parts, thereby improving the oxidation function of the non-effective chip 2b. Further, by improving the pressing force of the retainer ring 37 and the rotation speed of the platen 32, the frictional heat between the retainer ring 37 and the polishing pad 33 is increased, and the oxidizing action of the ineffective tip 2b in the vicinity of the retainer ring 37 is amplified, and the metal Layer 24 is easily polished. In this way, excessive erosion occurs, and the recess 21b is formed.

In addition, the recessed part provided in the outermost periphery part of a semiconductor substrate is not limited to what is shown in FIG.
For example, as shown in FIG. 6, the recess 22 and the dummy recess 122a are formed in the non-effective chip 2b. The dummy recess 122a is provided in the non-effective chip 2b along the boundary _{L 1} of the non-effective chip 2b. Then, the dummy recess 122a is a groove 122b provided along the boundary _{L 1.} As described above, the dummy recess 122a may be a groove.
Further, as shown in FIG. 7, the dummy recess 222a, it may be provided on the dicing line L ₂ or on the scribe line L ₃ of the non-effective chip 2b. Dummy recess 222a in this case may also plurality of holes 222b provided along the dicing line L ₂ or the scribe line L ₃ as shown in FIG. 7, provided along the upper dicing line L ₂ or the scribe line L ₃ It may be a groove.
In the example shown in FIGS. 6 and 7, the dummy recess 22a and the recess 22 are also formed in the effective chip 2a as in the case of FIG. 3, but excessive erosion occurs in the dummy recess 22a of the effective chip 2a. I won't let you.

As described above, according to the manufacturing method of the semiconductor device of the present embodiment, the metal layer 24 covering the insulating film 21 is removed and the metal embedded in the dummy recess 22a while supplying the polishing liquid containing the oxidizing agent. Excessive erosion can be generated in the outermost peripheral portion 1b of the semiconductor substrate by chemically and mechanically polishing the semiconductor substrate 1 under the condition that a part of the layer 24 is removed.
Further, while supplying the polishing liquid containing the oxidizing agent, the metal layer covering the insulating film 21 is removed by chemical mechanical polishing and a part of the metal layer 24 embedded in the dummy recess 22a is removed. The polishing scraps 51 can be captured in the recesses formed by removing 24.
By capturing the polishing debris 51 generated by chemical mechanical polishing in the recess 21b on the insulating film 21 generated by excessive erosion, the generation of defects associated with the CMP process can be suppressed and the yield can be improved.

Further, as a condition for the chemical mechanical polishing, the oxidant concentration in the polishing liquid is increased compared to the condition in which the metal layer 24 covering the insulating film 21 is removed but the metal layer 24 buried in the dummy recess 22a is not removed. By satisfying these conditions, the difference in polishing conditions between the dummy recess 22a in the outermost peripheral portion 1b and the recess adjacent to the dummy recess 22a increases, and excessive erosion can be caused in the dummy recess.
Further, by increasing the pressing force of the retainer ring 37 or increasing the relative movement speed between the polishing pad 33 and the semiconductor substrate 1, the dummy recess 22a in the outermost peripheral portion 1b and the recess adjacent to the dummy recess 22a can be reduced. The difference in polishing conditions between the two becomes larger, and excessive erosion can be caused in the dummy recesses.

Further, according to the semiconductor device manufacturing method of the present embodiment, the semiconductor substrate 1 is partitioned into the effective chip region 12a and the non-effective chip region 12b, and the dummy recess 22a is provided in the non-effective chip region 12b. Since excess erosion is caused with respect to 22a, there is no possibility of causing excessive erosion in the effective chip in the effective chip region 12a, and the yield of the semiconductor device can be improved.
Further, a dummy recess 22a provided along the non-effective chip 2b boundary L ₁ of the adjacent end 1a of the semiconductor substrate 1, so causing excessive erosion against the dummy recess 22a, causing excessive erosion dummy The recess 22a is limited to the outermost periphery side of the semiconductor substrate 1, and excessive erosion can be prevented from expanding.
Further, in any case, the distance between the dummy recesses 22a and 122a shown in FIG. 3 or FIG. 6 and the inner recess 22 is arbitrary. Thus as shown in FIG. 7, there is no need to install a dummy recess 222a in the non-effective chip 2b, it is provided dummy recess 222a in the scribe line L ₂ or dicing lines L ₃ near the end portion 1a of the semiconductor substrate 1, It is possible to fulfill that role. By doing so, it is possible to reduce the chip area.

  Since the polishing pad 33 in the CMP process is an elastic body, if the polishing target film is in a dense mixed state with two or more kinds of films (metal layer 24 and insulating film 21) and there is a difference in the polishing selection ratio, the erosion film The decrease is an unavoidable phenomenon. Further, since polishing scraps 51 such as the semiconductor substrate 1 and the polishing pad 32 are scattered on the polishing pad 33, transfer onto the semiconductor substrate 1 is unavoidable. In the present invention, a dummy recess 22a is disposed in the peripheral portion of the recess 22, a deep hole (recessed portion 21b) is formed by utilizing an excessive erosion phenomenon, and the polishing waste 51 is captured by the deep hole, thereby generating a defect. The rate can be reduced. Since the void depth is shortened by deepening the holes, it is easy to clean and remove the trapped polishing debris 51 and it is not brought into the next process.

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 1a ... End of semiconductor substrate, 1b ... Outermost peripheral part, 2a ... Effective chip, 2b ... Non-effective chip, 12a ... Effective chip area, 12b ... Non-effective chip area, 21 ... Insulating film, 21b ... Recessed portion, 22 ... recessed portion, 22a ... dummy recessed portion (recessed portion), 22b, 222b ... hole portion, 24 ... metal layer, 33 ... polishing pad, 35 ... polishing head, 37 ... retainer ring, 51 ... polishing scrap, 122b ... groove portion , L ₁ ... Ineffective chip boundary, L ₂ ... Scribe line, L ₃ ... Dicing line

Claims (12)

An insulating film is formed on one surface side, a concave portion is provided on the outermost peripheral portion of the insulating film, and a semiconductor substrate is prepared in which a metal layer that fills the concave portion and covers the insulating film is formed,
A semiconductor device characterized in that, while supplying a polishing liquid containing an oxidizing agent, a metal layer covering the one surface is removed by chemical mechanical polishing and a part of the metal layer embedded in the recess is removed. Production method. An insulating film is formed on one surface side, a concave portion is provided on the outermost peripheral portion of the insulating film, and a semiconductor substrate is prepared in which a metal layer that fills the concave portion and covers the insulating film is formed,
The semiconductor substrate is chemically and mechanically polished under the condition that the metal layer covering the one surface is removed and a part of the metal layer embedded in the recess is removed while supplying a polishing liquid containing an oxidizing agent. A method of manufacturing a semiconductor device.   2. The polishing debris generated by the chemical mechanical polishing is captured in a recess on the insulating film formed by removing a part of the metal layer embedded in the recess. A method for manufacturing a semiconductor device according to claim 2.   The condition in claim 2 is a condition in which the oxidant concentration in the polishing liquid is increased with respect to a condition in which the metal layer covering the one surface is removed but the metal layer buried in the recess is not removed. A method of manufacturing a semiconductor device.   Chemical mechanical polishing of the semiconductor substrate using a polishing head that holds the semiconductor substrate and has a retainer ring adjacent to the outermost peripheral portion of the semiconductor substrate, and a polishing pad that moves relative to the polishing head The condition in which the pressing force of the retainer ring is increased with respect to the condition in which the metal layer covering the one surface is removed but the metal layer buried in the recess is not removed. Item 5. The method for manufacturing a semiconductor device according to Item 2 or Item 4.   As a condition at the time of chemical mechanical polishing the semiconductor substrate, the metal pad covering the one surface is removed but the metal layer buried in the recess is not removed. 6. The method of manufacturing a semiconductor device according to claim 2, wherein the relative movement speed is increased.   The semiconductor substrate is partitioned into an effective chip area which is an effective chip forming area and an ineffective chip area which is an ineffective chip forming area and is located outside the effective chip area, and the recess is the ineffective chip area. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is provided in a chip region.   8. The method of manufacturing a semiconductor device according to claim 7, wherein the recess is provided in the ineffective chip along a boundary portion of the ineffective chip adjacent to an end portion of the semiconductor substrate.   The method of manufacturing a semiconductor device according to claim 8, wherein the recess is a groove or a plurality of holes provided along the boundary.   8. The method of manufacturing a semiconductor device according to claim 7, wherein the recess is provided on a scribe line or a dicing line of the ineffective chip.   The method of manufacturing a semiconductor device according to claim 10, wherein the recess is a groove or a plurality of holes provided along the scribe line or the dicing line.   3. The method of manufacturing a semiconductor device according to claim 1, wherein the recess is further provided on the entire surface of the insulating film other than the outermost periphery, and the recess provided on the outermost periphery is a dummy recess. .

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